From f25f64ed5bd3c2932493681bdfdb483ea707da0a Mon Sep 17 00:00:00 2001 From: Juergen Beisert Date: Sun, 22 Jul 2007 11:12:38 +0200 Subject: x86: Replace NSC/Cyrix specific chipset access macros by inlined functions. Due to index register access ordering problems, when using macros a line like this fails (and does nothing): setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88); With inlined functions this line will work as expected. Note about a side effect: Seems on Geode GX1 based systems the "suspend on halt power saving feature" was never enabled due to this wrong macro expansion. With inlined functions it will be enabled, but this will stop the TSC when the CPU runs into a HLT instruction. Kernel output something like this: Clocksource tsc unstable (delta = -472746897 ns) This is the 3rd version of this patch. - Adding missed arch/i386/kernel/cpu/mtrr/state.c Thanks to Andres Salomon - Adding some big fat comments into the new header file Suggested by Andi Kleen AK: fixed x86-64 compilation Signed-off-by: Juergen Beisert Signed-off-by: Andi Kleen Signed-off-by: Linus Torvalds --- include/asm-x86_64/processor.h | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'include/asm-x86_64') diff --git a/include/asm-x86_64/processor.h b/include/asm-x86_64/processor.h index a1645bbc03bd..19525175b91c 100644 --- a/include/asm-x86_64/processor.h +++ b/include/asm-x86_64/processor.h @@ -389,17 +389,6 @@ static inline void prefetchw(void *x) #define cpu_relax() rep_nop() -/* - * NSC/Cyrix CPU indexed register access macros - */ - -#define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); }) - -#define setCx86(reg, data) do { \ - outb((reg), 0x22); \ - outb((data), 0x23); \ -} while (0) - static inline void serialize_cpu(void) { __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx"); -- cgit v1.2.2