From d1acb4210aaa9bdc413d276dbc96d0a23ada97ba Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Fri, 16 Mar 2007 17:20:28 -0700 Subject: [SPARC64]: Get DEBUG_PAGEALLOC working again. We have to make sure to use base-pagesize TLB entries even during the early transition period where we need TLB miss handling but don't have the kernel page tables setup yet for the linear region. Also, it is necessary therefore to not use the 4MB TSB for these translations, and instead use the normal kernel TSB. This allows us to also get rid of the 4MB tsb for debug builds which shrinks the kernel a little bit. Signed-off-by: David S. Miller --- include/asm-sparc64/tsb.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/asm-sparc64') diff --git a/include/asm-sparc64/tsb.h b/include/asm-sparc64/tsb.h index e82612cd9f33..ab55ffcb7bf4 100644 --- a/include/asm-sparc64/tsb.h +++ b/include/asm-sparc64/tsb.h @@ -264,6 +264,7 @@ extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end; be,a,pt %xcc, OK_LABEL; \ mov REG4, REG1; +#ifndef CONFIG_DEBUG_PAGEALLOC /* This version uses a trick, the TAG is already (VADDR >> 22) so * we can make use of that for the index computation. */ @@ -277,5 +278,6 @@ extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end; cmp REG3, TAG; \ be,a,pt %xcc, OK_LABEL; \ mov REG4, REG1; +#endif #endif /* !(_SPARC64_TSB_H) */ -- cgit v1.2.2