From f4151b9ba87901eb3a7bc49f418cc352d4e1927e Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 20 Nov 2007 21:19:16 +1100 Subject: [POWERPC] 4xx: Fix TLB 0 problem with CONFIG_SERIAL_TEXT_DEBUG Right now TLB entry 0 ist used as UART0 mapping for the early debug output (via CONFIG_SERIAL_TEXT_DEBUG). This causes problems when many TLB's get used upon Linux bootup (e.g. while PCIe scanning behind bridges and/or switches on 440SPe platforms). This will overwrite the TLB 0 entry and further debug output's may crash/hang the system. This patch moves the early debug UART0 TLB entry from 0 to 62 as done in arch/powerpc. This way it is in the "pinned" area and will not get overwritten. Also the arch/ppc/mm/44x_mmu.c code is now synced with the newer code from arch/powerpc. Signed-off-by: Stefan Roese Signed-off-by: Josh Boyer --- include/asm-ppc/mmu.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include/asm-ppc') diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 14584e505ed5..d46b57b589ae 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -383,6 +383,12 @@ typedef struct _P601_BAT { #define BOOKE_PAGESZ_256GB 14 #define BOOKE_PAGESZ_1TB 15 +#ifndef CONFIG_SERIAL_TEXT_DEBUG +#define PPC44x_EARLY_TLBS 1 +#else +#define PPC44x_EARLY_TLBS 2 +#endif + /* * Freescale Book-E MMU support */ -- cgit v1.2.2