From 514ccd4e6c414d8064d53235f7fc09fc02ec2078 Mon Sep 17 00:00:00 2001 From: Vitaly Bordug Date: Fri, 16 Sep 2005 19:28:00 -0700 Subject: [PATCH] ppc32: Add ppc_sys descriptions for PowerQUICC I devices Added ppc_sys device and system definitions for PowerQUICC I devices. This will allow drivers for PQI to be proper platform device drivers. Currently sys section contains only MPC885 and MPC866. Identification should be done with identify_ppc_sys_by_name call, with board-specific "name" string passed, since PQI do not have any register that could identify the SOC. Signed-off-by: Vitaly Bordug Signed-off-by: Kumar Gala Signed-off-by: Marcelo Tosatti Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/asm-ppc/irq.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include/asm-ppc/irq.h') diff --git a/include/asm-ppc/irq.h b/include/asm-ppc/irq.h index 55752474d0d9..bd9674807f05 100644 --- a/include/asm-ppc/irq.h +++ b/include/asm-ppc/irq.h @@ -138,6 +138,16 @@ irq_canonicalize(int irq) #define SIU_IRQ7 (14) #define SIU_LEVEL7 (15) +#define MPC8xx_INT_FEC1 SIU_LEVEL1 +#define MPC8xx_INT_FEC2 SIU_LEVEL3 + +#define MPC8xx_INT_SCC1 (CPM_IRQ_OFFSET + CPMVEC_SCC1) +#define MPC8xx_INT_SCC2 (CPM_IRQ_OFFSET + CPMVEC_SCC2) +#define MPC8xx_INT_SCC3 (CPM_IRQ_OFFSET + CPMVEC_SCC3) +#define MPC8xx_INT_SCC4 (CPM_IRQ_OFFSET + CPMVEC_SCC4) +#define MPC8xx_INT_SMC1 (CPM_IRQ_OFFSET + CPMVEC_SMC1) +#define MPC8xx_INT_SMC2 (CPM_IRQ_OFFSET + CPMVEC_SMC2) + /* The internal interrupts we can configure as we see fit. * My personal preference is CPM at level 2, which puts it above the * MBX PCI/ISA/IDE interrupts. -- cgit v1.2.2