From 02416dcf5a94af34bcd28b4baf25bbbf399d8136 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 15 Jun 2005 13:00:12 +0000 Subject: Redo RM9000 workaround which along with other DSP ASE changes was causing some headache for debuggers knowing about signal frames. Signed-off-by: Ralf Baechle --- include/asm-mips/war.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'include/asm-mips/war.h') diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index 04ee53b34c2e..ad374bd3f130 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -176,6 +176,17 @@ #define RM9000_CDEX_SMP_WAR 1 #endif +/* + * The RM9000 has a bug (though PMC-Sierra opposes it being called that) + * where invalid instructions in the same I-cache line worth of instructions + * being fetched may case spurious exceptions. + */ +#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \ + defined(CONFIG_PMC_YOSEMITE) +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#endif + + /* * ON the R10000 upto version 2.6 (not sure about 2.7) there is a bug that * may cause ll / sc and lld / scd sequences to execute non-atomically. @@ -187,6 +198,9 @@ /* * Workarounds default to off */ +#ifndef ICACHE_REFILLS_WORKAROUND_WAR +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#endif #ifndef R4600_V1_INDEX_ICACHEOP_WAR #define R4600_V1_INDEX_ICACHEOP_WAR 0 #endif -- cgit v1.2.2