From 9ffa73960631502841d78b79ce857b15b9290abc Mon Sep 17 00:00:00 2001 From: "Hans J. Koch" Date: Tue, 16 Oct 2007 01:28:41 -0700 Subject: pxafb: Add support for other palette formats This patch adds support for the other three palette formats possible with the PXA LCD controller. This is required on boards where an LCD is connected with all its 18 bits. With this patch, it's possible to use an 8-bit mode with 18-bit palette entries. This used to be possible in 2.4 kernels but disappeared in 2.6. With current kernels, you can only get wrong colours out of an LCD connected this way. Users can choose the palette format by doing something like this in their board definition: static struct pxafb_mach_info my_fb_info = { [...] .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg | LCCR3_PDFOR_3, .lccr4 = LCCR4_PAL_FOR_2, [...] }; Signed-off-by: Hans J. Koch Signed-off-by: Antonino Daplas Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/asm-arm/arch-pxa/pxa-regs.h | 11 +++++++++++ include/asm-arm/arch-pxa/pxafb.h | 7 ++++++- 2 files changed, 17 insertions(+), 1 deletion(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 67f53e07db86..bb68b598c436 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -1823,6 +1823,7 @@ #define LCCR1 __REG(0x44000004) /* LCD Controller Control Register 1 */ #define LCCR2 __REG(0x44000008) /* LCD Controller Control Register 2 */ #define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */ +#define LCCR4 __REG(0x44000010) /* LCD Controller Control Register 3 */ #define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */ #define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */ #define LCSR __REG(0x44000038) /* LCD Controller Status Register */ @@ -1836,6 +1837,16 @@ #define LCCR3_8BPP (3 << 24) #define LCCR3_16BPP (4 << 24) +#define LCCR3_PDFOR_0 (0 << 30) +#define LCCR3_PDFOR_1 (1 << 30) +#define LCCR3_PDFOR_2 (2 << 30) +#define LCCR3_PDFOR_3 (3 << 30) + +#define LCCR4_PAL_FOR_0 (0 << 15) +#define LCCR4_PAL_FOR_1 (1 << 15) +#define LCCR4_PAL_FOR_2 (2 << 15) +#define LCCR4_PAL_FOR_MASK (3 << 15) + #define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */ #define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */ #define FIDR0 __REG(0x44000208) /* DMA Channel 0 Frame ID Register */ diff --git a/include/asm-arm/arch-pxa/pxafb.h b/include/asm-arm/arch-pxa/pxafb.h index 81c3928d608c..ea2336aa70e4 100644 --- a/include/asm-arm/arch-pxa/pxafb.h +++ b/include/asm-arm/arch-pxa/pxafb.h @@ -70,7 +70,12 @@ struct pxafb_mach_info { * LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp */ u_int lccr3; - + /* The following should be defined in LCCR4 + * LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2 + * + * All other bits in LCCR4 should be left alone. + */ + u_int lccr4; void (*pxafb_backlight_power)(int); void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *); -- cgit v1.2.2