From a88a447d44648f1dfba4c40b3f4b6f75597150ed Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 20 Aug 2007 10:34:37 +0100 Subject: [ARM] pxa: remove get_lcdclk_frequency_10khz() get_lcdclk_frequency_10khz() is now redundant, remove it. Hide pxa27x_get_lcdclk_frequency_10khz() from public view. Signed-off-by: Russell King --- include/asm-arm/arch-pxa/hardware.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h index 386121746417..68e7b430ac80 100644 --- a/include/asm-arm/arch-pxa/hardware.h +++ b/include/asm-arm/arch-pxa/hardware.h @@ -122,7 +122,6 @@ extern void pxa_set_cken(int clock, int enable); * return current memory and LCD clock frequency in units of 10kHz */ extern unsigned int get_memclk_frequency_10khz(void); -extern unsigned int get_lcdclk_frequency_10khz(void); #endif -- cgit v1.2.2 From a7073b8b47651ce2ed27564ed8395eff81120c58 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 19 Sep 2007 09:33:55 +0100 Subject: [ARM] pxa: mark pxa_set_cken deprecated Allow the generic clock support code to fiddle with the CKEN register and mark pxa_set_cken() deprecated. Signed-off-by: Russell King --- include/asm-arm/arch-pxa/hardware.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h index 68e7b430ac80..538a34e39e92 100644 --- a/include/asm-arm/arch-pxa/hardware.h +++ b/include/asm-arm/arch-pxa/hardware.h @@ -116,7 +116,11 @@ extern void pxa_gpio_set_value(unsigned gpio, int value); /* * Routine to enable or disable CKEN */ -extern void pxa_set_cken(int clock, int enable); +static inline void __deprecated pxa_set_cken(int clock, int enable) +{ + extern void __pxa_set_cken(int clock, int enable); + __pxa_set_cken(clock, enable); +} /* * return current memory and LCD clock frequency in units of 10kHz -- cgit v1.2.2 From cd272ab01141c908ccccb068e6d38b7fcd3240ac Mon Sep 17 00:00:00 2001 From: eric miao Date: Tue, 11 Sep 2007 19:13:17 -0700 Subject: [ARM] pxa: add PXA3 cpu_is_xxx() macros Extracted from patch by Eric Miao, this adds the cpu_is_xxx() macros for identifying PXA3 SoCs. Signed-off-by: eric miao Signed-off-by: Russell King --- include/asm-arm/arch-pxa/hardware.h | 65 +++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h index 538a34e39e92..fc20d72d4844 100644 --- a/include/asm-arm/arch-pxa/hardware.h +++ b/include/asm-arm/arch-pxa/hardware.h @@ -80,6 +80,24 @@ _id == 0x411; \ }) +#define __cpu_is_pxa300(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x688; \ + }) + +#define __cpu_is_pxa310(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x689; \ + }) + +#define __cpu_is_pxa320(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x603 || _id == 0x682; \ + }) + #define cpu_is_pxa21x() \ ({ \ unsigned int id = read_cpuid(CPUID_ID); \ @@ -98,6 +116,53 @@ __cpu_is_pxa27x(id); \ }) +#define cpu_is_pxa300() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa300(id); \ + }) + +#define cpu_is_pxa310() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa310(id); \ + }) + +#define cpu_is_pxa320() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa320(id); \ + }) + +/* + * CPUID Core Generation Bit + * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x + * == 0x3 for pxa300/pxa310/pxa320 + */ +#define __cpu_is_pxa2xx(id) \ + ({ \ + unsigned int _id = (id) >> 13 & 0x7; \ + _id <= 0x2; \ + }) + +#define __cpu_is_pxa3xx(id) \ + ({ \ + unsigned int _id = (id) >> 13 & 0x7; \ + _id == 0x3; \ + }) + +#define cpu_is_pxa2xx() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa2xx(id); \ + }) + +#define cpu_is_pxa3xx() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa3xx(id); \ + }) + /* * Handy routine to set GPIO alternate functions */ -- cgit v1.2.2 From 30f0b40844e5add7ad879e2f5939ff498f72f3e6 Mon Sep 17 00:00:00 2001 From: eric miao Date: Wed, 29 Aug 2007 10:18:47 +0100 Subject: [ARM] 4559/1: pxa: make PXA_LAST_GPIO a run-time variable This definition produces processor specific code in generic function pxa_gpio_mode(), thus creating inconsistencies for support of pxa25x and pxa27x in a single zImage. As David Brownell suggests, make it a run-time variable and initialize at run-time according to the number of GPIOs on the processor. For now the initialization happens in pxa_init_irq_gpio(), since there is already a parameter for that, besides, this is and MUST be earlier than any subsequent calls to pxa_gpio_mode(). Signed-off-by: eric miao Signed-off-by: Russell King --- include/asm-arm/arch-pxa/irqs.h | 6 ------ 1 file changed, 6 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h index a07fe0f928cd..1bcc7632b46c 100644 --- a/include/asm-arm/arch-pxa/irqs.h +++ b/include/asm-arm/arch-pxa/irqs.h @@ -66,12 +66,6 @@ #define IRQ_TO_GPIO_2_x(i) ((i) - PXA_GPIO_IRQ_BASE) #define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i)) -#if defined(CONFIG_PXA25x) -#define PXA_LAST_GPIO 84 -#elif defined(CONFIG_PXA27x) -#define PXA_LAST_GPIO 127 -#endif - /* * The next 16 interrupts are for board specific purposes. Since * the kernel can only run on one machine at a time, we can re-use -- cgit v1.2.2 From 2c8086a5d073e8e72122a5b84febde236a39845b Mon Sep 17 00:00:00 2001 From: eric miao Date: Tue, 11 Sep 2007 19:13:17 -0700 Subject: [ARM] pxa: PXA3xx base support Signed-off-by: eric miao Signed-off-by: Russell King --- include/asm-arm/arch-pxa/mfp-pxa300.h | 574 ++++++++++++++++++++++++++++++++ include/asm-arm/arch-pxa/mfp-pxa320.h | 446 +++++++++++++++++++++++++ include/asm-arm/arch-pxa/mfp.h | 576 +++++++++++++++++++++++++++++++++ include/asm-arm/arch-pxa/pxa-regs.h | 2 +- include/asm-arm/arch-pxa/pxa3xx-regs.h | 75 +++++ include/asm-arm/arch-pxa/timex.h | 2 + include/asm-arm/arch-pxa/zylonite.h | 35 ++ 7 files changed, 1709 insertions(+), 1 deletion(-) create mode 100644 include/asm-arm/arch-pxa/mfp-pxa300.h create mode 100644 include/asm-arm/arch-pxa/mfp-pxa320.h create mode 100644 include/asm-arm/arch-pxa/mfp.h create mode 100644 include/asm-arm/arch-pxa/pxa3xx-regs.h create mode 100644 include/asm-arm/arch-pxa/zylonite.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/mfp-pxa300.h b/include/asm-arm/arch-pxa/mfp-pxa300.h new file mode 100644 index 000000000000..7513c7a3402d --- /dev/null +++ b/include/asm-arm/arch-pxa/mfp-pxa300.h @@ -0,0 +1,574 @@ +/* + * linux/include/asm-arm/arch-pxa/mfp-pxa300.h + * + * PXA300/PXA310 specific MFP configuration definitions + * + * Copyright (C) 2007 Marvell International Ltd. + * 2007-08-21: eric miao + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MFP_PXA300_H +#define __ASM_ARCH_MFP_PXA300_H + +#include + +/* GPIO */ +#define GPIO46_GPIO MFP_CFG(GPIO46, AF1) +#define GPIO49_GPIO MFP_CFG(GPIO49, AF3) +#define GPIO50_GPIO MFP_CFG(GPIO50, AF2) +#define GPIO51_GPIO MFP_CFG(GPIO51, AF3) +#define GPIO52_GPIO MFP_CFG(GPIO52, AF3) +#define GPIO56_GPIO MFP_CFG(GPIO56, AF0) +#define GPIO58_GPIO MFP_CFG(GPIO58, AF0) +#define GPIO59_GPIO MFP_CFG(GPIO59, AF0) +#define GPIO60_GPIO MFP_CFG(GPIO60, AF0) +#define GPIO61_GPIO MFP_CFG(GPIO61, AF0) +#define GPIO62_GPIO MFP_CFG(GPIO62, AF0) + +#ifdef CONFIG_CPU_PXA310 +#define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0) +#define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0) +#define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0) +#define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0) +#define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0) +#define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0) +#endif + +/* Chip Select */ +#define GPIO2_nCS3 MFP_CFG(GPIO2, AF1) + +/* AC97 */ +#define GPIO23_AC97_nACRESET MFP_CFG(GPIO23, AF1) +#define GPIO24_AC97_SYSCLK MFP_CFG(GPIO24, AF1) +#define GPIO29_AC97_BITCLK MFP_CFG(GPIO29, AF1) +#define GPIO25_AC97_SDATA_IN_0 MFP_CFG(GPIO25, AF1) +#define GPIO26_AC97_SDATA_IN_1 MFP_CFG(GPIO26, AF1) +#define GPIO17_AC97_SDATA_IN_2 MFP_CFG(GPIO17, AF3) +#define GPIO21_AC97_SDATA_IN_2 MFP_CFG(GPIO21, AF2) +#define GPIO18_AC97_SDATA_IN_3 MFP_CFG(GPIO18, AF3) +#define GPIO22_AC97_SDATA_IN_3 MFP_CFG(GPIO22, AF2) +#define GPIO27_AC97_SDATA_OUT MFP_CFG(GPIO27, AF1) +#define GPIO28_AC97_SYNC MFP_CFG(GPIO28, AF1) + +/* I2C */ +#define GPIO21_I2C_SCL MFP_CFG_LPM(GPIO21, AF1, PULL_HIGH) +#define GPIO22_I2C_SDA MFP_CFG_LPM(GPIO22, AF1, PULL_HIGH) + +/* QCI */ +#define GPIO39_CI_DD_0 MFP_CFG_DRV(GPIO39, AF1, DS04X) +#define GPIO40_CI_DD_1 MFP_CFG_DRV(GPIO40, AF1, DS04X) +#define GPIO41_CI_DD_2 MFP_CFG_DRV(GPIO41, AF1, DS04X) +#define GPIO42_CI_DD_3 MFP_CFG_DRV(GPIO42, AF1, DS04X) +#define GPIO43_CI_DD_4 MFP_CFG_DRV(GPIO43, AF1, DS04X) +#define GPIO44_CI_DD_5 MFP_CFG_DRV(GPIO44, AF1, DS04X) +#define GPIO45_CI_DD_6 MFP_CFG_DRV(GPIO45, AF1, DS04X) +#define GPIO46_CI_DD_7 MFP_CFG_DRV(GPIO46, AF0, DS04X) +#define GPIO47_CI_DD_8 MFP_CFG_DRV(GPIO47, AF1, DS04X) +#define GPIO48_CI_DD_9 MFP_CFG_DRV(GPIO48, AF1, DS04X) +#define GPIO52_CI_HSYNC MFP_CFG_DRV(GPIO52, AF0, DS04X) +#define GPIO51_CI_VSYNC MFP_CFG_DRV(GPIO51, AF0, DS04X) +#define GPIO49_CI_MCLK MFP_CFG_DRV(GPIO49, AF0, DS04X) +#define GPIO50_CI_PCLK MFP_CFG_DRV(GPIO50, AF0, DS04X) + +/* KEYPAD */ +#define GPIO3_KP_DKIN_6 MFP_CFG_LPM(GPIO3, AF2, FLOAT) +#define GPIO4_KP_DKIN_7 MFP_CFG_LPM(GPIO4, AF2, FLOAT) +#define GPIO16_KP_DKIN_6 MFP_CFG_LPM(GPIO16, AF6, FLOAT) +#define GPIO83_KP_DKIN_2 MFP_CFG_LPM(GPIO83, AF5, FLOAT) +#define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF5, FLOAT) +#define GPIO85_KP_DKIN_0 MFP_CFG_LPM(GPIO85, AF3, FLOAT) +#define GPIO86_KP_DKIN_1 MFP_CFG_LPM(GPIO86, AF3, FLOAT) +#define GPIO87_KP_DKIN_2 MFP_CFG_LPM(GPIO87, AF3, FLOAT) +#define GPIO88_KP_DKIN_3 MFP_CFG_LPM(GPIO88, AF3, FLOAT) +#define GPIO89_KP_DKIN_3 MFP_CFG_LPM(GPIO89, AF3, FLOAT) +#define GPIO107_KP_DKIN_0 MFP_CFG_LPM(GPIO107, AF2, FLOAT) +#define GPIO108_KP_DKIN_1 MFP_CFG_LPM(GPIO108, AF2, FLOAT) +#define GPIO109_KP_DKIN_2 MFP_CFG_LPM(GPIO109, AF2, FLOAT) +#define GPIO110_KP_DKIN_3 MFP_CFG_LPM(GPIO110, AF2, FLOAT) +#define GPIO111_KP_DKIN_4 MFP_CFG_LPM(GPIO111, AF2, FLOAT) +#define GPIO112_KP_DKIN_5 MFP_CFG_LPM(GPIO112, AF2, FLOAT) +#define GPIO113_KP_DKIN_6 MFP_CFG_LPM(GPIO113, AF2, FLOAT) +#define GPIO114_KP_DKIN_7 MFP_CFG_LPM(GPIO114, AF2, FLOAT) +#define GPIO115_KP_DKIN_0 MFP_CFG_LPM(GPIO115, AF2, FLOAT) +#define GPIO116_KP_DKIN_1 MFP_CFG_LPM(GPIO116, AF2, FLOAT) +#define GPIO117_KP_DKIN_2 MFP_CFG_LPM(GPIO117, AF2, FLOAT) +#define GPIO118_KP_DKIN_3 MFP_CFG_LPM(GPIO118, AF2, FLOAT) +#define GPIO119_KP_DKIN_4 MFP_CFG_LPM(GPIO119, AF2, FLOAT) +#define GPIO120_KP_DKIN_5 MFP_CFG_LPM(GPIO120, AF2, FLOAT) +#define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT) +#define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT) +#define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT) +#define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT) +#define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF5, FLOAT) +#define GPIO0_2_KP_DKIN_0 MFP_CFG_LPM(GPIO0_2, AF2, FLOAT) +#define GPIO1_2_KP_DKIN_1 MFP_CFG_LPM(GPIO1_2, AF2, FLOAT) +#define GPIO2_2_KP_DKIN_6 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT) +#define GPIO3_2_KP_DKIN_7 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT) +#define GPIO4_2_KP_DKIN_1 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT) +#define GPIO5_2_KP_DKIN_0 MFP_CFG_LPM(GPIO5_2, AF2, FLOAT) + +#define GPIO5_KP_MKIN_0 MFP_CFG_LPM(GPIO5, AF2, FLOAT) +#define GPIO6_KP_MKIN_1 MFP_CFG_LPM(GPIO6, AF2, FLOAT) +#define GPIO9_KP_MKIN_6 MFP_CFG_LPM(GPIO9, AF3, FLOAT) +#define GPIO10_KP_MKIN_7 MFP_CFG_LPM(GPIO10, AF3, FLOAT) +#define GPIO70_KP_MKIN_6 MFP_CFG_LPM(GPIO70, AF3, FLOAT) +#define GPIO71_KP_MKIN_7 MFP_CFG_LPM(GPIO71, AF3, FLOAT) +#define GPIO100_KP_MKIN_6 MFP_CFG_LPM(GPIO100, AF7, FLOAT) +#define GPIO101_KP_MKIN_7 MFP_CFG_LPM(GPIO101, AF7, FLOAT) +#define GPIO112_KP_MKIN_6 MFP_CFG_LPM(GPIO112, AF4, FLOAT) +#define GPIO113_KP_MKIN_7 MFP_CFG_LPM(GPIO113, AF4, FLOAT) +#define GPIO115_KP_MKIN_0 MFP_CFG_LPM(GPIO115, AF1, FLOAT) +#define GPIO116_KP_MKIN_1 MFP_CFG_LPM(GPIO116, AF1, FLOAT) +#define GPIO117_KP_MKIN_2 MFP_CFG_LPM(GPIO117, AF1, FLOAT) +#define GPIO118_KP_MKIN_3 MFP_CFG_LPM(GPIO118, AF1, FLOAT) +#define GPIO119_KP_MKIN_4 MFP_CFG_LPM(GPIO119, AF1, FLOAT) +#define GPIO120_KP_MKIN_5 MFP_CFG_LPM(GPIO120, AF1, FLOAT) +#define GPIO125_KP_MKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT) +#define GPIO2_2_KP_MKIN_6 MFP_CFG_LPM(GPIO2_2, AF1, FLOAT) +#define GPIO3_2_KP_MKIN_7 MFP_CFG_LPM(GPIO3_2, AF1, FLOAT) + +#define GPIO7_KP_MKOUT_5 MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH) +#define GPIO11_KP_MKOUT_5 MFP_CFG_LPM(GPIO11, AF3, DRIVE_HIGH) +#define GPIO12_KP_MKOUT_6 MFP_CFG_LPM(GPIO12, AF3, DRIVE_HIGH) +#define GPIO13_KP_MKOUT_7 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH) +#define GPIO19_KP_MKOUT_4 MFP_CFG_LPM(GPIO19, AF3, DRIVE_HIGH) +#define GPIO20_KP_MKOUT_5 MFP_CFG_LPM(GPIO20, AF3, DRIVE_HIGH) +#define GPIO38_KP_MKOUT_5 MFP_CFG_LPM(GPIO38, AF5, DRIVE_HIGH) +#define GPIO53_KP_MKOUT_6 MFP_CFG_LPM(GPIO53, AF5, DRIVE_HIGH) +#define GPIO78_KP_MKOUT_7 MFP_CFG_LPM(GPIO78, AF5, DRIVE_HIGH) +#define GPIO85_KP_MKOUT_0 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH) +#define GPIO86_KP_MKOUT_1 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH) +#define GPIO87_KP_MKOUT_2 MFP_CFG_LPM(GPIO87, AF2, DRIVE_HIGH) +#define GPIO88_KP_MKOUT_3 MFP_CFG_LPM(GPIO88, AF2, DRIVE_HIGH) +#define GPIO104_KP_MKOUT_6 MFP_CFG_LPM(GPIO104, AF5, DRIVE_HIGH) +#define GPIO105_KP_MKOUT_7 MFP_CFG_LPM(GPIO105, AF5, DRIVE_HIGH) +#define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH) +#define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH) +#define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH) +#define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH) +#define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH) +#define GPIO126_KP_MKOUT_7 MFP_CFG_LPM(GPIO126, AF4, DRIVE_HIGH) +#define GPIO5_2_KP_MKOUT_6 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH) +#define GPIO4_2_KP_MKOUT_5 MFP_CFG_LPM(GPIO4_2, AF1, DRIVE_HIGH) +#define GPIO6_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO6_2, AF1, DRIVE_HIGH) + +/* LCD */ +#define GPIO54_LCD_LDD_0 MFP_CFG_DRV(GPIO54, AF1, DS01X) +#define GPIO55_LCD_LDD_1 MFP_CFG_DRV(GPIO55, AF1, DS01X) +#define GPIO56_LCD_LDD_2 MFP_CFG_DRV(GPIO56, AF1, DS01X) +#define GPIO57_LCD_LDD_3 MFP_CFG_DRV(GPIO57, AF1, DS01X) +#define GPIO58_LCD_LDD_4 MFP_CFG_DRV(GPIO58, AF1, DS01X) +#define GPIO59_LCD_LDD_5 MFP_CFG_DRV(GPIO59, AF1, DS01X) +#define GPIO60_LCD_LDD_6 MFP_CFG_DRV(GPIO60, AF1, DS01X) +#define GPIO61_LCD_LDD_7 MFP_CFG_DRV(GPIO61, AF1, DS01X) +#define GPIO62_LCD_LDD_8 MFP_CFG_DRV(GPIO62, AF1, DS01X) +#define GPIO63_LCD_LDD_9 MFP_CFG_DRV(GPIO63, AF1, DS01X) +#define GPIO64_LCD_LDD_10 MFP_CFG_DRV(GPIO64, AF1, DS01X) +#define GPIO65_LCD_LDD_11 MFP_CFG_DRV(GPIO65, AF1, DS01X) +#define GPIO66_LCD_LDD_12 MFP_CFG_DRV(GPIO66, AF1, DS01X) +#define GPIO67_LCD_LDD_13 MFP_CFG_DRV(GPIO67, AF1, DS01X) +#define GPIO68_LCD_LDD_14 MFP_CFG_DRV(GPIO68, AF1, DS01X) +#define GPIO69_LCD_LDD_15 MFP_CFG_DRV(GPIO69, AF1, DS01X) +#define GPIO70_LCD_LDD_16 MFP_CFG_DRV(GPIO70, AF1, DS01X) +#define GPIO71_LCD_LDD_17 MFP_CFG_DRV(GPIO71, AF1, DS01X) +#define GPIO62_LCD_CS_N MFP_CFG_DRV(GPIO62, AF2, DS01X) +#define GPIO72_LCD_FCLK MFP_CFG_DRV(GPIO72, AF1, DS01X) +#define GPIO73_LCD_LCLK MFP_CFG_DRV(GPIO73, AF1, DS01X) +#define GPIO74_LCD_PCLK MFP_CFG_DRV(GPIO74, AF1, DS01X) +#define GPIO75_LCD_BIAS MFP_CFG_DRV(GPIO75, AF1, DS01X) +#define GPIO76_LCD_VSYNC MFP_CFG_DRV(GPIO76, AF2, DS01X) + +#define GPIO15_LCD_CS_N MFP_CFG_DRV(GPIO15, AF2, DS01X) +#define GPIO127_LCD_CS_N MFP_CFG_DRV(GPIO127, AF1, DS01X) +#define GPIO63_LCD_VSYNC MFP_CFG_DRV(GPIO63, AF2, DS01X) + +/* Mini-LCD */ +#define GPIO72_MLCD_FCLK MFP_CFG_DRV(GPIO72, AF7, DS08X) +#define GPIO73_MLCD_LCLK MFP_CFG_DRV(GPIO73, AF7, DS08X) +#define GPIO54_MLCD_LDD_0 MFP_CFG_DRV(GPIO54, AF7, DS08X) +#define GPIO55_MLCD_LDD_1 MFP_CFG_DRV(GPIO55, AF7, DS08X) +#define GPIO56_MLCD_LDD_2 MFP_CFG_DRV(GPIO56, AF7, DS08X) +#define GPIO57_MLCD_LDD_3 MFP_CFG_DRV(GPIO57, AF7, DS08X) +#define GPIO58_MLCD_LDD_4 MFP_CFG_DRV(GPIO58, AF7, DS08X) +#define GPIO59_MLCD_LDD_5 MFP_CFG_DRV(GPIO59, AF7, DS08X) +#define GPIO60_MLCD_LDD_6 MFP_CFG_DRV(GPIO60, AF7, DS08X) +#define GPIO61_MLCD_LDD_7 MFP_CFG_DRV(GPIO61, AF7, DS08X) +#define GPIO62_MLCD_LDD_8 MFP_CFG_DRV(GPIO62, AF7, DS08X) +#define GPIO63_MLCD_LDD_9 MFP_CFG_DRV(GPIO63, AF7, DS08X) +#define GPIO64_MLCD_LDD_10 MFP_CFG_DRV(GPIO64, AF7, DS08X) +#define GPIO65_MLCD_LDD_11 MFP_CFG_DRV(GPIO65, AF7, DS08X) +#define GPIO66_MLCD_LDD_12 MFP_CFG_DRV(GPIO66, AF7, DS08X) +#define GPIO67_MLCD_LDD_13 MFP_CFG_DRV(GPIO67, AF7, DS08X) +#define GPIO68_MLCD_LDD_14 MFP_CFG_DRV(GPIO68, AF7, DS08X) +#define GPIO69_MLCD_LDD_15 MFP_CFG_DRV(GPIO69, AF7, DS08X) +#define GPIO74_MLCD_PCLK MFP_CFG_DRV(GPIO74, AF7, DS08X) +#define GPIO75_MLCD_BIAS MFP_CFG_DRV(GPIO75, AF2, DS08X) + +/* MMC1 */ +#define GPIO7_MMC1_CLK MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH) +#define GPIO8_MMC1_CMD MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH) +#define GPIO14_MMC1_CMD MFP_CFG_LPM(GPIO14, AF5, DRIVE_HIGH) +#define GPIO15_MMC1_CMD MFP_CFG_LPM(GPIO15, AF5, DRIVE_HIGH) +#define GPIO3_MMC1_DAT0 MFP_CFG_LPM(GPIO3, AF4, DRIVE_HIGH) +#define GPIO4_MMC1_DAT1 MFP_CFG_LPM(GPIO4, AF4, DRIVE_HIGH) +#define GPIO5_MMC1_DAT2 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH) +#define GPIO6_MMC1_DAT3 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH) + +/* MMC2 */ +#define GPIO9_MMC2_DAT0 MFP_CFG_LPM(GPIO9, AF4, PULL_HIGH) +#define GPIO10_MMC2_DAT1 MFP_CFG_LPM(GPIO10, AF4, PULL_HIGH) +#define GPIO11_MMC2_DAT2 MFP_CFG_LPM(GPIO11, AF4, PULL_HIGH) +#define GPIO12_MMC2_DAT3 MFP_CFG_LPM(GPIO12, AF4, PULL_HIGH) +#define GPIO13_MMC2_CLK MFP_CFG_LPM(GPIO13, AF4, PULL_HIGH) +#define GPIO14_MMC2_CMD MFP_CFG_LPM(GPIO14, AF4, PULL_HIGH) +#define GPIO77_MMC2_DAT0 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH) +#define GPIO78_MMC2_DAT1 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH) +#define GPIO79_MMC2_DAT2 MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH) +#define GPIO80_MMC2_DAT3 MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH) +#define GPIO81_MMC2_CLK MFP_CFG_LPM(GPIO81, AF4, PULL_HIGH) +#define GPIO82_MMC2_CMD MFP_CFG_LPM(GPIO82, AF4, PULL_HIGH) + +/* SSP1 */ +#define GPIO89_SSP1_EXTCLK MFP_CFG(GPIO89, AF1) +#define GPIO90_SSP1_SYSCLK MFP_CFG(GPIO90, AF1) +#define GPIO15_SSP1_SCLK MFP_CFG(GPIO15, AF6) +#define GPIO16_SSP1_FRM MFP_CFG(GPIO16, AF2) +#define GPIO33_SSP1_SCLK MFP_CFG(GPIO33, AF5) +#define GPIO34_SSP1_FRM MFP_CFG(GPIO34, AF5) +#define GPIO85_SSP1_SCLK MFP_CFG(GPIO85, AF1) +#define GPIO86_SSP1_FRM MFP_CFG(GPIO86, AF1) +#define GPIO18_SSP1_TXD MFP_CFG(GPIO18, AF7) +#define GPIO18_SSP1_RXD MFP_CFG(GPIO18, AF2) +#define GPIO20_SSP1_TXD MFP_CFG(GPIO20, AF2) +#define GPIO20_SSP1_RXD MFP_CFG(GPIO20, AF7) +#define GPIO35_SSP1_TXD MFP_CFG(GPIO35, AF5) +#define GPIO35_SSP1_RXD MFP_CFG(GPIO35, AF4) +#define GPIO36_SSP1_TXD MFP_CFG(GPIO36, AF5) +#define GPIO36_SSP1_RXD MFP_CFG(GPIO36, AF6) +#define GPIO87_SSP1_TXD MFP_CFG(GPIO87, AF1) +#define GPIO87_SSP1_RXD MFP_CFG(GPIO87, AF6) +#define GPIO88_SSP1_TXD MFP_CFG(GPIO88, AF6) +#define GPIO88_SSP1_RXD MFP_CFG(GPIO88, AF1) + +/* SSP2 */ +#define GPIO29_SSP2_EXTCLK MFP_CFG(GPIO29, AF2) +#define GPIO23_SSP2_SCLK MFP_CFG(GPIO23, AF2) +#define GPIO17_SSP2_FRM MFP_CFG(GPIO17, AF2) +#define GPIO25_SSP2_SCLK MFP_CFG(GPIO25, AF2) +#define GPIO26_SSP2_FRM MFP_CFG(GPIO26, AF2) +#define GPIO33_SSP2_SCLK MFP_CFG(GPIO33, AF6) +#define GPIO34_SSP2_FRM MFP_CFG(GPIO34, AF6) +#define GPIO64_SSP2_SCLK MFP_CFG(GPIO64, AF2) +#define GPIO65_SSP2_FRM MFP_CFG(GPIO65, AF2) +#define GPIO19_SSP2_TXD MFP_CFG(GPIO19, AF2) +#define GPIO19_SSP2_RXD MFP_CFG(GPIO19, AF7) +#define GPIO24_SSP2_TXD MFP_CFG(GPIO24, AF5) +#define GPIO24_SSP2_RXD MFP_CFG(GPIO24, AF4) +#define GPIO27_SSP2_TXD MFP_CFG(GPIO27, AF2) +#define GPIO27_SSP2_RXD MFP_CFG(GPIO27, AF5) +#define GPIO28_SSP2_TXD MFP_CFG(GPIO28, AF5) +#define GPIO28_SSP2_RXD MFP_CFG(GPIO28, AF2) +#define GPIO35_SSP2_TXD MFP_CFG(GPIO35, AF7) +#define GPIO35_SSP2_RXD MFP_CFG(GPIO35, AF6) +#define GPIO66_SSP2_TXD MFP_CFG(GPIO66, AF4) +#define GPIO66_SSP2_RXD MFP_CFG(GPIO66, AF2) +#define GPIO67_SSP2_TXD MFP_CFG(GPIO67, AF2) +#define GPIO67_SSP2_RXD MFP_CFG(GPIO67, AF4) +#define GPIO36_SSP2_TXD MFP_CFG(GPIO36, AF7) + +/* SSP3 */ +#define GPIO69_SSP3_FRM MFP_CFG_X(GPIO69, AF2, DS08X, DRIVE_LOW) +#define GPIO68_SSP3_SCLK MFP_CFG_X(GPIO68, AF2, DS08X, FLOAT) +#define GPIO92_SSP3_FRM MFP_CFG_X(GPIO92, AF1, DS08X, DRIVE_LOW) +#define GPIO91_SSP3_SCLK MFP_CFG_X(GPIO91, AF1, DS08X, FLOAT) +#define GPIO70_SSP3_TXD MFP_CFG_X(GPIO70, AF2, DS08X, DRIVE_LOW) +#define GPIO70_SSP3_RXD MFP_CFG_X(GPIO70, AF5, DS08X, FLOAT) +#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF5, DS08X, DRIVE_LOW) +#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF2, DS08X, FLOAT) +#define GPIO93_SSP3_TXD MFP_CFG_X(GPIO93, AF1, DS08X, DRIVE_LOW) +#define GPIO93_SSP3_RXD MFP_CFG_X(GPIO93, AF5, DS08X, FLOAT) +#define GPIO94_SSP3_TXD MFP_CFG_X(GPIO94, AF5, DS08X, DRIVE_LOW) +#define GPIO94_SSP3_RXD MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT) + +/* SSP4 */ +#define GPIO95_SSP4_SCLK MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH) +#define GPIO96_SSP4_FRM MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH) +#define GPIO97_SSP4_TXD MFP_CFG_LPM(GPIO97, AF1, PULL_HIGH) +#define GPIO97_SSP4_RXD MFP_CFG_LPM(GPIO97, AF5, PULL_HIGH) +#define GPIO98_SSP4_TXD MFP_CFG_LPM(GPIO98, AF5, PULL_HIGH) +#define GPIO98_SSP4_RXD MFP_CFG_LPM(GPIO98, AF1, PULL_HIGH) + +/* UART1 */ +#define GPIO32_UART1_CTS MFP_CFG_LPM(GPIO32, AF2, FLOAT) +#define GPIO37_UART1_CTS MFP_CFG_LPM(GPIO37, AF4, FLOAT) +#define GPIO79_UART1_CTS MFP_CFG_LPM(GPIO79, AF1, FLOAT) +#define GPIO84_UART1_CTS MFP_CFG_LPM(GPIO84, AF3, FLOAT) +#define GPIO101_UART1_CTS MFP_CFG_LPM(GPIO101, AF1, FLOAT) +#define GPIO106_UART1_CTS MFP_CFG_LPM(GPIO106, AF6, FLOAT) + +#define GPIO32_UART1_RTS MFP_CFG_LPM(GPIO32, AF4, FLOAT) +#define GPIO37_UART1_RTS MFP_CFG_LPM(GPIO37, AF2, FLOAT) +#define GPIO79_UART1_RTS MFP_CFG_LPM(GPIO79, AF3, FLOAT) +#define GPIO84_UART1_RTS MFP_CFG_LPM(GPIO84, AF1, FLOAT) +#define GPIO101_UART1_RTS MFP_CFG_LPM(GPIO101, AF6, FLOAT) +#define GPIO106_UART1_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT) + +#define GPIO34_UART1_DSR MFP_CFG_LPM(GPIO34, AF2, FLOAT) +#define GPIO36_UART1_DSR MFP_CFG_LPM(GPIO36, AF4, FLOAT) +#define GPIO81_UART1_DSR MFP_CFG_LPM(GPIO81, AF1, FLOAT) +#define GPIO83_UART1_DSR MFP_CFG_LPM(GPIO83, AF3, FLOAT) +#define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF1, FLOAT) +#define GPIO105_UART1_DSR MFP_CFG_LPM(GPIO105, AF6, FLOAT) + +#define GPIO34_UART1_DTR MFP_CFG_LPM(GPIO34, AF4, FLOAT) +#define GPIO36_UART1_DTR MFP_CFG_LPM(GPIO36, AF2, FLOAT) +#define GPIO81_UART1_DTR MFP_CFG_LPM(GPIO81, AF3, FLOAT) +#define GPIO83_UART1_DTR MFP_CFG_LPM(GPIO83, AF1, FLOAT) +#define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF6, FLOAT) +#define GPIO105_UART1_DTR MFP_CFG_LPM(GPIO105, AF1, FLOAT) + +#define GPIO35_UART1_RI MFP_CFG_LPM(GPIO35, AF2, FLOAT) +#define GPIO82_UART1_RI MFP_CFG_LPM(GPIO82, AF1, FLOAT) +#define GPIO104_UART1_RI MFP_CFG_LPM(GPIO104, AF1, FLOAT) + +#define GPIO33_UART1_DCD MFP_CFG_LPM(GPIO33, AF2, FLOAT) +#define GPIO80_UART1_DCD MFP_CFG_LPM(GPIO80, AF1, FLOAT) +#define GPIO102_UART1_DCD MFP_CFG_LPM(GPIO102, AF1, FLOAT) + +#define GPIO30_UART1_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT) +#define GPIO31_UART1_RXD MFP_CFG_LPM(GPIO31, AF4, FLOAT) +#define GPIO77_UART1_RXD MFP_CFG_LPM(GPIO77, AF1, FLOAT) +#define GPIO78_UART1_RXD MFP_CFG_LPM(GPIO78, AF3, FLOAT) +#define GPIO99_UART1_RXD MFP_CFG_LPM(GPIO99, AF1, FLOAT) +#define GPIO100_UART1_RXD MFP_CFG_LPM(GPIO100, AF6, FLOAT) +#define GPIO102_UART1_RXD MFP_CFG_LPM(GPIO102, AF6, FLOAT) +#define GPIO104_UART1_RXD MFP_CFG_LPM(GPIO104, AF4, FLOAT) + +#define GPIO30_UART1_TXD MFP_CFG_LPM(GPIO30, AF4, FLOAT) +#define GPIO31_UART1_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT) +#define GPIO77_UART1_TXD MFP_CFG_LPM(GPIO77, AF3, FLOAT) +#define GPIO78_UART1_TXD MFP_CFG_LPM(GPIO78, AF1, FLOAT) +#define GPIO99_UART1_TXD MFP_CFG_LPM(GPIO99, AF6, FLOAT) +#define GPIO100_UART1_TXD MFP_CFG_LPM(GPIO100, AF1, FLOAT) +#define GPIO102_UART1_TXD MFP_CFG_LPM(GPIO102, AF4, FLOAT) + +/* UART2 */ +#define GPIO15_UART2_CTS MFP_CFG_LPM(GPIO15, AF3, FLOAT) +#define GPIO16_UART2_CTS MFP_CFG_LPM(GPIO16, AF5, FLOAT) +#define GPIO111_UART2_CTS MFP_CFG_LPM(GPIO111, AF3, FLOAT) +#define GPIO114_UART2_CTS MFP_CFG_LPM(GPIO114, AF1, FLOAT) + +#define GPIO15_UART2_RTS MFP_CFG_LPM(GPIO15, AF4, FLOAT) +#define GPIO16_UART2_RTS MFP_CFG_LPM(GPIO16, AF4, FLOAT) +#define GPIO114_UART2_RTS MFP_CFG_LPM(GPIO114, AF3, FLOAT) +#define GPIO111_UART2_RTS MFP_CFG_LPM(GPIO111, AF1, FLOAT) + +#define GPIO18_UART2_RXD MFP_CFG_LPM(GPIO18, AF5, FLOAT) +#define GPIO19_UART2_RXD MFP_CFG_LPM(GPIO19, AF4, FLOAT) +#define GPIO112_UART2_RXD MFP_CFG_LPM(GPIO112, AF1, FLOAT) +#define GPIO113_UART2_RXD MFP_CFG_LPM(GPIO113, AF3, FLOAT) + +#define GPIO18_UART2_TXD MFP_CFG_LPM(GPIO18, AF4, FLOAT) +#define GPIO19_UART2_TXD MFP_CFG_LPM(GPIO19, AF5, FLOAT) +#define GPIO112_UART2_TXD MFP_CFG_LPM(GPIO112, AF3, FLOAT) +#define GPIO113_UART2_TXD MFP_CFG_LPM(GPIO113, AF1, FLOAT) + +/* UART3 */ +#define GPIO91_UART3_CTS MFP_CFG_LPM(GPIO91, AF2, FLOAT) +#define GPIO92_UART3_CTS MFP_CFG_LPM(GPIO92, AF4, FLOAT) +#define GPIO107_UART3_CTS MFP_CFG_LPM(GPIO107, AF1, FLOAT) +#define GPIO108_UART3_CTS MFP_CFG_LPM(GPIO108, AF3, FLOAT) + +#define GPIO91_UART3_RTS MFP_CFG_LPM(GPIO91, AF4, FLOAT) +#define GPIO92_UART3_RTS MFP_CFG_LPM(GPIO92, AF2, FLOAT) +#define GPIO107_UART3_RTS MFP_CFG_LPM(GPIO107, AF3, FLOAT) +#define GPIO108_UART3_RTS MFP_CFG_LPM(GPIO108, AF1, FLOAT) + +#define GPIO7_UART3_RXD MFP_CFG_LPM(GPIO7, AF2, FLOAT) +#define GPIO8_UART3_RXD MFP_CFG_LPM(GPIO8, AF6, FLOAT) +#define GPIO93_UART3_RXD MFP_CFG_LPM(GPIO93, AF4, FLOAT) +#define GPIO94_UART3_RXD MFP_CFG_LPM(GPIO94, AF2, FLOAT) +#define GPIO109_UART3_RXD MFP_CFG_LPM(GPIO109, AF3, FLOAT) +#define GPIO110_UART3_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT) + +#define GPIO7_UART3_TXD MFP_CFG_LPM(GPIO7, AF6, FLOAT) +#define GPIO8_UART3_TXD MFP_CFG_LPM(GPIO8, AF2, FLOAT) +#define GPIO93_UART3_TXD MFP_CFG_LPM(GPIO93, AF2, FLOAT) +#define GPIO94_UART3_TXD MFP_CFG_LPM(GPIO94, AF4, FLOAT) +#define GPIO109_UART3_TXD MFP_CFG_LPM(GPIO109, AF1, FLOAT) +#define GPIO110_UART3_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT) + +/* USB Host */ +#define GPIO0_2_USBH_PEN MFP_CFG(GPIO0_2, AF1) +#define GPIO1_2_USBH_PWR MFP_CFG(GPIO1_2, AF1) + +/* USB P3 */ +#define GPIO77_USB_P3_1 MFP_CFG(GPIO77, AF2) +#define GPIO78_USB_P3_2 MFP_CFG(GPIO78, AF2) +#define GPIO79_USB_P3_3 MFP_CFG(GPIO79, AF2) +#define GPIO80_USB_P3_4 MFP_CFG(GPIO80, AF2) +#define GPIO81_USB_P3_5 MFP_CFG(GPIO81, AF2) +#define GPIO82_USB_P3_6 MFP_CFG(GPIO82, AF2) + +/* PWM */ +#define GPIO17_PWM0_OUT MFP_CFG(GPIO17, AF1) +#define GPIO18_PWM1_OUT MFP_CFG(GPIO18, AF1) +#define GPIO19_PWM2_OUT MFP_CFG(GPIO19, AF1) +#define GPIO20_PWM3_OUT MFP_CFG(GPIO20, AF1) + +/* CIR */ +#define GPIO8_CIR_OUT MFP_CFG(GPIO8, AF5) +#define GPIO16_CIR_OUT MFP_CFG(GPIO16, AF3) + +#define GPIO20_OW_DQ_IN MFP_CFG(GPIO20, AF5) +#define GPIO126_OW_DQ MFP_CFG(GPIO126, AF2) + +#define GPIO0_DF_RDY MFP_CFG(GPIO0, AF1) +#define GPIO7_CLK_BYPASS_XSC MFP_CFG(GPIO7, AF7) +#define GPIO17_EXT_SYNC_MVT_0 MFP_CFG(GPIO17, AF6) +#define GPIO18_EXT_SYNC_MVT_1 MFP_CFG(GPIO18, AF6) +#define GPIO19_OST_CHOUT_MVT_0 MFP_CFG(GPIO19, AF6) +#define GPIO20_OST_CHOUT_MVT_1 MFP_CFG(GPIO20, AF6) +#define GPIO49_48M_CLK MFP_CFG(GPIO49, AF2) +#define GPIO126_EXT_CLK MFP_CFG(GPIO126, AF3) +#define GPIO127_CLK_BYPASS_GB MFP_CFG(GPIO127, AF7) +#define GPIO71_EXT_MATCH_MVT MFP_CFG(GPIO71, AF6) + +#define GPIO3_uIO_IN MFP_CFG(GPIO3, AF1) + +#define GPIO4_uSIM_CARD_STATE MFP_CFG(GPIO4, AF1) +#define GPIO5_uSIM_uCLK MFP_CFG(GPIO5, AF1) +#define GPIO6_uSIM_uRST MFP_CFG(GPIO6, AF1) +#define GPIO16_uSIM_UVS_0 MFP_CFG(GPIO16, AF1) + +#define GPIO9_SCIO MFP_CFG(GPIO9, AF1) +#define GPIO20_RTC_MVT MFP_CFG(GPIO20, AF4) +#define GPIO126_RTC_MVT MFP_CFG(GPIO126, AF1) + +/* + * PXA300 specific MFP configurations + */ +#ifdef CONFIG_CPU_PXA300 +#define GPIO99_USB_P2_2 MFP_CFG(GPIO99, AF2) +#define GPIO99_USB_P2_5 MFP_CFG(GPIO99, AF3) +#define GPIO99_USB_P2_6 MFP_CFG(GPIO99, AF4) +#define GPIO100_USB_P2_2 MFP_CFG(GPIO100, AF4) +#define GPIO100_USB_P2_5 MFP_CFG(GPIO100, AF5) +#define GPIO101_USB_P2_1 MFP_CFG(GPIO101, AF2) +#define GPIO102_USB_P2_4 MFP_CFG(GPIO102, AF2) +#define GPIO104_USB_P2_3 MFP_CFG(GPIO104, AF2) +#define GPIO105_USB_P2_5 MFP_CFG(GPIO105, AF2) +#define GPIO100_USB_P2_6 MFP_CFG(GPIO100, AF2) +#define GPIO106_USB_P2_7 MFP_CFG(GPIO106, AF2) +#define GPIO103_USB_P2_8 MFP_CFG(GPIO103, AF2) + +/* U2D UTMI */ +#define GPIO38_UTM_CLK MFP_CFG(GPIO38, AF1) +#define GPIO26_U2D_RXERROR MFP_CFG(GPIO26, AF3) +#define GPIO50_U2D_RXERROR MFP_CFG(GPIO50, AF1) +#define GPIO89_U2D_RXERROR MFP_CFG(GPIO89, AF5) +#define GPIO24_UTM_RXVALID MFP_CFG(GPIO24, AF3) +#define GPIO48_UTM_RXVALID MFP_CFG(GPIO48, AF2) +#define GPIO87_UTM_RXVALID MFP_CFG(GPIO87, AF5) +#define GPIO25_UTM_RXACTIVE MFP_CFG(GPIO25, AF3) +#define GPIO47_UTM_RXACTIVE MFP_CFG(GPIO47, AF2) +#define GPIO49_UTM_RXACTIVE MFP_CFG(GPIO49, AF1) +#define GPIO88_UTM_RXACTIVE MFP_CFG(GPIO88, AF5) +#define GPIO53_UTM_TXREADY MFP_CFG(GPIO53, AF1) +#define GPIO67_UTM_LINESTATE_0 MFP_CFG(GPIO67, AF3) +#define GPIO92_UTM_LINESTATE_0 MFP_CFG(GPIO92, AF3) +#define GPIO104_UTM_LINESTATE_0 MFP_CFG(GPIO104, AF3) +#define GPIO109_UTM_LINESTATE_0 MFP_CFG(GPIO109, AF4) +#define GPIO68_UTM_LINESTATE_1 MFP_CFG(GPIO68, AF3) +#define GPIO93_UTM_LINESTATE_1 MFP_CFG(GPIO93, AF3) +#define GPIO105_UTM_LINESTATE_1 MFP_CFG(GPIO105, AF3) +#define GPIO27_U2D_OPMODE_0 MFP_CFG(GPIO27, AF4) +#define GPIO51_U2D_OPMODE_0 MFP_CFG(GPIO51, AF2) +#define GPIO90_U2D_OPMODE_0 MFP_CFG(GPIO90, AF7) +#define GPIO28_U2D_OPMODE_1 MFP_CFG(GPIO28, AF4) +#define GPIO52_U2D_OPMODE_1 MFP_CFG(GPIO52, AF2) +#define GPIO106_U2D_OPMODE_1 MFP_CFG(GPIO106, AF3) +#define GPIO110_U2D_OPMODE_1 MFP_CFG(GPIO110, AF5) +#define GPIO76_U2D_RESET MFP_CFG(GPIO76, AF1) +#define GPIO95_U2D_RESET MFP_CFG(GPIO95, AF2) +#define GPIO100_U2D_RESET MFP_CFG(GPIO100, AF3) +#define GPIO66_U2D_SUSPEND MFP_CFG(GPIO66, AF3) +#define GPIO98_U2D_SUSPEND MFP_CFG(GPIO98, AF2) +#define GPIO103_U2D_SUSPEND MFP_CFG(GPIO103, AF3) +#define GPIO65_U2D_TERM_SEL MFP_CFG(GPIO65, AF5) +#define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF3) +#define GPIO102_U2D_TERM_SEL MFP_CFG(GPIO102, AF5) +#define GPIO29_U2D_TXVALID MFP_CFG(GPIO29, AF3) +#define GPIO52_U2D_TXVALID MFP_CFG(GPIO52, AF4) +#define GPIO69_U2D_TXVALID MFP_CFG(GPIO69, AF3) +#define GPIO85_U2D_TXVALID MFP_CFG(GPIO85, AF7) +#define GPIO64_U2D_XCVR_SEL MFP_CFG(GPIO64, AF5) +#define GPIO96_U2D_XCVR_SEL MFP_CFG(GPIO96, AF3) +#define GPIO101_U2D_XCVR_SEL MFP_CFG(GPIO101, AF5) +#define GPIO30_UTM_PHYDATA_0 MFP_CFG(GPIO30, AF3) +#define GPIO31_UTM_PHYDATA_1 MFP_CFG(GPIO31, AF3) +#define GPIO32_UTM_PHYDATA_2 MFP_CFG(GPIO32, AF3) +#define GPIO33_UTM_PHYDATA_3 MFP_CFG(GPIO33, AF3) +#define GPIO34_UTM_PHYDATA_4 MFP_CFG(GPIO34, AF3) +#define GPIO35_UTM_PHYDATA_5 MFP_CFG(GPIO35, AF3) +#define GPIO36_UTM_PHYDATA_6 MFP_CFG(GPIO36, AF3) +#define GPIO37_UTM_PHYDATA_7 MFP_CFG(GPIO37, AF3) +#define GPIO39_UTM_PHYDATA_0 MFP_CFG(GPIO39, AF3) +#define GPIO40_UTM_PHYDATA_1 MFP_CFG(GPIO40, AF3) +#define GPIO41_UTM_PHYDATA_2 MFP_CFG(GPIO41, AF3) +#define GPIO42_UTM_PHYDATA_3 MFP_CFG(GPIO42, AF3) +#define GPIO43_UTM_PHYDATA_4 MFP_CFG(GPIO43, AF3) +#define GPIO44_UTM_PHYDATA_5 MFP_CFG(GPIO44, AF3) +#define GPIO45_UTM_PHYDATA_6 MFP_CFG(GPIO45, AF3) +#define GPIO46_UTM_PHYDATA_7 MFP_CFG(GPIO46, AF3) +#endif /* CONFIG_CPU_PXA300 */ + +/* + * PXA310 specific MFP configurations + */ +#ifdef CONFIG_CPU_PXA310 +/* USB P2 */ +#define GPIO36_USB_P2_1 MFP_CFG(GPIO36, AF1) +#define GPIO30_USB_P2_2 MFP_CFG(GPIO30, AF1) +#define GPIO35_USB_P2_3 MFP_CFG(GPIO35, AF1) +#define GPIO32_USB_P2_4 MFP_CFG(GPIO32, AF1) +#define GPIO34_USB_P2_5 MFP_CFG(GPIO34, AF1) +#define GPIO31_USB_P2_6 MFP_CFG(GPIO31, AF1) + +/* MMC1 */ +#define GPIO24_MMC1_CMD MFP_CFG(GPIO24, AF3) +#define GPIO29_MMC1_DAT0 MFP_CFG(GPIO29, AF3) + +/* MMC3 */ +#define GPIO103_MMC3_CLK MFP_CFG(GPIO103, AF2) +#define GPIO105_MMC3_CMD MFP_CFG(GPIO105, AF2) +#define GPIO11_2_MMC3_CLK MFP_CFG(GPIO11_2, AF1) +#define GPIO12_2_MMC3_CMD MFP_CFG(GPIO12_2, AF1) +#define GPIO7_2_MMC3_DAT0 MFP_CFG(GPIO7_2, AF1) +#define GPIO8_2_MMC3_DAT1 MFP_CFG(GPIO8_2, AF1) +#define GPIO9_2_MMC3_DAT2 MFP_CFG(GPIO9_2, AF1) +#define GPIO10_2_MMC3_DAT3 MFP_CFG(GPIO10_2, AF1) + +/* ULPI */ +#define GPIO38_ULPI_CLK MFP_CFG(GPIO38, AF1) +#define GPIO30_ULPI_DATA_OUT_0 MFP_CFG(GPIO30, AF3) +#define GPIO31_ULPI_DATA_OUT_1 MFP_CFG(GPIO31, AF3) +#define GPIO32_ULPI_DATA_OUT_2 MFP_CFG(GPIO32, AF3) +#define GPIO33_ULPI_DATA_OUT_3 MFP_CFG(GPIO33, AF3) +#define GPIO34_ULPI_DATA_OUT_4 MFP_CFG(GPIO34, AF3) +#define GPIO35_ULPI_DATA_OUT_5 MFP_CFG(GPIO35, AF3) +#define GPIO36_ULPI_DATA_OUT_6 MFP_CFG(GPIO36, AF3) +#define GPIO37_ULPI_DATA_OUT_7 MFP_CFG(GPIO37, AF3) +#define GPIO33_ULPI_OTG_INTR MFP_CFG(GPIO33, AF1) + +#define ULPI_DIR MFP_CFG_DRV(ULPI_DIR, MFP_AF0, MFP_DS01X) +#define ULPI_NXT MFP_CFG_DRV(ULPI_NXT, MFP_AF0, MFP_DS01X) +#define ULPI_STP MFP_CFG_DRV(ULPI_STP, MFP_AF0, MFP_DS01X) +#endif /* CONFIG_CPU_PXA310 */ + +#endif /* __ASM_ARCH_MFP_PXA300_H */ diff --git a/include/asm-arm/arch-pxa/mfp-pxa320.h b/include/asm-arm/arch-pxa/mfp-pxa320.h new file mode 100644 index 000000000000..ae8ba34194cf --- /dev/null +++ b/include/asm-arm/arch-pxa/mfp-pxa320.h @@ -0,0 +1,446 @@ +/* + * linux/include/asm-arm/arch-pxa/mfp-pxa320.h + * + * PXA320 specific MFP configuration definitions + * + * Copyright (C) 2007 Marvell International Ltd. + * 2007-08-21: eric miao + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MFP_PXA320_H +#define __ASM_ARCH_MFP_PXA320_H + +#include + +/* GPIO */ +#define GPIO46_GPIO MFP_CFG(GPIO6, AF0) +#define GPIO49_GPIO MFP_CFG(GPIO49, AF0) +#define GPIO50_GPIO MFP_CFG(GPIO50, AF0) +#define GPIO51_GPIO MFP_CFG(GPIO51, AF0) +#define GPIO52_GPIO MFP_CFG(GPIO52, AF0) + +#define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0) +#define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0) +#define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0) +#define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0) +#define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0) +#define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0) +#define GPIO13_2_GPIO MFP_CFG(GPIO13_2, AF0) +#define GPIO14_2_GPIO MFP_CFG(GPIO14_2, AF0) +#define GPIO15_2_GPIO MFP_CFG(GPIO15_2, AF0) +#define GPIO16_2_GPIO MFP_CFG(GPIO16_2, AF0) +#define GPIO17_2_GPIO MFP_CFG(GPIO17_2, AF0) + +/* Chip Select */ +#define GPIO4_nCS3 MFP_CFG(GPIO4, AF1) + +/* AC97 */ +#define GPIO34_AC97_SYSCLK MFP_CFG(GPIO34, AF1) +#define GPIO39_AC97_BITCLK MFP_CFG(GPIO39, AF1) +#define GPIO40_AC97_nACRESET MFP_CFG(GPIO40, AF1) +#define GPIO35_AC97_SDATA_IN_0 MFP_CFG(GPIO35, AF1) +#define GPIO36_AC97_SDATA_IN_1 MFP_CFG(GPIO36, AF1) +#define GPIO32_AC97_SDATA_IN_2 MFP_CFG(GPIO32, AF2) +#define GPIO33_AC97_SDATA_IN_3 MFP_CFG(GPIO33, AF2) +#define GPIO11_AC97_SDATA_IN_2 MFP_CFG(GPIO11, AF3) +#define GPIO12_AC97_SDATA_IN_3 MFP_CFG(GPIO12, AF3) +#define GPIO37_AC97_SDATA_OUT MFP_CFG(GPIO37, AF1) +#define GPIO38_AC97_SYNC MFP_CFG(GPIO38, AF1) + +/* I2C */ +#define GPIO32_I2C_SCL MFP_CFG_LPM(GPIO32, AF1, PULL_HIGH) +#define GPIO33_I2C_SDA MFP_CFG_LPM(GPIO33, AF1, PULL_HIGH) + +/* QCI */ +#define GPIO49_CI_DD_0 MFP_CFG_DRV(GPIO49, AF1, DS04X) +#define GPIO50_CI_DD_1 MFP_CFG_DRV(GPIO50, AF1, DS04X) +#define GPIO51_CI_DD_2 MFP_CFG_DRV(GPIO51, AF1, DS04X) +#define GPIO52_CI_DD_3 MFP_CFG_DRV(GPIO52, AF1, DS04X) +#define GPIO53_CI_DD_4 MFP_CFG_DRV(GPIO53, AF1, DS04X) +#define GPIO54_CI_DD_5 MFP_CFG_DRV(GPIO54, AF1, DS04X) +#define GPIO55_CI_DD_6 MFP_CFG_DRV(GPIO55, AF1, DS04X) +#define GPIO56_CI_DD_7 MFP_CFG_DRV(GPIO56, AF0, DS04X) +#define GPIO57_CI_DD_8 MFP_CFG_DRV(GPIO57, AF1, DS04X) +#define GPIO58_CI_DD_9 MFP_CFG_DRV(GPIO58, AF1, DS04X) +#define GPIO59_CI_MCLK MFP_CFG_DRV(GPIO59, AF0, DS04X) +#define GPIO60_CI_PCLK MFP_CFG_DRV(GPIO60, AF0, DS04X) +#define GPIO61_CI_HSYNC MFP_CFG_DRV(GPIO61, AF0, DS04X) +#define GPIO62_CI_VSYNC MFP_CFG_DRV(GPIO62, AF0, DS04X) + +#define GPIO31_CIR_OUT MFP_CFG(GPIO31, AF5) + +#define GPIO0_2_CLK_EXT MFP_CFG(GPIO0_2, AF3) +#define GPIO0_DRQ MFP_CFG(GPIO0, AF2) +#define GPIO11_EXT_SYNC0 MFP_CFG(GPIO11, AF5) +#define GPIO12_EXT_SYNC1 MFP_CFG(GPIO12, AF6) +#define GPIO0_2_HZ_CLK MFP_CFG(GPIO0_2, AF1) +#define GPIO14_HZ_CLK MFP_CFG(GPIO14, AF4) +#define GPIO30_ICP_RXD MFP_CFG(GPIO30, AF1) +#define GPIO31_ICP_TXD MFP_CFG(GPIO31, AF1) + +#define GPIO83_KP_DKIN_0 MFP_CFG_LPM(GPIO83, AF3, FLOAT) +#define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF3, FLOAT) +#define GPIO85_KP_DKIN_2 MFP_CFG_LPM(GPIO85, AF3, FLOAT) +#define GPIO86_KP_DKIN_3 MFP_CFG_LPM(GPIO86, AF3, FLOAT) + +#define GPIO105_KP_DKIN_0 MFP_CFG_LPM(GPIO105, AF2, FLOAT) +#define GPIO106_KP_DKIN_1 MFP_CFG_LPM(GPIO106, AF2, FLOAT) +#define GPIO107_KP_DKIN_2 MFP_CFG_LPM(GPIO107, AF2, FLOAT) +#define GPIO108_KP_DKIN_3 MFP_CFG_LPM(GPIO108, AF2, FLOAT) +#define GPIO109_KP_DKIN_4 MFP_CFG_LPM(GPIO109, AF2, FLOAT) +#define GPIO110_KP_DKIN_5 MFP_CFG_LPM(GPIO110, AF2, FLOAT) +#define GPIO111_KP_DKIN_6 MFP_CFG_LPM(GPIO111, AF2, FLOAT) +#define GPIO112_KP_DKIN_7 MFP_CFG_LPM(GPIO112, AF2, FLOAT) + +#define GPIO113_KP_DKIN_0 MFP_CFG_LPM(GPIO113, AF2, FLOAT) +#define GPIO114_KP_DKIN_1 MFP_CFG_LPM(GPIO114, AF2, FLOAT) +#define GPIO115_KP_DKIN_2 MFP_CFG_LPM(GPIO115, AF2, FLOAT) +#define GPIO116_KP_DKIN_3 MFP_CFG_LPM(GPIO116, AF2, FLOAT) +#define GPIO117_KP_DKIN_4 MFP_CFG_LPM(GPIO117, AF2, FLOAT) +#define GPIO118_KP_DKIN_5 MFP_CFG_LPM(GPIO118, AF2, FLOAT) +#define GPIO119_KP_DKIN_6 MFP_CFG_LPM(GPIO119, AF2, FLOAT) +#define GPIO120_KP_DKIN_7 MFP_CFG_LPM(GPIO120, AF2, FLOAT) + +#define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF2, FLOAT) +#define GPIO126_KP_DKIN_1 MFP_CFG_LPM(GPIO126, AF2, FLOAT) + +#define GPIO2_2_KP_DKIN_0 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT) +#define GPIO3_2_KP_DKIN_1 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT) +#define GPIO125_KP_DKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT) +#define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT) +#define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT) +#define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT) +#define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT) +#define GPIO4_2_KP_DKIN_7 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT) + +#define GPIO113_KP_MKIN_0 MFP_CFG_LPM(GPIO113, AF1, FLOAT) +#define GPIO114_KP_MKIN_1 MFP_CFG_LPM(GPIO114, AF1, FLOAT) +#define GPIO115_KP_MKIN_2 MFP_CFG_LPM(GPIO115, AF1, FLOAT) +#define GPIO116_KP_MKIN_3 MFP_CFG_LPM(GPIO116, AF1, FLOAT) +#define GPIO117_KP_MKIN_4 MFP_CFG_LPM(GPIO117, AF1, FLOAT) +#define GPIO118_KP_MKIN_5 MFP_CFG_LPM(GPIO118, AF1, FLOAT) +#define GPIO119_KP_MKIN_6 MFP_CFG_LPM(GPIO119, AF1, FLOAT) +#define GPIO120_KP_MKIN_7 MFP_CFG_LPM(GPIO120, AF1, FLOAT) + +#define GPIO83_KP_MKOUT_0 MFP_CFG_LPM(GPIO83, AF2, DRIVE_HIGH) +#define GPIO84_KP_MKOUT_1 MFP_CFG_LPM(GPIO84, AF2, DRIVE_HIGH) +#define GPIO85_KP_MKOUT_2 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH) +#define GPIO86_KP_MKOUT_3 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH) +#define GPIO13_KP_MKOUT_4 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH) +#define GPIO14_KP_MKOUT_5 MFP_CFG_LPM(GPIO14, AF3, DRIVE_HIGH) + +#define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH) +#define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH) +#define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH) +#define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH) +#define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH) +#define GPIO126_KP_MKOUT_5 MFP_CFG_LPM(GPIO126, AF1, DRIVE_HIGH) +#define GPIO127_KP_MKOUT_6 MFP_CFG_LPM(GPIO127, AF1, DRIVE_HIGH) +#define GPIO5_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH) + +/* LCD */ +#define GPIO6_2_LCD_LDD_0 MFP_CFG_DRV(GPIO6_2, AF1, DS01X) +#define GPIO7_2_LCD_LDD_1 MFP_CFG_DRV(GPIO7_2, AF1, DS01X) +#define GPIO8_2_LCD_LDD_2 MFP_CFG_DRV(GPIO8_2, AF1, DS01X) +#define GPIO9_2_LCD_LDD_3 MFP_CFG_DRV(GPIO9_2, AF1, DS01X) +#define GPIO10_2_LCD_LDD_4 MFP_CFG_DRV(GPIO10_2, AF1, DS01X) +#define GPIO11_2_LCD_LDD_5 MFP_CFG_DRV(GPIO11_2, AF1, DS01X) +#define GPIO12_2_LCD_LDD_6 MFP_CFG_DRV(GPIO12_2, AF1, DS01X) +#define GPIO13_2_LCD_LDD_7 MFP_CFG_DRV(GPIO13_2, AF1, DS01X) +#define GPIO63_LCD_LDD_8 MFP_CFG_DRV(GPIO63, AF1, DS01X) +#define GPIO64_LCD_LDD_9 MFP_CFG_DRV(GPIO64, AF1, DS01X) +#define GPIO65_LCD_LDD_10 MFP_CFG_DRV(GPIO65, AF1, DS01X) +#define GPIO66_LCD_LDD_11 MFP_CFG_DRV(GPIO66, AF1, DS01X) +#define GPIO67_LCD_LDD_12 MFP_CFG_DRV(GPIO67, AF1, DS01X) +#define GPIO68_LCD_LDD_13 MFP_CFG_DRV(GPIO68, AF1, DS01X) +#define GPIO69_LCD_LDD_14 MFP_CFG_DRV(GPIO69, AF1, DS01X) +#define GPIO70_LCD_LDD_15 MFP_CFG_DRV(GPIO70, AF1, DS01X) +#define GPIO71_LCD_LDD_16 MFP_CFG_DRV(GPIO71, AF1, DS01X) +#define GPIO72_LCD_LDD_17 MFP_CFG_DRV(GPIO72, AF1, DS01X) +#define GPIO73_LCD_CS_N MFP_CFG_DRV(GPIO73, AF2, DS01X) +#define GPIO74_LCD_VSYNC MFP_CFG_DRV(GPIO74, AF2, DS01X) +#define GPIO14_2_LCD_FCLK MFP_CFG_DRV(GPIO14_2, AF1, DS01X) +#define GPIO15_2_LCD_LCLK MFP_CFG_DRV(GPIO15_2, AF1, DS01X) +#define GPIO16_2_LCD_PCLK MFP_CFG_DRV(GPIO16_2, AF1, DS01X) +#define GPIO17_2_LCD_BIAS MFP_CFG_DRV(GPIO17_2, AF1, DS01X) +#define GPIO64_LCD_VSYNC MFP_CFG_DRV(GPIO64, AF2, DS01X) +#define GPIO63_LCD_CS_N MFP_CFG_DRV(GPIO63, AF2, DS01X) + +#define GPIO6_2_MLCD_DD_0 MFP_CFG_DRV(GPIO6_2, AF7, DS08X) +#define GPIO7_2_MLCD_DD_1 MFP_CFG_DRV(GPIO7_2, AF7, DS08X) +#define GPIO8_2_MLCD_DD_2 MFP_CFG_DRV(GPIO8_2, AF7, DS08X) +#define GPIO9_2_MLCD_DD_3 MFP_CFG_DRV(GPIO9_2, AF7, DS08X) +#define GPIO10_2_MLCD_DD_4 MFP_CFG_DRV(GPIO10_2, AF7, DS08X) +#define GPIO11_2_MLCD_DD_5 MFP_CFG_DRV(GPIO11_2, AF7, DS08X) +#define GPIO12_2_MLCD_DD_6 MFP_CFG_DRV(GPIO12_2, AF7, DS08X) +#define GPIO13_2_MLCD_DD_7 MFP_CFG_DRV(GPIO13_2, AF7, DS08X) +#define GPIO63_MLCD_DD_8 MFP_CFG_DRV(GPIO63, AF7, DS08X) +#define GPIO64_MLCD_DD_9 MFP_CFG_DRV(GPIO64, AF7, DS08X) +#define GPIO65_MLCD_DD_10 MFP_CFG_DRV(GPIO65, AF7, DS08X) +#define GPIO66_MLCD_DD_11 MFP_CFG_DRV(GPIO66, AF7, DS08X) +#define GPIO67_MLCD_DD_12 MFP_CFG_DRV(GPIO67, AF7, DS08X) +#define GPIO68_MLCD_DD_13 MFP_CFG_DRV(GPIO68, AF7, DS08X) +#define GPIO69_MLCD_DD_14 MFP_CFG_DRV(GPIO69, AF7, DS08X) +#define GPIO70_MLCD_DD_15 MFP_CFG_DRV(GPIO70, AF7, DS08X) +#define GPIO71_MLCD_DD_16 MFP_CFG_DRV(GPIO71, AF7, DS08X) +#define GPIO72_MLCD_DD_17 MFP_CFG_DRV(GPIO72, AF7, DS08X) +#define GPIO73_MLCD_CS MFP_CFG_DRV(GPIO73, AF7, DS08X) +#define GPIO74_MLCD_VSYNC MFP_CFG_DRV(GPIO74, AF7, DS08X) +#define GPIO14_2_MLCD_FCLK MFP_CFG_DRV(GPIO14_2, AF7, DS08X) +#define GPIO15_2_MLCD_LCLK MFP_CFG_DRV(GPIO15_2, AF7, DS08X) +#define GPIO16_2_MLCD_PCLK MFP_CFG_DRV(GPIO16_2, AF7, DS08X) +#define GPIO17_2_MLCD_BIAS MFP_CFG_DRV(GPIO17_2, AF7, DS08X) + +/* MMC1 */ +#define GPIO9_MMC1_CMD MFP_CFG_LPM(GPIO9, AF4, DRIVE_HIGH) +#define GPIO22_MMC1_CLK MFP_CFG_LPM(GPIO22, AF4, DRIVE_HIGH) +#define GPIO23_MMC1_CMD MFP_CFG_LPM(GPIO23, AF4, DRIVE_HIGH) +#define GPIO30_MMC1_CLK MFP_CFG_LPM(GPIO30, AF4, DRIVE_HIGH) +#define GPIO31_MMC1_CMD MFP_CFG_LPM(GPIO31, AF4, DRIVE_HIGH) +#define GPIO5_MMC1_DAT0 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH) +#define GPIO6_MMC1_DAT1 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH) +#define GPIO7_MMC1_DAT2 MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH) +#define GPIO8_MMC1_DAT3 MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH) +#define GPIO18_MMC1_DAT0 MFP_CFG_LPM(GPIO18, AF4, DRIVE_HIGH) +#define GPIO19_MMC1_DAT1 MFP_CFG_LPM(GPIO19, AF4, DRIVE_HIGH) +#define GPIO20_MMC1_DAT2 MFP_CFG_LPM(GPIO20, AF4, DRIVE_HIGH) +#define GPIO21_MMC1_DAT3 MFP_CFG_LPM(GPIO21, AF4, DRIVE_HIGH) + +#define GPIO28_MMC2_CLK MFP_CFG_LPM(GPIO28, AF4, PULL_HIGH) +#define GPIO29_MMC2_CMD MFP_CFG_LPM(GPIO29, AF4, PULL_HIGH) +#define GPIO30_MMC2_CLK MFP_CFG_LPM(GPIO30, AF3, PULL_HIGH) +#define GPIO31_MMC2_CMD MFP_CFG_LPM(GPIO31, AF3, PULL_HIGH) +#define GPIO79_MMC2_CLK MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH) +#define GPIO80_MMC2_CMD MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH) + +#define GPIO5_MMC2_DAT0 MFP_CFG_LPM(GPIO5, AF2, PULL_HIGH) +#define GPIO6_MMC2_DAT1 MFP_CFG_LPM(GPIO6, AF2, PULL_HIGH) +#define GPIO7_MMC2_DAT2 MFP_CFG_LPM(GPIO7, AF2, PULL_HIGH) +#define GPIO8_MMC2_DAT3 MFP_CFG_LPM(GPIO8, AF2, PULL_HIGH) +#define GPIO24_MMC2_DAT0 MFP_CFG_LPM(GPIO24, AF4, PULL_HIGH) +#define GPIO75_MMC2_DAT0 MFP_CFG_LPM(GPIO75, AF4, PULL_HIGH) +#define GPIO25_MMC2_DAT1 MFP_CFG_LPM(GPIO25, AF4, PULL_HIGH) +#define GPIO76_MMC2_DAT1 MFP_CFG_LPM(GPIO76, AF4, PULL_HIGH) +#define GPIO26_MMC2_DAT2 MFP_CFG_LPM(GPIO26, AF4, PULL_HIGH) +#define GPIO77_MMC2_DAT2 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH) +#define GPIO27_MMC2_DAT3 MFP_CFG_LPM(GPIO27, AF4, PULL_HIGH) +#define GPIO78_MMC2_DAT3 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH) + +/* 1-Wire */ +#define GPIO14_ONE_WIRE MFP_CFG_LPM(GPIO14, AF5, FLOAT) +#define GPIO0_2_ONE_WIRE MFP_CFG_LPM(GPIO0_2, AF2, FLOAT) + +/* SSP1 */ +#define GPIO87_SSP1_EXTCLK MFP_CFG(GPIO87, AF1) +#define GPIO88_SSP1_SYSCLK MFP_CFG(GPIO88, AF1) +#define GPIO83_SSP1_SCLK MFP_CFG(GPIO83, AF1) +#define GPIO84_SSP1_SFRM MFP_CFG(GPIO84, AF1) +#define GPIO85_SSP1_RXD MFP_CFG(GPIO85, AF6) +#define GPIO85_SSP1_TXD MFP_CFG(GPIO85, AF1) +#define GPIO86_SSP1_RXD MFP_CFG(GPIO86, AF1) +#define GPIO86_SSP1_TXD MFP_CFG(GPIO86, AF6) + +/* SSP2 */ +#define GPIO39_SSP2_EXTCLK MFP_CFG(GPIO39, AF2) +#define GPIO40_SSP2_SYSCLK MFP_CFG(GPIO40, AF2) +#define GPIO12_SSP2_SCLK MFP_CFG(GPIO12, AF2) +#define GPIO35_SSP2_SCLK MFP_CFG(GPIO35, AF2) +#define GPIO36_SSP2_SFRM MFP_CFG(GPIO36, AF2) +#define GPIO37_SSP2_RXD MFP_CFG(GPIO37, AF5) +#define GPIO37_SSP2_TXD MFP_CFG(GPIO37, AF2) +#define GPIO38_SSP2_RXD MFP_CFG(GPIO38, AF2) +#define GPIO38_SSP2_TXD MFP_CFG(GPIO38, AF5) + +#define GPIO69_SSP3_SCLK MFP_CFG(GPIO69, AF2, DS08X, FLOAT) +#define GPIO70_SSP3_FRM MFP_CFG(GPIO70, AF2, DS08X, DRIVE_LOW) +#define GPIO89_SSP3_SCLK MFP_CFG(GPIO89, AF1, DS08X, FLOAT) +#define GPIO90_SSP3_FRM MFP_CFG(GPIO90, AF1, DS08X, DRIVE_LOW) +#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF5, DS08X, FLOAT) +#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF2, DS08X, DRIVE_LOW) +#define GPIO72_SSP3_RXD MFP_CFG_X(GPIO72, AF2, DS08X, FLOAT) +#define GPIO72_SSP3_TXD MFP_CFG_X(GPIO72, AF5, DS08X, DRIVE_LOW) +#define GPIO91_SSP3_RXD MFP_CFG_X(GPIO91, AF5, DS08X, FLOAT) +#define GPIO91_SSP3_TXD MFP_CFG_X(GPIO91, AF1, DS08X, DRIVE_LOW) +#define GPIO92_SSP3_RXD MFP_CFG_X(GPIO92, AF1, DS08X, FLOAT) +#define GPIO92_SSP3_TXD MFP_CFG_X(GPIO92, AF5, DS08X, DRIVE_LOW) + +#define GPIO93_SSP4_SCLK MFP_CFG_LPM(GPIO93, AF1, PULL_HIGH) +#define GPIO94_SSP4_FRM MFP_CFG_LPM(GPIO94, AF1, PULL_HIGH) +#define GPIO94_SSP4_RXD MFP_CFG_LPM(GPIO94, AF5, PULL_HIGH) +#define GPIO95_SSP4_RXD MFP_CFG_LPM(GPIO95, AF5, PULL_HIGH) +#define GPIO95_SSP4_TXD MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH) +#define GPIO96_SSP4_RXD MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH) +#define GPIO96_SSP4_TXD MFP_CFG_LPM(GPIO96, AF5, PULL_HIGH) + +/* UART1 */ +#define GPIO41_UART1_RXD MFP_CFG_LPM(GPIO41, AF2, FLOAT) +#define GPIO41_UART1_TXD MFP_CFG_LPM(GPIO41, AF4, FLOAT) +#define GPIO42_UART1_RXD MFP_CFG_LPM(GPIO42, AF4, FLOAT) +#define GPIO42_UART1_TXD MFP_CFG_LPM(GPIO42, AF2, FLOAT) +#define GPIO97_UART1_RXD MFP_CFG_LPM(GPIO97, AF1, FLOAT) +#define GPIO97_UART1_TXD MFP_CFG_LPM(GPIO97, AF6, FLOAT) +#define GPIO98_UART1_RXD MFP_CFG_LPM(GPIO98, AF6, FLOAT) +#define GPIO98_UART1_TXD MFP_CFG_LPM(GPIO98, AF1, FLOAT) +#define GPIO43_UART1_CTS MFP_CFG_LPM(GPIO43, AF2, FLOAT) +#define GPIO43_UART1_RTS MFP_CFG_LPM(GPIO43, AF4, FLOAT) +#define GPIO48_UART1_CTS MFP_CFG_LPM(GPIO48, AF4, FLOAT) +#define GPIO48_UART1_RTS MFP_CFG_LPM(GPIO48, AF2, FLOAT) +#define GPIO99_UART1_CTS MFP_CFG_LPM(GPIO99, AF1, FLOAT) +#define GPIO99_UART1_RTS MFP_CFG_LPM(GPIO99, AF6, FLOAT) +#define GPIO104_UART1_CTS MFP_CFG_LPM(GPIO104, AF6, FLOAT) +#define GPIO104_UART1_RTS MFP_CFG_LPM(GPIO104, AF1, FLOAT) +#define GPIO45_UART1_DTR MFP_CFG_LPM(GPIO45, AF4, FLOAT) +#define GPIO45_UART1_DSR MFP_CFG_LPM(GPIO45, AF2, FLOAT) +#define GPIO47_UART1_DTR MFP_CFG_LPM(GPIO47, AF2, FLOAT) +#define GPIO47_UART1_DSR MFP_CFG_LPM(GPIO47, AF4, FLOAT) +#define GPIO101_UART1_DTR MFP_CFG_LPM(GPIO101, AF6, FLOAT) +#define GPIO101_UART1_DSR MFP_CFG_LPM(GPIO101, AF1, FLOAT) +#define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF1, FLOAT) +#define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF6, FLOAT) +#define GPIO44_UART1_DCD MFP_CFG_LPM(GPIO44, AF2, FLOAT) +#define GPIO100_UART1_DCD MFP_CFG_LPM(GPIO100, AF1, FLOAT) +#define GPIO46_UART1_RI MFP_CFG_LPM(GPIO46, AF2, FLOAT) +#define GPIO102_UART1_RI MFP_CFG_LPM(GPIO102, AF1, FLOAT) + +/* UART2 */ +#define GPIO109_UART2_CTS MFP_CFG_LPM(GPIO109, AF3, FLOAT) +#define GPIO109_UART2_RTS MFP_CFG_LPM(GPIO109, AF1, FLOAT) +#define GPIO112_UART2_CTS MFP_CFG_LPM(GPIO112, AF1, FLOAT) +#define GPIO112_UART2_RTS MFP_CFG_LPM(GPIO112, AF3, FLOAT) +#define GPIO110_UART2_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT) +#define GPIO110_UART2_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT) +#define GPIO111_UART2_RXD MFP_CFG_LPM(GPIO111, AF3, FLOAT) +#define GPIO111_UART2_TXD MFP_CFG_LPM(GPIO111, AF1, FLOAT) + +/* UART3 */ +#define GPIO89_UART3_CTS MFP_CFG_LPM(GPIO89, AF2, FLOAT) +#define GPIO89_UART3_RTS MFP_CFG_LPM(GPIO89, AF4, FLOAT) +#define GPIO90_UART3_CTS MFP_CFG_LPM(GPIO90, AF4, FLOAT) +#define GPIO90_UART3_RTS MFP_CFG_LPM(GPIO90, AF2, FLOAT) +#define GPIO105_UART3_CTS MFP_CFG_LPM(GPIO105, AF1, FLOAT) +#define GPIO105_UART3_RTS MFP_CFG_LPM(GPIO105, AF3, FLOAT) +#define GPIO106_UART3_CTS MFP_CFG_LPM(GPIO106, AF3, FLOAT) +#define GPIO106_UART3_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT) +#define GPIO30_UART3_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT) +#define GPIO30_UART3_TXD MFP_CFG_LPM(GPIO30, AF6, FLOAT) +#define GPIO31_UART3_RXD MFP_CFG_LPM(GPIO31, AF6, FLOAT) +#define GPIO31_UART3_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT) +#define GPIO91_UART3_RXD MFP_CFG_LPM(GPIO91, AF4, FLOAT) +#define GPIO91_UART3_TXD MFP_CFG_LPM(GPIO91, AF2, FLOAT) +#define GPIO92_UART3_RXD MFP_CFG_LPM(GPIO92, AF2, FLOAT) +#define GPIO92_UART3_TXD MFP_CFG_LPM(GPIO92, AF4, FLOAT) +#define GPIO107_UART3_RXD MFP_CFG_LPM(GPIO107, AF3, FLOAT) +#define GPIO107_UART3_TXD MFP_CFG_LPM(GPIO107, AF1, FLOAT) +#define GPIO108_UART3_RXD MFP_CFG_LPM(GPIO108, AF1, FLOAT) +#define GPIO108_UART3_TXD MFP_CFG_LPM(GPIO108, AF3, FLOAT) + + +/* USB 2.0 UTMI */ +#define GPIO10_UTM_CLK MFP_CFG(GPIO10, AF1) +#define GPIO36_U2D_RXERROR MFP_CFG(GPIO36, AF3) +#define GPIO60_U2D_RXERROR MFP_CFG(GPIO60, AF1) +#define GPIO87_U2D_RXERROR MFP_CFG(GPIO87, AF5) +#define GPIO34_UTM_RXVALID MFP_CFG(GPIO34, AF3) +#define GPIO58_UTM_RXVALID MFP_CFG(GPIO58, AF2) +#define GPIO85_UTM_RXVALID MFP_CFG(GPIO85, AF5) +#define GPIO35_UTM_RXACTIVE MFP_CFG(GPIO35, AF3) +#define GPIO59_UTM_RXACTIVE MFP_CFG(GPIO59, AF1) +#define GPIO86_UTM_RXACTIVE MFP_CFG(GPIO86, AF5) +#define GPIO73_UTM_TXREADY MFP_CFG(GPIO73, AF1) +#define GPIO68_UTM_LINESTATE_0 MFP_CFG(GPIO68, AF3) +#define GPIO90_UTM_LINESTATE_0 MFP_CFG(GPIO90, AF3) +#define GPIO102_UTM_LINESTATE_0 MFP_CFG(GPIO102, AF3) +#define GPIO107_UTM_LINESTATE_0 MFP_CFG(GPIO107, AF4) +#define GPIO69_UTM_LINESTATE_1 MFP_CFG(GPIO69, AF3) +#define GPIO91_UTM_LINESTATE_1 MFP_CFG(GPIO91, AF3) +#define GPIO103_UTM_LINESTATE_1 MFP_CFG(GPIO103, AF3) + +#define GPIO41_U2D_PHYDATA_0 MFP_CFG(GPIO41, AF3) +#define GPIO42_U2D_PHYDATA_1 MFP_CFG(GPIO42, AF3) +#define GPIO43_U2D_PHYDATA_2 MFP_CFG(GPIO43, AF3) +#define GPIO44_U2D_PHYDATA_3 MFP_CFG(GPIO44, AF3) +#define GPIO45_U2D_PHYDATA_4 MFP_CFG(GPIO45, AF3) +#define GPIO46_U2D_PHYDATA_5 MFP_CFG(GPIO46, AF3) +#define GPIO47_U2D_PHYDATA_6 MFP_CFG(GPIO47, AF3) +#define GPIO48_U2D_PHYDATA_7 MFP_CFG(GPIO48, AF3) + +#define GPIO49_U2D_PHYDATA_0 MFP_CFG(GPIO49, AF3) +#define GPIO50_U2D_PHYDATA_1 MFP_CFG(GPIO50, AF3) +#define GPIO51_U2D_PHYDATA_2 MFP_CFG(GPIO51, AF3) +#define GPIO52_U2D_PHYDATA_3 MFP_CFG(GPIO52, AF3) +#define GPIO53_U2D_PHYDATA_4 MFP_CFG(GPIO53, AF3) +#define GPIO54_U2D_PHYDATA_5 MFP_CFG(GPIO54, AF3) +#define GPIO55_U2D_PHYDATA_6 MFP_CFG(GPIO55, AF3) +#define GPIO56_U2D_PHYDATA_7 MFP_CFG(GPIO56, AF3) + +#define GPIO37_U2D_OPMODE0 MFP_CFG(GPIO37, AF4) +#define GPIO61_U2D_OPMODE0 MFP_CFG(GPIO61, AF2) +#define GPIO88_U2D_OPMODE0 MFP_CFG(GPIO88, AF7) + +#define GPIO38_U2D_OPMODE1 MFP_CFG(GPIO38, AF4) +#define GPIO62_U2D_OPMODE1 MFP_CFG(GPIO62, AF2) +#define GPIO104_U2D_OPMODE1 MFP_CFG(GPIO104, AF4) +#define GPIO108_U2D_OPMODE1 MFP_CFG(GPIO108, AF5) + +#define GPIO74_U2D_RESET MFP_CFG(GPIO74, AF1) +#define GPIO93_U2D_RESET MFP_CFG(GPIO93, AF2) +#define GPIO98_U2D_RESET MFP_CFG(GPIO98, AF3) + +#define GPIO67_U2D_SUSPEND MFP_CFG(GPIO67, AF3) +#define GPIO96_U2D_SUSPEND MFP_CFG(GPIO96, AF2) +#define GPIO101_U2D_SUSPEND MFP_CFG(GPIO101, AF3) + +#define GPIO66_U2D_TERM_SEL MFP_CFG(GPIO66, AF5) +#define GPIO95_U2D_TERM_SEL MFP_CFG(GPIO95, AF3) +#define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF7) +#define GPIO100_U2D_TERM_SEL MFP_CFG(GPIO100, AF5) + +#define GPIO39_U2D_TXVALID MFP_CFG(GPIO39, AF4) +#define GPIO70_U2D_TXVALID MFP_CFG(GPIO70, AF5) +#define GPIO83_U2D_TXVALID MFP_CFG(GPIO83, AF7) + +#define GPIO65_U2D_XCVR_SEL MFP_CFG(GPIO65, AF5) +#define GPIO94_U2D_XCVR_SEL MFP_CFG(GPIO94, AF3) +#define GPIO99_U2D_XCVR_SEL MFP_CFG(GPIO99, AF5) + +/* USB Host 1.1 */ +#define GPIO2_2_USBH_PEN MFP_CFG(GPIO2_2, AF1) +#define GPIO3_2_USBH_PWR MFP_CFG(GPIO3_2, AF1) + +/* USB P2 */ +#define GPIO97_USB_P2_2 MFP_CFG(GPIO97, AF2) +#define GPIO97_USB_P2_6 MFP_CFG(GPIO97, AF4) +#define GPIO98_USB_P2_2 MFP_CFG(GPIO98, AF4) +#define GPIO98_USB_P2_6 MFP_CFG(GPIO98, AF2) +#define GPIO99_USB_P2_1 MFP_CFG(GPIO99, AF2) +#define GPIO100_USB_P2_4 MFP_CFG(GPIO100, AF2) +#define GPIO101_USB_P2_8 MFP_CFG(GPIO101, AF2) +#define GPIO102_USB_P2_3 MFP_CFG(GPIO102, AF2) +#define GPIO103_USB_P2_5 MFP_CFG(GPIO103, AF2) +#define GPIO104_USB_P2_7 MFP_CFG(GPIO104, AF2) + +/* USB P3 */ +#define GPIO75_USB_P3_1 MFP_CFG(GPIO75, AF2) +#define GPIO76_USB_P3_2 MFP_CFG(GPIO76, AF2) +#define GPIO77_USB_P3_3 MFP_CFG(GPIO77, AF2) +#define GPIO78_USB_P3_4 MFP_CFG(GPIO78, AF2) +#define GPIO79_USB_P3_5 MFP_CFG(GPIO79, AF2) +#define GPIO80_USB_P3_6 MFP_CFG(GPIO80, AF2) + +#define GPIO13_CHOUT0 MFP_CFG(GPIO13, AF6) +#define GPIO14_CHOUT1 MFP_CFG(GPIO14, AF6) + +#define GPIO2_RDY MFP_CFG(GPIO2, AF1) +#define GPIO5_NPIOR MFP_CFG(GPIO5, AF3) + +#define GPIO11_PWM0_OUT MFP_CFG(GPIO11, AF1) +#define GPIO12_PWM1_OUT MFP_CFG(GPIO12, AF1) +#define GPIO13_PWM2_OUT MFP_CFG(GPIO13, AF1) +#define GPIO14_PWM3_OUT MFP_CFG(GPIO14, AF1) + +#endif /* __ASM_ARCH_MFP_PXA320_H */ diff --git a/include/asm-arm/arch-pxa/mfp.h b/include/asm-arm/arch-pxa/mfp.h new file mode 100644 index 000000000000..60291742ffdd --- /dev/null +++ b/include/asm-arm/arch-pxa/mfp.h @@ -0,0 +1,576 @@ +/* + * linux/include/asm-arm/arch-pxa/mfp.h + * + * Multi-Function Pin Definitions + * + * Copyright (C) 2007 Marvell International Ltd. + * + * 2007-8-21: eric miao + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MFP_H +#define __ASM_ARCH_MFP_H + +#define MFPR_BASE (0x40e10000) +#define MFPR_SIZE (PAGE_SIZE) + +#define mfp_to_gpio(m) ((m) % 128) + +/* list of all the configurable MFP pins */ +enum { + MFP_PIN_INVALID = -1, + + MFP_PIN_GPIO0 = 0, + MFP_PIN_GPIO1, + MFP_PIN_GPIO2, + MFP_PIN_GPIO3, + MFP_PIN_GPIO4, + MFP_PIN_GPIO5, + MFP_PIN_GPIO6, + MFP_PIN_GPIO7, + MFP_PIN_GPIO8, + MFP_PIN_GPIO9, + MFP_PIN_GPIO10, + MFP_PIN_GPIO11, + MFP_PIN_GPIO12, + MFP_PIN_GPIO13, + MFP_PIN_GPIO14, + MFP_PIN_GPIO15, + MFP_PIN_GPIO16, + MFP_PIN_GPIO17, + MFP_PIN_GPIO18, + MFP_PIN_GPIO19, + MFP_PIN_GPIO20, + MFP_PIN_GPIO21, + MFP_PIN_GPIO22, + MFP_PIN_GPIO23, + MFP_PIN_GPIO24, + MFP_PIN_GPIO25, + MFP_PIN_GPIO26, + MFP_PIN_GPIO27, + MFP_PIN_GPIO28, + MFP_PIN_GPIO29, + MFP_PIN_GPIO30, + MFP_PIN_GPIO31, + MFP_PIN_GPIO32, + MFP_PIN_GPIO33, + MFP_PIN_GPIO34, + MFP_PIN_GPIO35, + MFP_PIN_GPIO36, + MFP_PIN_GPIO37, + MFP_PIN_GPIO38, + MFP_PIN_GPIO39, + MFP_PIN_GPIO40, + MFP_PIN_GPIO41, + MFP_PIN_GPIO42, + MFP_PIN_GPIO43, + MFP_PIN_GPIO44, + MFP_PIN_GPIO45, + MFP_PIN_GPIO46, + MFP_PIN_GPIO47, + MFP_PIN_GPIO48, + MFP_PIN_GPIO49, + MFP_PIN_GPIO50, + MFP_PIN_GPIO51, + MFP_PIN_GPIO52, + MFP_PIN_GPIO53, + MFP_PIN_GPIO54, + MFP_PIN_GPIO55, + MFP_PIN_GPIO56, + MFP_PIN_GPIO57, + MFP_PIN_GPIO58, + MFP_PIN_GPIO59, + MFP_PIN_GPIO60, + MFP_PIN_GPIO61, + MFP_PIN_GPIO62, + MFP_PIN_GPIO63, + MFP_PIN_GPIO64, + MFP_PIN_GPIO65, + MFP_PIN_GPIO66, + MFP_PIN_GPIO67, + MFP_PIN_GPIO68, + MFP_PIN_GPIO69, + MFP_PIN_GPIO70, + MFP_PIN_GPIO71, + MFP_PIN_GPIO72, + MFP_PIN_GPIO73, + MFP_PIN_GPIO74, + MFP_PIN_GPIO75, + MFP_PIN_GPIO76, + MFP_PIN_GPIO77, + MFP_PIN_GPIO78, + MFP_PIN_GPIO79, + MFP_PIN_GPIO80, + MFP_PIN_GPIO81, + MFP_PIN_GPIO82, + MFP_PIN_GPIO83, + MFP_PIN_GPIO84, + MFP_PIN_GPIO85, + MFP_PIN_GPIO86, + MFP_PIN_GPIO87, + MFP_PIN_GPIO88, + MFP_PIN_GPIO89, + MFP_PIN_GPIO90, + MFP_PIN_GPIO91, + MFP_PIN_GPIO92, + MFP_PIN_GPIO93, + MFP_PIN_GPIO94, + MFP_PIN_GPIO95, + MFP_PIN_GPIO96, + MFP_PIN_GPIO97, + MFP_PIN_GPIO98, + MFP_PIN_GPIO99, + MFP_PIN_GPIO100, + MFP_PIN_GPIO101, + MFP_PIN_GPIO102, + MFP_PIN_GPIO103, + MFP_PIN_GPIO104, + MFP_PIN_GPIO105, + MFP_PIN_GPIO106, + MFP_PIN_GPIO107, + MFP_PIN_GPIO108, + MFP_PIN_GPIO109, + MFP_PIN_GPIO110, + MFP_PIN_GPIO111, + MFP_PIN_GPIO112, + MFP_PIN_GPIO113, + MFP_PIN_GPIO114, + MFP_PIN_GPIO115, + MFP_PIN_GPIO116, + MFP_PIN_GPIO117, + MFP_PIN_GPIO118, + MFP_PIN_GPIO119, + MFP_PIN_GPIO120, + MFP_PIN_GPIO121, + MFP_PIN_GPIO122, + MFP_PIN_GPIO123, + MFP_PIN_GPIO124, + MFP_PIN_GPIO125, + MFP_PIN_GPIO126, + MFP_PIN_GPIO127, + MFP_PIN_GPIO0_2, + MFP_PIN_GPIO1_2, + MFP_PIN_GPIO2_2, + MFP_PIN_GPIO3_2, + MFP_PIN_GPIO4_2, + MFP_PIN_GPIO5_2, + MFP_PIN_GPIO6_2, + MFP_PIN_GPIO7_2, + MFP_PIN_GPIO8_2, + MFP_PIN_GPIO9_2, + MFP_PIN_GPIO10_2, + MFP_PIN_GPIO11_2, + MFP_PIN_GPIO12_2, + MFP_PIN_GPIO13_2, + MFP_PIN_GPIO14_2, + MFP_PIN_GPIO15_2, + MFP_PIN_GPIO16_2, + MFP_PIN_GPIO17_2, + + MFP_PIN_ULPI_STP, + MFP_PIN_ULPI_NXT, + MFP_PIN_ULPI_DIR, + + MFP_PIN_nXCVREN, + MFP_PIN_DF_CLE_nOE, + MFP_PIN_DF_nADV1_ALE, + MFP_PIN_DF_SCLK_E, + MFP_PIN_DF_SCLK_S, + MFP_PIN_nBE0, + MFP_PIN_nBE1, + MFP_PIN_DF_nADV2_ALE, + MFP_PIN_DF_INT_RnB, + MFP_PIN_DF_nCS0, + MFP_PIN_DF_nCS1, + MFP_PIN_nLUA, + MFP_PIN_nLLA, + MFP_PIN_DF_nWE, + MFP_PIN_DF_ALE_nWE, + MFP_PIN_DF_nRE_nOE, + MFP_PIN_DF_ADDR0, + MFP_PIN_DF_ADDR1, + MFP_PIN_DF_ADDR2, + MFP_PIN_DF_ADDR3, + MFP_PIN_DF_IO0, + MFP_PIN_DF_IO1, + MFP_PIN_DF_IO2, + MFP_PIN_DF_IO3, + MFP_PIN_DF_IO4, + MFP_PIN_DF_IO5, + MFP_PIN_DF_IO6, + MFP_PIN_DF_IO7, + MFP_PIN_DF_IO8, + MFP_PIN_DF_IO9, + MFP_PIN_DF_IO10, + MFP_PIN_DF_IO11, + MFP_PIN_DF_IO12, + MFP_PIN_DF_IO13, + MFP_PIN_DF_IO14, + MFP_PIN_DF_IO15, + + MFP_PIN_MAX, +}; + +/* + * Table that determines the low power modes outputs, with actual settings + * used in parentheses for don't-care values. Except for the float output, + * the configured driven and pulled levels match, so if there is a need for + * non-LPM pulled output, the same configuration could probably be used. + * + * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel + * (bit 7) (bit 8) (bit 14d) (bit 13d) + * + * Drive 0 0 0 0 X (1) 0 + * Drive 1 0 1 X (1) 0 0 + * Pull hi (1) 1 X(1) 1 0 0 + * Pull lo (0) 1 X(0) 0 1 0 + * Z (float) 1 X(0) 0 0 0 + */ +#define MFP_LPM_DRIVE_LOW 0x8 +#define MFP_LPM_DRIVE_HIGH 0x6 +#define MFP_LPM_PULL_HIGH 0x7 +#define MFP_LPM_PULL_LOW 0x9 +#define MFP_LPM_FLOAT 0x1 +#define MFP_LPM_PULL_NEITHER 0x0 + +/* + * The pullup and pulldown state of the MFP pin is by default determined by + * selected alternate function. In case some buggy devices need to override + * this default behavior, pxa3xx_mfp_set_pull() can be invoked with one of + * the following definition as the parameter. + * + * Definition pull_sel pullup_en pulldown_en + * MFP_PULL_HIGH 1 1 0 + * MFP_PULL_LOW 1 0 1 + * MFP_PULL_BOTH 1 1 1 + * MFP_PULL_NONE 1 0 0 + * MFP_PULL_DEFAULT 0 X X + * + * NOTE: pxa3xx_mfp_set_pull() will modify the PULLUP_EN and PULLDOWN_EN + * bits, which will cause potential conflicts with the low power mode + * setting, device drivers should take care of this + */ +#define MFP_PULL_BOTH (0x7u) +#define MFP_PULL_HIGH (0x6u) +#define MFP_PULL_LOW (0x5u) +#define MFP_PULL_NONE (0x4u) +#define MFP_PULL_DEFAULT (0x0u) + +#define MFP_AF0 (0) +#define MFP_AF1 (1) +#define MFP_AF2 (2) +#define MFP_AF3 (3) +#define MFP_AF4 (4) +#define MFP_AF5 (5) +#define MFP_AF6 (6) +#define MFP_AF7 (7) + +#define MFP_DS01X (0) +#define MFP_DS02X (1) +#define MFP_DS03X (2) +#define MFP_DS04X (3) +#define MFP_DS06X (4) +#define MFP_DS08X (5) +#define MFP_DS10X (6) +#define MFP_DS12X (7) + +#define MFP_EDGE_BOTH 0x3 +#define MFP_EDGE_RISE 0x2 +#define MFP_EDGE_FALL 0x1 +#define MFP_EDGE_NONE 0x0 + +#define MFPR_AF_MASK 0x0007 +#define MFPR_DRV_MASK 0x1c00 +#define MFPR_RDH_MASK 0x0200 +#define MFPR_LPM_MASK 0xe180 +#define MFPR_PULL_MASK 0xe000 +#define MFPR_EDGE_MASK 0x0070 + +#define MFPR_ALT_OFFSET 0 +#define MFPR_ERE_OFFSET 4 +#define MFPR_EFE_OFFSET 5 +#define MFPR_EC_OFFSET 6 +#define MFPR_SON_OFFSET 7 +#define MFPR_SD_OFFSET 8 +#define MFPR_SS_OFFSET 9 +#define MFPR_DRV_OFFSET 10 +#define MFPR_PD_OFFSET 13 +#define MFPR_PU_OFFSET 14 +#define MFPR_PS_OFFSET 15 + +#define MFPR(af, drv, rdh, lpm, edge) \ + (((af) & 0x7) | (((drv) & 0x7) << 10) |\ + (((rdh) & 0x1) << 9) |\ + (((lpm) & 0x3) << 7) |\ + (((lpm) & 0x4) << 12)|\ + (((lpm) & 0x8) << 10)|\ + ((!(edge)) << 6) |\ + (((edge) & 0x1) << 5) |\ + (((edge) & 0x2) << 3)) + +/* + * a possible MFP configuration is represented by a 32-bit integer + * bit 0..15 - MFPR value (16-bit) + * bit 16..31 - mfp pin index (used to obtain the MFPR offset) + * + * to facilitate the definition, the following macros are provided + * + * MFPR_DEFAULT - default MFPR value, with + * alternate function = 0, + * drive strength = fast 1mA (MFP_DS01X) + * low power mode = default + * release dalay hold = false (RDH bit) + * edge detection = none + * + * MFP_CFG - default MFPR value with alternate function + * MFP_CFG_DRV - default MFPR value with alternate function and + * pin drive strength + * MFP_CFG_LPM - default MFPR value with alternate function and + * low power mode + * MFP_CFG_X - default MFPR value with alternate function, + * pin drive strength and low power mode + * + * use + * + * MFP_CFG_PIN - to get the MFP pin index + * MFP_CFG_VAL - to get the corresponding MFPR value + */ + +typedef uint32_t mfp_cfg_t; + +#define MFP_CFG_PIN(mfp_cfg) (((mfp_cfg) >> 16) & 0xffff) +#define MFP_CFG_VAL(mfp_cfg) ((mfp_cfg) & 0xffff) + +#define MFPR_DEFAULT (0x0000) + +#define MFP_CFG(pin, af) \ + ((MFP_PIN_##pin << 16) | MFPR_DEFAULT | (MFP_##af)) + +#define MFP_CFG_DRV(pin, af, drv) \ + ((MFP_PIN_##pin << 16) | MFPR_DEFAULT |\ + ((MFP_##drv) << 10) | (MFP_##af)) + +#define MFP_CFG_LPM(pin, af, lpm) \ + ((MFP_PIN_##pin << 16) | MFPR_DEFAULT | (MFP_##af) |\ + (((MFP_LPM_##lpm) & 0x3) << 7) |\ + (((MFP_LPM_##lpm) & 0x4) << 12) |\ + (((MFP_LPM_##lpm) & 0x8) << 10)) + +#define MFP_CFG_X(pin, af, drv, lpm) \ + ((MFP_PIN_##pin << 16) | MFPR_DEFAULT |\ + ((MFP_##drv) << 10) | (MFP_##af) |\ + (((MFP_LPM_##lpm) & 0x3) << 7) |\ + (((MFP_LPM_##lpm) & 0x4) << 12) |\ + (((MFP_LPM_##lpm) & 0x8) << 10)) + +/* common MFP configurations - processor specific ones defined + * in mfp-pxa3xx.h + */ +#define GPIO0_GPIO MFP_CFG(GPIO0, AF0) +#define GPIO1_GPIO MFP_CFG(GPIO1, AF0) +#define GPIO2_GPIO MFP_CFG(GPIO2, AF0) +#define GPIO3_GPIO MFP_CFG(GPIO3, AF0) +#define GPIO4_GPIO MFP_CFG(GPIO4, AF0) +#define GPIO5_GPIO MFP_CFG(GPIO5, AF0) +#define GPIO6_GPIO MFP_CFG(GPIO6, AF0) +#define GPIO7_GPIO MFP_CFG(GPIO7, AF0) +#define GPIO8_GPIO MFP_CFG(GPIO8, AF0) +#define GPIO9_GPIO MFP_CFG(GPIO9, AF0) +#define GPIO10_GPIO MFP_CFG(GPIO10, AF0) +#define GPIO11_GPIO MFP_CFG(GPIO11, AF0) +#define GPIO12_GPIO MFP_CFG(GPIO12, AF0) +#define GPIO13_GPIO MFP_CFG(GPIO13, AF0) +#define GPIO14_GPIO MFP_CFG(GPIO14, AF0) +#define GPIO15_GPIO MFP_CFG(GPIO15, AF0) +#define GPIO16_GPIO MFP_CFG(GPIO16, AF0) +#define GPIO17_GPIO MFP_CFG(GPIO17, AF0) +#define GPIO18_GPIO MFP_CFG(GPIO18, AF0) +#define GPIO19_GPIO MFP_CFG(GPIO19, AF0) +#define GPIO20_GPIO MFP_CFG(GPIO20, AF0) +#define GPIO21_GPIO MFP_CFG(GPIO21, AF0) +#define GPIO22_GPIO MFP_CFG(GPIO22, AF0) +#define GPIO23_GPIO MFP_CFG(GPIO23, AF0) +#define GPIO24_GPIO MFP_CFG(GPIO24, AF0) +#define GPIO25_GPIO MFP_CFG(GPIO25, AF0) +#define GPIO26_GPIO MFP_CFG(GPIO26, AF0) +#define GPIO27_GPIO MFP_CFG(GPIO27, AF0) +#define GPIO28_GPIO MFP_CFG(GPIO28, AF0) +#define GPIO29_GPIO MFP_CFG(GPIO29, AF0) +#define GPIO30_GPIO MFP_CFG(GPIO30, AF0) +#define GPIO31_GPIO MFP_CFG(GPIO31, AF0) +#define GPIO32_GPIO MFP_CFG(GPIO32, AF0) +#define GPIO33_GPIO MFP_CFG(GPIO33, AF0) +#define GPIO34_GPIO MFP_CFG(GPIO34, AF0) +#define GPIO35_GPIO MFP_CFG(GPIO35, AF0) +#define GPIO36_GPIO MFP_CFG(GPIO36, AF0) +#define GPIO37_GPIO MFP_CFG(GPIO37, AF0) +#define GPIO38_GPIO MFP_CFG(GPIO38, AF0) +#define GPIO39_GPIO MFP_CFG(GPIO39, AF0) +#define GPIO40_GPIO MFP_CFG(GPIO40, AF0) +#define GPIO41_GPIO MFP_CFG(GPIO41, AF0) +#define GPIO42_GPIO MFP_CFG(GPIO42, AF0) +#define GPIO43_GPIO MFP_CFG(GPIO43, AF0) +#define GPIO44_GPIO MFP_CFG(GPIO44, AF0) +#define GPIO45_GPIO MFP_CFG(GPIO45, AF0) + +#define GPIO47_GPIO MFP_CFG(GPIO47, AF0) +#define GPIO48_GPIO MFP_CFG(GPIO48, AF0) + +#define GPIO53_GPIO MFP_CFG(GPIO53, AF0) +#define GPIO54_GPIO MFP_CFG(GPIO54, AF0) +#define GPIO55_GPIO MFP_CFG(GPIO55, AF0) + +#define GPIO57_GPIO MFP_CFG(GPIO57, AF0) + +#define GPIO63_GPIO MFP_CFG(GPIO63, AF0) +#define GPIO64_GPIO MFP_CFG(GPIO64, AF0) +#define GPIO65_GPIO MFP_CFG(GPIO65, AF0) +#define GPIO66_GPIO MFP_CFG(GPIO66, AF0) +#define GPIO67_GPIO MFP_CFG(GPIO67, AF0) +#define GPIO68_GPIO MFP_CFG(GPIO68, AF0) +#define GPIO69_GPIO MFP_CFG(GPIO69, AF0) +#define GPIO70_GPIO MFP_CFG(GPIO70, AF0) +#define GPIO71_GPIO MFP_CFG(GPIO71, AF0) +#define GPIO72_GPIO MFP_CFG(GPIO72, AF0) +#define GPIO73_GPIO MFP_CFG(GPIO73, AF0) +#define GPIO74_GPIO MFP_CFG(GPIO74, AF0) +#define GPIO75_GPIO MFP_CFG(GPIO75, AF0) +#define GPIO76_GPIO MFP_CFG(GPIO76, AF0) +#define GPIO77_GPIO MFP_CFG(GPIO77, AF0) +#define GPIO78_GPIO MFP_CFG(GPIO78, AF0) +#define GPIO79_GPIO MFP_CFG(GPIO79, AF0) +#define GPIO80_GPIO MFP_CFG(GPIO80, AF0) +#define GPIO81_GPIO MFP_CFG(GPIO81, AF0) +#define GPIO82_GPIO MFP_CFG(GPIO82, AF0) +#define GPIO83_GPIO MFP_CFG(GPIO83, AF0) +#define GPIO84_GPIO MFP_CFG(GPIO84, AF0) +#define GPIO85_GPIO MFP_CFG(GPIO85, AF0) +#define GPIO86_GPIO MFP_CFG(GPIO86, AF0) +#define GPIO87_GPIO MFP_CFG(GPIO87, AF0) +#define GPIO88_GPIO MFP_CFG(GPIO88, AF0) +#define GPIO89_GPIO MFP_CFG(GPIO89, AF0) +#define GPIO90_GPIO MFP_CFG(GPIO90, AF0) +#define GPIO91_GPIO MFP_CFG(GPIO91, AF0) +#define GPIO92_GPIO MFP_CFG(GPIO92, AF0) +#define GPIO93_GPIO MFP_CFG(GPIO93, AF0) +#define GPIO94_GPIO MFP_CFG(GPIO94, AF0) +#define GPIO95_GPIO MFP_CFG(GPIO95, AF0) +#define GPIO96_GPIO MFP_CFG(GPIO96, AF0) +#define GPIO97_GPIO MFP_CFG(GPIO97, AF0) +#define GPIO98_GPIO MFP_CFG(GPIO98, AF0) +#define GPIO99_GPIO MFP_CFG(GPIO99, AF0) +#define GPIO100_GPIO MFP_CFG(GPIO100, AF0) +#define GPIO101_GPIO MFP_CFG(GPIO101, AF0) +#define GPIO102_GPIO MFP_CFG(GPIO102, AF0) +#define GPIO103_GPIO MFP_CFG(GPIO103, AF0) +#define GPIO104_GPIO MFP_CFG(GPIO104, AF0) +#define GPIO105_GPIO MFP_CFG(GPIO105, AF0) +#define GPIO106_GPIO MFP_CFG(GPIO106, AF0) +#define GPIO107_GPIO MFP_CFG(GPIO107, AF0) +#define GPIO108_GPIO MFP_CFG(GPIO108, AF0) +#define GPIO109_GPIO MFP_CFG(GPIO109, AF0) +#define GPIO110_GPIO MFP_CFG(GPIO110, AF0) +#define GPIO111_GPIO MFP_CFG(GPIO111, AF0) +#define GPIO112_GPIO MFP_CFG(GPIO112, AF0) +#define GPIO113_GPIO MFP_CFG(GPIO113, AF0) +#define GPIO114_GPIO MFP_CFG(GPIO114, AF0) +#define GPIO115_GPIO MFP_CFG(GPIO115, AF0) +#define GPIO116_GPIO MFP_CFG(GPIO116, AF0) +#define GPIO117_GPIO MFP_CFG(GPIO117, AF0) +#define GPIO118_GPIO MFP_CFG(GPIO118, AF0) +#define GPIO119_GPIO MFP_CFG(GPIO119, AF0) +#define GPIO120_GPIO MFP_CFG(GPIO120, AF0) +#define GPIO121_GPIO MFP_CFG(GPIO121, AF0) +#define GPIO122_GPIO MFP_CFG(GPIO122, AF0) +#define GPIO123_GPIO MFP_CFG(GPIO123, AF0) +#define GPIO124_GPIO MFP_CFG(GPIO124, AF0) +#define GPIO125_GPIO MFP_CFG(GPIO125, AF0) +#define GPIO126_GPIO MFP_CFG(GPIO126, AF0) +#define GPIO127_GPIO MFP_CFG(GPIO127, AF0) + +#define GPIO0_2_GPIO MFP_CFG(GPIO0_2, AF0) +#define GPIO1_2_GPIO MFP_CFG(GPIO1_2, AF0) +#define GPIO2_2_GPIO MFP_CFG(GPIO2_2, AF0) +#define GPIO3_2_GPIO MFP_CFG(GPIO3_2, AF0) +#define GPIO4_2_GPIO MFP_CFG(GPIO4_2, AF0) +#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0) +#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0) + +/* + * each MFP pin will have a MFPR register, since the offset of the + * register varies between processors, the processor specific code + * should initialize the pin offsets by pxa3xx_mfp_init_addr() + * + * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map" + * structure, which represents a range of MFP pins from "start" to + * "end", with the offset begining at "offset", to define a single + * pin, let "end" = -1 + * + * use + * + * MFP_ADDR_X() to define a range of pins + * MFP_ADDR() to define a single pin + * MFP_ADDR_END to signal the end of pin offset definitions + */ +struct pxa3xx_mfp_addr_map { + unsigned int start; + unsigned int end; + unsigned long offset; +}; + +#define MFP_ADDR_X(start, end, offset) \ + { MFP_PIN_##start, MFP_PIN_##end, offset } + +#define MFP_ADDR(pin, offset) \ + { MFP_PIN_##pin, -1, offset } + +#define MFP_ADDR_END { MFP_PIN_INVALID, 0 } + +struct pxa3xx_mfp_pin { + unsigned long mfpr_off; /* MFPRxx register offset */ + unsigned long mfpr_val; /* MFPRxx register value */ +}; + +/* + * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access + * to the MFPR register + */ +unsigned long pxa3xx_mfp_read(int mfp); +void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val); + +/* + * pxa3xx_mfp_set_afds - set MFP alternate function and drive strength + * pxa3xx_mfp_set_rdh - set MFP release delay hold on/off + * pxa3xx_mfp_set_lpm - set MFP low power mode state + * pxa3xx_mfp_set_edge - set MFP edge detection in low power mode + * + * use these functions to override/change the default configuration + * done by pxa3xx_mfp_set_config(s) + */ +void pxa3xx_mfp_set_afds(int mfp, int af, int ds); +void pxa3xx_mfp_set_rdh(int mfp, int rdh); +void pxa3xx_mfp_set_lpm(int mfp, int lpm); +void pxa3xx_mfp_set_edge(int mfp, int edge); + +/* + * pxa3xx_mfp_config - configure the MFPR registers + * + * used by board specific initialization code + */ +void pxa3xx_mfp_config(mfp_cfg_t *mfp_cfgs, int num); + +/* + * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin + * index and MFPR register offset + * + * used by processor specific code + */ +void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *); +void __init pxa3xx_init_mfp(void); + +#endif /* __ASM_ARCH_MFP_H */ diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index e68b593d69da..67f53e07db86 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -1177,7 +1177,7 @@ #define GPIO_bit(x) (1 << ((x) & 0x1f)) -#ifdef CONFIG_PXA27x +#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) /* Interrupt Controller */ diff --git a/include/asm-arm/arch-pxa/pxa3xx-regs.h b/include/asm-arm/arch-pxa/pxa3xx-regs.h new file mode 100644 index 000000000000..3900a0ca0bc0 --- /dev/null +++ b/include/asm-arm/arch-pxa/pxa3xx-regs.h @@ -0,0 +1,75 @@ +/* + * linux/include/asm-arm/arch-pxa/pxa3xx-regs.h + * + * PXA3xx specific register definitions + * + * Copyright (C) 2007 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_PXA3XX_REGS_H +#define __ASM_ARCH_PXA3XX_REGS_H + +/* + * Application Subsystem Clock + */ +#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */ +#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */ +#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ +#define CKENA __REG(0x4134000C) /* A Clock Enable Register */ +#define CKENB __REG(0x41340010) /* B Clock Enable Register */ +#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ + +/* + * Clock Enable Bit + */ +#define CKEN_LCD 1 /* < LCD Clock Enable */ +#define CKEN_USBH 2 /* < USB host clock enable */ +#define CKEN_CAMERA 3 /* < Camera interface clock enable */ +#define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */ +#define CKEN_USB2 6 /* < USB 2.0 client clock enable. */ +#define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */ +#define CKEN_SMC 9 /* < Static Memory Controller clock enable */ +#define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */ +#define CKEN_BOOT 11 /* < Boot rom clock enable */ +#define CKEN_MMC1 12 /* < MMC1 Clock enable */ +#define CKEN_MMC2 13 /* < MMC2 clock enable */ +#define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */ +#define CKEN_CIR 15 /* < Consumer IR Clock Enable */ +#define CKEN_USIM0 17 /* < USIM[0] Clock Enable */ +#define CKEN_USIM1 18 /* < USIM[1] Clock Enable */ +#define CKEN_TPM 19 /* < TPM clock enable */ +#define CKEN_UDC 20 /* < UDC clock enable */ +#define CKEN_BTUART 21 /* < BTUART clock enable */ +#define CKEN_FFUART 22 /* < FFUART clock enable */ +#define CKEN_STUART 23 /* < STUART clock enable */ +#define CKEN_AC97 24 /* < AC97 clock enable */ +#define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */ +#define CKEN_SSP1 26 /* < SSP1 clock enable */ +#define CKEN_SSP2 27 /* < SSP2 clock enable */ +#define CKEN_SSP3 28 /* < SSP3 clock enable */ +#define CKEN_SSP4 29 /* < SSP4 clock enable */ +#define CKEN_MSL0 30 /* < MSL0 clock enable */ +#define CKEN_PWM0 32 /* < PWM[0] clock enable */ +#define CKEN_PWM1 33 /* < PWM[1] clock enable */ +#define CKEN_I2C 36 /* < I2C clock enable */ +#define CKEN_INTC 38 /* < Interrupt controller clock enable */ +#define CKEN_GPIO 39 /* < GPIO clock enable */ +#define CKEN_1WIRE 40 /* < 1-wire clock enable */ +#define CKEN_HSIO2 41 /* < HSIO2 clock enable */ +#define CKEN_MINI_IM 48 /* < Mini-IM */ +#define CKEN_MINI_LCD 49 /* < Mini LCD */ + +#if defined(CONFIG_CPU_PXA310) +#define CKEN_MMC3 5 /* < MMC3 Clock Enable */ +#define CKEN_MVED 43 /* < MVED clock enable */ +#endif + +/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */ +#define PXA300_CKEN_GRAPHICS 42 /* Graphics controller clock enable */ +#define PXA320_CKEN_GRAPHICS 7 /* Graphics controller clock enable */ + +#endif /* __ASM_ARCH_PXA3XX_REGS_H */ diff --git a/include/asm-arm/arch-pxa/timex.h b/include/asm-arm/arch-pxa/timex.h index 2473bb51d0a6..8d882f0b6a16 100644 --- a/include/asm-arm/arch-pxa/timex.h +++ b/include/asm-arm/arch-pxa/timex.h @@ -21,4 +21,6 @@ #else #define CLOCK_TICK_RATE 3250000 #endif +#else +#define CLOCK_TICK_RATE 3250000 #endif diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h new file mode 100644 index 000000000000..f58b59162b82 --- /dev/null +++ b/include/asm-arm/arch-pxa/zylonite.h @@ -0,0 +1,35 @@ +#ifndef __ASM_ARCH_ZYLONITE_H +#define __ASM_ARCH_ZYLONITE_H + +#define ZYLONITE_ETH_PHYS 0x14000000 + +/* the following variables are processor specific and initialized + * by the corresponding zylonite_pxa3xx_init() + */ +extern int gpio_backlight; +extern int gpio_eth_irq; + +extern int lcd_id; +extern int lcd_orientation; + +#ifdef CONFIG_CPU_PXA300 +extern void zylonite_pxa300_init(void); +#else +static inline void zylonite_pxa300_init(void) +{ + if (cpu_is_pxa300() || cpu_is_pxa310()) + panic("%s: PXA300/PXA310 not supported\n", __FUNCTION__); +} +#endif + +#ifdef CONFIG_CPU_PXA320 +extern void zylonite_pxa320_init(void); +#else +static inline void zylonite_pxa320_init(void) +{ + if (cpu_is_pxa320()) + panic("%s: PXA320 not supported\n", __FUNCTION__); +} +#endif + +#endif /* __ASM_ARCH_ZYLONITE_H */ -- cgit v1.2.2 From 36d8b17b4364915615aff312ba20a1b90e22b963 Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 1 Oct 2007 16:22:24 +0100 Subject: [ARM] pxa: Make cpu_is_pxaXXX dependent on configuration symbols Make the cpu_is_pxaXXX() macros define to zero when support for a particular CPU is disabled. This allows us to eliminate code for CPUs which aren't enabled. Signed-off-by: Russell King --- include/asm-arm/arch-pxa/hardware.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h index fc20d72d4844..89df077a7e24 100644 --- a/include/asm-arm/arch-pxa/hardware.h +++ b/include/asm-arm/arch-pxa/hardware.h @@ -62,6 +62,7 @@ #ifndef __ASSEMBLY__ +#ifdef CONFIG_PXA25x #define __cpu_is_pxa21x(id) \ ({ \ unsigned int _id = (id) >> 4 & 0xf3f; \ @@ -73,30 +74,50 @@ unsigned int _id = (id) >> 4 & 0xfff; \ _id == 0x2d0 || _id == 0x290; \ }) +#else +#define __cpu_is_pxa21x(id) (0) +#define __cpu_is_pxa25x(id) (0) +#endif +#ifdef CONFIG_PXA27x #define __cpu_is_pxa27x(id) \ ({ \ unsigned int _id = (id) >> 4 & 0xfff; \ _id == 0x411; \ }) +#else +#define __cpu_is_pxa27x(id) (0) +#endif +#ifdef CONFIG_CPU_PXA300 #define __cpu_is_pxa300(id) \ ({ \ unsigned int _id = (id) >> 4 & 0xfff; \ _id == 0x688; \ }) +#else +#define __cpu_is_pxa300(id) (0) +#endif +#ifdef CONFIG_CPU_PXA310 #define __cpu_is_pxa310(id) \ ({ \ unsigned int _id = (id) >> 4 & 0xfff; \ _id == 0x689; \ }) +#else +#define __cpu_is_pxa310(id) (0) +#endif +#ifdef CONFIG_CPU_PXA320 #define __cpu_is_pxa320(id) \ ({ \ unsigned int _id = (id) >> 4 & 0xfff; \ _id == 0x603 || _id == 0x682; \ }) +#else +#define __cpu_is_pxa320(id) (0) +#endif #define cpu_is_pxa21x() \ ({ \ -- cgit v1.2.2 From 3e0cc7ee045fb53e8215fed7442455c0cee0ee93 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 2 Oct 2007 14:28:01 +0100 Subject: [ARM] pxa: Avoid pxa_gpio_mode() in gpio_direction_{in,out}put() pxa_gpio_mode() is a universal call that fiddles with the GAFR (gpio alternate function register.) GAFR does not exist on PXA3 CPUs, but instead the alternate functions are controlled via the MFP support code. Platforms are expected to configure the MFP according to their needs in their platform support code rather than drivers. We extend this idea to the GAFR, and make the gpio_direction_*() functions purely operate on the GPIO level. This means platform support code is entirely responsible for configuring the GPIOs alternate functions on all PXA CPU types. Signed-off-by: Russell King --- include/asm-arm/arch-pxa/gpio.h | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/gpio.h b/include/asm-arm/arch-pxa/gpio.h index 9e99241f3edf..9dbc2dc794f7 100644 --- a/include/asm-arm/arch-pxa/gpio.h +++ b/include/asm-arm/arch-pxa/gpio.h @@ -38,16 +38,8 @@ static inline void gpio_free(unsigned gpio) return; } -static inline int gpio_direction_input(unsigned gpio) -{ - return pxa_gpio_mode(gpio | GPIO_IN); -} - -static inline int gpio_direction_output(unsigned gpio, int value) -{ - return pxa_gpio_mode(gpio | GPIO_OUT | - (value ? GPIO_DFLT_HIGH : GPIO_DFLT_LOW)); -} +extern int gpio_direction_input(unsigned gpio); +extern int gpio_direction_output(unsigned gpio, int value); static inline int __gpio_get_value(unsigned gpio) { -- cgit v1.2.2 From 3696a8a426f8caebd97463e9b5cf9f06c1c36759 Mon Sep 17 00:00:00 2001 From: Mike Rapoport Date: Sun, 23 Sep 2007 15:59:26 +0100 Subject: [ARM] 4576/1: CM-X270 machine support This patch provides core support for CM-X270 platform. Signed-off-by: Mike Rapoport Signed-off-by: Russell King --- include/asm-arm/arch-pxa/cm-x270.h | 50 +++++++++++++++++++++++++++++++++++++ include/asm-arm/arch-pxa/dma.h | 4 +++ include/asm-arm/arch-pxa/hardware.h | 6 +++++ include/asm-arm/arch-pxa/irqs.h | 21 ++++++++++++++++ include/asm-arm/arch-pxa/memory.h | 10 ++++++++ 5 files changed, 91 insertions(+) create mode 100644 include/asm-arm/arch-pxa/cm-x270.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/cm-x270.h b/include/asm-arm/arch-pxa/cm-x270.h new file mode 100644 index 000000000000..f8fac9e18009 --- /dev/null +++ b/include/asm-arm/arch-pxa/cm-x270.h @@ -0,0 +1,50 @@ +/* + * linux/include/asm/arch-pxa/cm-x270.h + * + * Copyright Compulab Ltd., 2003, 2007 + * Mike Rapoport + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + + +/* CM-x270 device physical addresses */ +#define CMX270_CS1_PHYS (PXA_CS1_PHYS) +#define MARATHON_PHYS (PXA_CS2_PHYS) +#define CMX270_IDE104_PHYS (PXA_CS3_PHYS) +#define CMX270_IT8152_PHYS (PXA_CS4_PHYS) + +/* Statically mapped regions */ +#define CMX270_VIRT_BASE (0xe8000000) +#define CMX270_IT8152_VIRT (CMX270_VIRT_BASE) +#define CMX270_IDE104_VIRT (CMX270_IT8152_VIRT + SZ_64M) + +/* GPIO related definitions */ +#define GPIO_IT8152_IRQ (22) + +#define IRQ_GPIO_IT8152_IRQ IRQ_GPIO(GPIO_IT8152_IRQ) +#define PME_IRQ IRQ_GPIO(0) +#define CMX270_IDE_IRQ IRQ_GPIO(100) +#define CMX270_GPIRQ1 IRQ_GPIO(101) +#define CMX270_TOUCHIRQ IRQ_GPIO(96) +#define CMX270_ETHIRQ IRQ_GPIO(10) +#define CMX270_GFXIRQ IRQ_GPIO(95) +#define CMX270_NANDIRQ IRQ_GPIO(89) +#define CMX270_MMC_IRQ IRQ_GPIO(83) + +/* PCMCIA related definitions */ +#define PCC_DETECT(x) (GPLR(84 - (x)) & GPIO_bit(84 - (x))) +#define PCC_READY(x) (GPLR(82 - (x)) & GPIO_bit(82 - (x))) + +#define PCMCIA_S0_CD_VALID IRQ_GPIO(84) +#define PCMCIA_S0_CD_VALID_EDGE GPIO_BOTH_EDGES + +#define PCMCIA_S1_CD_VALID IRQ_GPIO(83) +#define PCMCIA_S1_CD_VALID_EDGE GPIO_BOTH_EDGES + +#define PCMCIA_S0_RDYINT IRQ_GPIO(82) +#define PCMCIA_S1_RDYINT IRQ_GPIO(81) + +#define PCMCIA_RESET_GPIO 53 diff --git a/include/asm-arm/arch-pxa/dma.h b/include/asm-arm/arch-pxa/dma.h index 3280ee2ddfa5..dbe110ee2666 100644 --- a/include/asm-arm/arch-pxa/dma.h +++ b/include/asm-arm/arch-pxa/dma.h @@ -30,6 +30,10 @@ typedef enum { DMA_PRIO_LOW = 2 } pxa_dma_prio; +#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) +#define HAVE_ARCH_PCI_SET_DMA_MASK 1 +#endif + /* * DMA registration */ diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h index 89df077a7e24..ab2d963e742a 100644 --- a/include/asm-arm/arch-pxa/hardware.h +++ b/include/asm-arm/arch-pxa/hardware.h @@ -215,4 +215,10 @@ extern unsigned int get_memclk_frequency_10khz(void); #endif +#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) +#define PCIBIOS_MIN_IO 0 +#define PCIBIOS_MIN_MEM 0 +#define pcibios_assign_all_busses() 1 +#endif + #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h index 1bcc7632b46c..6238dbf7a236 100644 --- a/include/asm-arm/arch-pxa/irqs.h +++ b/include/asm-arm/arch-pxa/irqs.h @@ -210,3 +210,24 @@ #define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1) #define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2) #define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3) + +/* ITE8152 irqs */ +/* add IT8152 IRQs beyond BOARD_END */ +#ifdef CONFIG_PCI_HOST_ITE8152 +#define IT8152_IRQ(x) (IRQ_GPIO(IRQ_BOARD_END) + 1 + (x)) + +/* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */ +#define IT8152_LD_IRQ_COUNT 9 +#define IT8152_LP_IRQ_COUNT 16 +#define IT8152_PD_IRQ_COUNT 15 + +/* Priorities: */ +#define IT8152_PD_IRQ(i) IT8152_IRQ(i) +#define IT8152_LP_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT) +#define IT8152_LD_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT + IT8152_LP_IRQ_COUNT) + +#define IT8152_LAST_IRQ IT8152_LD_IRQ(IT8152_LD_IRQ_COUNT - 1) + +#undef NR_IRQS +#define NR_IRQS (IT8152_LAST_IRQ+1) +#endif diff --git a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h index e17f9881faf0..bee81d66c184 100644 --- a/include/asm-arm/arch-pxa/memory.h +++ b/include/asm-arm/arch-pxa/memory.h @@ -39,4 +39,14 @@ */ #define NODE_MEM_SIZE_BITS 26 +#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) +void cmx270_pci_adjust_zones(int node, unsigned long *size, + unsigned long *holes); + +#define arch_adjust_zones(node, size, holes) \ + cmx270_pci_adjust_zones(node, size, holes) + +#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1) +#endif + #endif -- cgit v1.2.2 From a8fc0789558d81d2898b87473404b71b7f7cd0fc Mon Sep 17 00:00:00 2001 From: Mike Rapoport Date: Sun, 23 Sep 2007 15:59:52 +0100 Subject: [ARM] 4577/1: ITE 8152 PCI bridge support This patch provides driver for ITE 8152 PCI bridge. Signed-off-by: Mike Rapoport Signed-off-by: Russell King --- include/asm-arm/hardware/it8152.h | 99 +++++++++++++++++++++++++++++++++++++++ include/asm-arm/pci.h | 7 +++ 2 files changed, 106 insertions(+) create mode 100644 include/asm-arm/hardware/it8152.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/hardware/it8152.h b/include/asm-arm/hardware/it8152.h new file mode 100644 index 000000000000..aaebb61aca48 --- /dev/null +++ b/include/asm-arm/hardware/it8152.h @@ -0,0 +1,99 @@ +/* + * linux/include/arm/hardware/it8152.h + * + * Copyright Compulab Ltd., 2006,2007 + * Mike Rapoport + * + * ITE 8152 companion chip register definitions + */ + +#ifndef __ASM_HARDWARE_IT8152_H +#define __ASM_HARDWARE_IT8152_H +extern unsigned long it8152_base_address; + +#define IT8152_IO_BASE (it8152_base_address + 0x03e00000) +#define IT8152_CFGREG_BASE (it8152_base_address + 0x03f00000) + +#define __REG_IT8152(x) (it8152_base_address + (x)) + +#define IT8152_PCI_CFG_ADDR __REG_IT8152(0x3f00800) +#define IT8152_PCI_CFG_DATA __REG_IT8152(0x3f00804) + +#define IT8152_INTC_LDCNIRR __REG_IT8152(0x3f00300) +#define IT8152_INTC_LDPNIRR __REG_IT8152(0x3f00304) +#define IT8152_INTC_LDCNIMR __REG_IT8152(0x3f00308) +#define IT8152_INTC_LDPNIMR __REG_IT8152(0x3f0030C) +#define IT8152_INTC_LDNITR __REG_IT8152(0x3f00310) +#define IT8152_INTC_LDNIAR __REG_IT8152(0x3f00314) +#define IT8152_INTC_LPCNIRR __REG_IT8152(0x3f00320) +#define IT8152_INTC_LPPNIRR __REG_IT8152(0x3f00324) +#define IT8152_INTC_LPCNIMR __REG_IT8152(0x3f00328) +#define IT8152_INTC_LPPNIMR __REG_IT8152(0x3f0032C) +#define IT8152_INTC_LPNITR __REG_IT8152(0x3f00330) +#define IT8152_INTC_LPNIAR __REG_IT8152(0x3f00334) +#define IT8152_INTC_PDCNIRR __REG_IT8152(0x3f00340) +#define IT8152_INTC_PDPNIRR __REG_IT8152(0x3f00344) +#define IT8152_INTC_PDCNIMR __REG_IT8152(0x3f00348) +#define IT8152_INTC_PDPNIMR __REG_IT8152(0x3f0034C) +#define IT8152_INTC_PDNITR __REG_IT8152(0x3f00350) +#define IT8152_INTC_PDNIAR __REG_IT8152(0x3f00354) +#define IT8152_INTC_INTC_TYPER __REG_IT8152(0x3f003FC) + +#define IT8152_GPIO_GPDR __REG_IT8152(0x3f00500) + +/* + Interrup contoler per register summary: + --------------------------------------- + LCDNIRR: + IT8152_LD_IRQ(8) PCICLK stop + IT8152_LD_IRQ(7) MCLK ready + IT8152_LD_IRQ(6) s/w + IT8152_LD_IRQ(5) UART + IT8152_LD_IRQ(4) GPIO + IT8152_LD_IRQ(3) TIMER 4 + IT8152_LD_IRQ(2) TIMER 3 + IT8152_LD_IRQ(1) TIMER 2 + IT8152_LD_IRQ(0) TIMER 1 + + LPCNIRR: + IT8152_LP_IRQ(x) serial IRQ x + + PCIDNIRR: + IT8152_PD_IRQ(14) PCISERR + IT8152_PD_IRQ(13) CPU/PCI bridge target abort (h2pTADR) + IT8152_PD_IRQ(12) CPU/PCI bridge master abort (h2pMADR) + IT8152_PD_IRQ(11) PCI INTD + IT8152_PD_IRQ(10) PCI INTC + IT8152_PD_IRQ(9) PCI INTB + IT8152_PD_IRQ(8) PCI INTA + IT8152_PD_IRQ(7) serial INTD + IT8152_PD_IRQ(6) serial INTC + IT8152_PD_IRQ(5) serial INTB + IT8152_PD_IRQ(4) serial INTA + IT8152_PD_IRQ(3) serial IRQ IOCHK (IOCHKR) + IT8152_PD_IRQ(2) chaining DMA (CDMAR) + IT8152_PD_IRQ(1) USB (USBR) + IT8152_PD_IRQ(0) Audio controller (ACR) + */ +/* frequently used interrupts */ +#define IT8152_PCISERR IT8152_PD_IRQ(14) +#define IT8152_H2PTADR IT8152_PD_IRQ(13) +#define IT8152_H2PMAR IT8152_PD_IRQ(12) +#define IT8152_PCI_INTD IT8152_PD_IRQ(11) +#define IT8152_PCI_INTC IT8152_PD_IRQ(10) +#define IT8152_PCI_INTB IT8152_PD_IRQ(9) +#define IT8152_PCI_INTA IT8152_PD_IRQ(8) +#define IT8152_CDMA_INT IT8152_PD_IRQ(2) +#define IT8152_USB_INT IT8152_PD_IRQ(1) +#define IT8152_AUDIO_INT IT8152_PD_IRQ(0) + +struct pci_dev; +struct pci_sys_data; + +extern void it8152_irq_demux(unsigned int irq, struct irq_desc *desc); +extern void it8152_init_irq(void); +extern int it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin); +extern int it8152_pci_setup(int nr, struct pci_sys_data *sys); +extern struct pci_bus *it8152_pci_scan_bus(int nr, struct pci_sys_data *sys); + +#endif /* __ASM_HARDWARE_IT8152_H */ diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h index ed3f898191f4..75feb1574a69 100644 --- a/include/asm-arm/pci.h +++ b/include/asm-arm/pci.h @@ -8,10 +8,17 @@ #define pcibios_scan_all_fns(a, b) 0 +#ifdef CONFIG_PCI_HOST_ITE8152 +/* ITE bridge requires setting latency timer to avoid early bus access + termination by PIC bus mater devices +*/ +extern void pcibios_set_master(struct pci_dev *dev); +#else static inline void pcibios_set_master(struct pci_dev *dev) { /* No special bus mastering setup handling */ } +#endif static inline void pcibios_penalize_isa_irq(int irq, int active) { -- cgit v1.2.2