From a977dbe8445b8a81d6127c4aa9112a2c29a1a008 Mon Sep 17 00:00:00 2001 From: Matt Carlson Date: Mon, 12 Apr 2010 06:58:26 +0000 Subject: tg3: Reduce 57765 core clock when link at 10Mbps This patch reduces the core clock to 6.25MHz when operating at 10Mbps link speed. This is needed to prevent a bug that will ultimately cause transmits to cease. Signed-off-by: Matt Carlson Reviewed-by: Michael Chan Signed-off-by: David S. Miller --- drivers/net/tg3.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers') diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index a0ab89eb8bcc..3e893231fef3 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -7654,6 +7654,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ); tw32(GRC_MODE, grc_mode); + + val = tr32(TG3_CPMU_LSPD_10MB_CLK); + val &= ~CPMU_LSPD_10MB_MACCLK_MASK; + val |= CPMU_LSPD_10MB_MACCLK_6_25; + tw32(TG3_CPMU_LSPD_10MB_CLK, val); } /* This works around an issue with Athlon chipsets on -- cgit v1.2.2