From c2fbd061a28530dd24b2593bffa2b6a5b15eb3ed Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Thu, 16 Oct 2014 16:01:51 +0300 Subject: OMAPDSS: HDMI: split PLL enable & config At the moment we have one function, hdmi_pll_enable, which enables the PLL and writes the PLL configuration to registers. To make the HDMI PLL ahere to the DSS PLL API, split the hdmi_pll_enable into two parts: hdmi_pll_enable which enables the PLL HW, and hdmi_pll_set_config which writes the config. Signed-off-by: Tomi Valkeinen --- drivers/video/fbdev/omap2/dss/hdmi4.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'drivers/video/fbdev/omap2/dss/hdmi4.c') diff --git a/drivers/video/fbdev/omap2/dss/hdmi4.c b/drivers/video/fbdev/omap2/dss/hdmi4.c index 2094b6eae99e..98aa910241b8 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi4.c +++ b/drivers/video/fbdev/omap2/dss/hdmi4.c @@ -196,13 +196,18 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev) hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), p->pixelclock); - /* config the PLL and PHY hdmi_set_pll_pwrfirst */ r = hdmi_pll_enable(&hdmi.pll); if (r) { - DSSDBG("Failed to lock PLL\n"); + DSSERR("Failed to enable PLL\n"); goto err_pll_enable; } + r = hdmi_pll_set_config(&hdmi.pll); + if (r) { + DSSERR("Failed to configure PLL\n"); + goto err_pll_cfg; + } + r = hdmi_phy_configure(&hdmi.phy, hdmi.pll.info.clkdco, hdmi.pll.info.clkout); if (r) { @@ -241,6 +246,7 @@ err_vid_enable: err_phy_cfg: hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); err_phy_pwr: +err_pll_cfg: hdmi_pll_disable(&hdmi.pll); err_pll_enable: hdmi_power_off_core(dssdev); -- cgit v1.2.2