From f35235a315a167e38e8e5bc9e476dcd7c932612c Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 27 Aug 2011 00:37:38 +0100 Subject: ARM: pm: some ARMv7 requires a dsb in resume to ensure correctness Add a dsb after the isb to ensure that the previous writes to the CP15 registers take effect before we enable the MMU. Signed-off-by: Russell King --- arch/arm/mm/proc-v7.S | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index dec72ee9f7af..a773f4e2869c 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -255,6 +255,7 @@ ENTRY(cpu_v7_do_resume) mcr p15, 0, r4, c10, c2, 0 @ write PRRR mcr p15, 0, r5, c10, c2, 1 @ write NMRR isb + dsb mov r0, r9 @ control register mov r2, r7, lsr #14 @ get TTB0 base mov r2, r2, lsl #14 -- cgit v1.2.2