From 999ba417cc1a43881126d08876d5d7e653113ae3 Mon Sep 17 00:00:00 2001 From: Joerg Roedel Date: Thu, 3 Jul 2008 19:35:08 +0200 Subject: x86, AMD IOMMU: flush domain TLB when there is more than one page to flush This patch changes the domain TLB flushing behavior of the driver. When there is more than one page to flush it flushes the whole domain TLB instead of every single page. So we send only a single command to the IOMMU in every case which is faster to execute. Signed-off-by: Joerg Roedel Cc: iommu@lists.linux-foundation.org Cc: bhavna.sarathy@amd.com Cc: robert.richter@amd.com Cc: Joerg Roedel Signed-off-by: Ingo Molnar --- arch/x86/kernel/amd_iommu.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'arch/x86/kernel/amd_iommu.c') diff --git a/arch/x86/kernel/amd_iommu.c b/arch/x86/kernel/amd_iommu.c index 329b2c3f2fed..f2766d84c7a0 100644 --- a/arch/x86/kernel/amd_iommu.c +++ b/arch/x86/kernel/amd_iommu.c @@ -140,16 +140,22 @@ static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, u64 address, size_t size) { - int i; + int s = 0; unsigned pages = to_pages(address, size); address &= PAGE_MASK; - for (i = 0; i < pages; ++i) { - iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 0); - address += PAGE_SIZE; + if (pages > 1) { + /* + * If we have to flush more than one page, flush all + * TLB entries for this domain + */ + address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; + s = 1; } + iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); + return 0; } -- cgit v1.2.2