From a88b5ba8bd8ac18aad65ee6c6a254e2e74876db3 Mon Sep 17 00:00:00 2001 From: Sam Ravnborg Date: Wed, 3 Dec 2008 03:11:52 -0800 Subject: sparc,sparc64: unify kernel/ o Move all files from sparc64/kernel/ to sparc/kernel - rename as appropriate o Update sparc/Makefile to the changes o Update sparc/kernel/Makefile to include the sparc64 files NOTE: This commit changes link order on sparc64! Link order had to change for either of sparc32 and sparc64. And assuming sparc64 see more testing than sparc32 change link order on sparc64 where issues will be caught faster. Signed-off-by: Sam Ravnborg Signed-off-by: David S. Miller --- arch/sparc64/kernel/itlb_miss.S | 39 --------------------------------------- 1 file changed, 39 deletions(-) delete mode 100644 arch/sparc64/kernel/itlb_miss.S (limited to 'arch/sparc64/kernel/itlb_miss.S') diff --git a/arch/sparc64/kernel/itlb_miss.S b/arch/sparc64/kernel/itlb_miss.S deleted file mode 100644 index 5a8377b54955..000000000000 --- a/arch/sparc64/kernel/itlb_miss.S +++ /dev/null @@ -1,39 +0,0 @@ -/* ITLB ** ICACHE line 1: Context 0 check and TSB load */ - ldxa [%g0] ASI_IMMU_TSB_8KB_PTR, %g1 ! Get TSB 8K pointer - ldxa [%g0] ASI_IMMU, %g6 ! Get TAG TARGET - srlx %g6, 48, %g5 ! Get context - sllx %g6, 22, %g6 ! Zero out context - brz,pn %g5, kvmap_itlb ! Context 0 processing - srlx %g6, 22, %g6 ! Delay slot - TSB_LOAD_QUAD(%g1, %g4) ! Load TSB entry - cmp %g4, %g6 ! Compare TAG - -/* ITLB ** ICACHE line 2: TSB compare and TLB load */ - bne,pn %xcc, tsb_miss_itlb ! Miss - mov FAULT_CODE_ITLB, %g3 - sethi %hi(_PAGE_EXEC_4U), %g4 - andcc %g5, %g4, %g0 ! Executable? - be,pn %xcc, tsb_do_fault - nop ! Delay slot, fill me - stxa %g5, [%g0] ASI_ITLB_DATA_IN ! Load TLB - retry ! Trap done - -/* ITLB ** ICACHE line 3: */ - nop - nop - nop - nop - nop - nop - nop - nop - -/* ITLB ** ICACHE line 4: */ - nop - nop - nop - nop - nop - nop - nop - nop -- cgit v1.2.2