From 2a7e2990340a1c42321d79dc99755683ea5a1026 Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Wed, 21 Sep 2005 18:50:51 -0700 Subject: [SPARC64]: Move kernel TLB miss handling into a seperate file. Signed-off-by: David S. Miller --- arch/sparc64/kernel/dtlb_base.S | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/sparc64/kernel/dtlb_base.S') diff --git a/arch/sparc64/kernel/dtlb_base.S b/arch/sparc64/kernel/dtlb_base.S index ded2fed23fcc..702d349c1e88 100644 --- a/arch/sparc64/kernel/dtlb_base.S +++ b/arch/sparc64/kernel/dtlb_base.S @@ -71,7 +71,7 @@ from_tl1_trap: rdpr %tl, %g5 ! For TL==3 test CREATE_VPTE_OFFSET1(%g4, %g6) ! Create VPTE offset - be,pn %xcc, 3f ! Yep, special processing + be,pn %xcc, kvmap ! Yep, special processing CREATE_VPTE_OFFSET2(%g4, %g6) ! Create VPTE offset cmp %g5, 4 ! Last trap level? be,pn %xcc, longpath ! Yep, cannot risk VPTE miss @@ -83,9 +83,9 @@ from_tl1_trap: nop ! Delay-slot 9: stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB retry ! Trap return -3: brlz,pt %g4, 9b ! Kernel virtual map? - xor %g2, %g4, %g5 ! Finish bit twiddles - ba,a,pt %xcc, kvmap ! Yep, go check for obp/vmalloc + nop + nop + nop /* DTLB ** ICACHE line 3: winfixups+real_faults */ longpath: -- cgit v1.2.2