From 46bc85872040ae7a98b983514bf79f68255b2643 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 29 Oct 2010 18:42:22 +0900 Subject: sh: mach-microdev: SuperIO-relative ioport mapping. The microdev only has to contend with silly PIO mangling on anything within the SuperIO range. As each of the SuperIO modules is already speciail cased, we just shift that logic over to the ioport map. With microdev PCI never being merged (and being fudamentally broken in hardware), and the ethernet chip only doing 16-bit accesses already, there's no need to maintain any of the extra special casing. Kill it all off. Signed-off-by: Paul Mundt --- arch/sh/include/mach-common/mach/microdev.h | 9 --------- 1 file changed, 9 deletions(-) (limited to 'arch/sh/include') diff --git a/arch/sh/include/mach-common/mach/microdev.h b/arch/sh/include/mach-common/mach/microdev.h index 1aed15856e11..dcb05fa8c164 100644 --- a/arch/sh/include/mach-common/mach/microdev.h +++ b/arch/sh/include/mach-common/mach/microdev.h @@ -68,13 +68,4 @@ extern void microdev_print_fpga_intc_status(void); #define __IO_PREFIX microdev #include -#if defined(CONFIG_PCI) -unsigned char microdev_pci_inb(unsigned long port); -unsigned short microdev_pci_inw(unsigned long port); -unsigned long microdev_pci_inl(unsigned long port); -void microdev_pci_outb(unsigned char data, unsigned long port); -void microdev_pci_outw(unsigned short data, unsigned long port); -void microdev_pci_outl(unsigned long data, unsigned long port); -#endif - #endif /* __ASM_SH_MICRODEV_H */ -- cgit v1.2.2 From 39c11984a4f36bd1ce7f90f7506824955f0f4863 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 29 Oct 2010 18:59:58 +0900 Subject: sh: mach-snapgear: Rip out superfluous PIO routines. None of these PIO routines do anything other than basic error checking, get rid of them and use the generic fallbacks. Signed-off-by: Paul Mundt --- arch/sh/include/mach-common/mach/snapgear.h | 22 ---------------------- 1 file changed, 22 deletions(-) (limited to 'arch/sh/include') diff --git a/arch/sh/include/mach-common/mach/snapgear.h b/arch/sh/include/mach-common/mach/snapgear.h index 042d95f51c4d..3653b9a4bacc 100644 --- a/arch/sh/include/mach-common/mach/snapgear.h +++ b/arch/sh/include/mach-common/mach/snapgear.h @@ -12,30 +12,9 @@ #ifndef _ASM_SH_IO_SNAPGEAR_H #define _ASM_SH_IO_SNAPGEAR_H -#if defined(CONFIG_CPU_SH4) -/* - * The external interrupt lines, these take up ints 0 - 15 inclusive - * depending on the priority for the interrupt. In fact the priority - * is the interrupt :-) - */ - -#define IRL0_IRQ 2 -#define IRL0_PRIORITY 13 - -#define IRL1_IRQ 5 -#define IRL1_PRIORITY 10 - -#define IRL2_IRQ 8 -#define IRL2_PRIORITY 7 - -#define IRL3_IRQ 11 -#define IRL3_PRIORITY 4 -#endif - #define __IO_PREFIX snapgear #include -#ifdef CONFIG_SH_SECUREEDGE5410 /* * We need to remember what was written to the ioport as some bits * are shared with other functions and you cannot read back what was @@ -66,6 +45,5 @@ extern unsigned short secureedge5410_ioport; ((secureedge5410_ioport & ~(mask)) | ((val) & (mask))))) #define SECUREEDGE_READ_IOPORT() \ ((*SECUREEDGE_IOPORT_ADDR&0x0817) | (secureedge5410_ioport&~0x0817)) -#endif #endif /* _ASM_SH_IO_SNAPGEAR_H */ -- cgit v1.2.2 From f6eec8d66400714e47add3d8341688a1e86c5de9 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 29 Oct 2010 19:06:53 +0900 Subject: sh: mach-snapgear: Kill off machtype, consolidate board def. Only the secureedge5410 was ever supported by this code, so make the board specification explicit rather than perpetuating a mach group. Signed-off-by: Paul Mundt --- arch/sh/include/mach-common/mach/secureedge5410.h | 49 +++++++++++++++++++++++ arch/sh/include/mach-common/mach/snapgear.h | 49 ----------------------- 2 files changed, 49 insertions(+), 49 deletions(-) create mode 100644 arch/sh/include/mach-common/mach/secureedge5410.h delete mode 100644 arch/sh/include/mach-common/mach/snapgear.h (limited to 'arch/sh/include') diff --git a/arch/sh/include/mach-common/mach/secureedge5410.h b/arch/sh/include/mach-common/mach/secureedge5410.h new file mode 100644 index 000000000000..3653b9a4bacc --- /dev/null +++ b/arch/sh/include/mach-common/mach/secureedge5410.h @@ -0,0 +1,49 @@ +/* + * include/asm-sh/snapgear.h + * + * Modified version of io_se.h for the snapgear-specific functions. + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * IO functions for a SnapGear + */ + +#ifndef _ASM_SH_IO_SNAPGEAR_H +#define _ASM_SH_IO_SNAPGEAR_H + +#define __IO_PREFIX snapgear +#include + +/* + * We need to remember what was written to the ioport as some bits + * are shared with other functions and you cannot read back what was + * written :-| + * + * Bit Read Write + * ----------------------------------------------- + * D0 DCD on ttySC1 power + * D1 Reset Switch heatbeat + * D2 ttySC0 CTS (7100) LAN + * D3 - WAN + * D4 ttySC0 DCD (7100) CONSOLE + * D5 - ONLINE + * D6 - VPN + * D7 - DTR on ttySC1 + * D8 - ttySC0 RTS (7100) + * D9 - ttySC0 DTR (7100) + * D10 - RTC SCLK + * D11 RTC DATA RTC DATA + * D12 - RTS RESET + */ + +#define SECUREEDGE_IOPORT_ADDR ((volatile short *) 0xb0000000) +extern unsigned short secureedge5410_ioport; + +#define SECUREEDGE_WRITE_IOPORT(val, mask) (*SECUREEDGE_IOPORT_ADDR = \ + (secureedge5410_ioport = \ + ((secureedge5410_ioport & ~(mask)) | ((val) & (mask))))) +#define SECUREEDGE_READ_IOPORT() \ + ((*SECUREEDGE_IOPORT_ADDR&0x0817) | (secureedge5410_ioport&~0x0817)) + +#endif /* _ASM_SH_IO_SNAPGEAR_H */ diff --git a/arch/sh/include/mach-common/mach/snapgear.h b/arch/sh/include/mach-common/mach/snapgear.h deleted file mode 100644 index 3653b9a4bacc..000000000000 --- a/arch/sh/include/mach-common/mach/snapgear.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * include/asm-sh/snapgear.h - * - * Modified version of io_se.h for the snapgear-specific functions. - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - * - * IO functions for a SnapGear - */ - -#ifndef _ASM_SH_IO_SNAPGEAR_H -#define _ASM_SH_IO_SNAPGEAR_H - -#define __IO_PREFIX snapgear -#include - -/* - * We need to remember what was written to the ioport as some bits - * are shared with other functions and you cannot read back what was - * written :-| - * - * Bit Read Write - * ----------------------------------------------- - * D0 DCD on ttySC1 power - * D1 Reset Switch heatbeat - * D2 ttySC0 CTS (7100) LAN - * D3 - WAN - * D4 ttySC0 DCD (7100) CONSOLE - * D5 - ONLINE - * D6 - VPN - * D7 - DTR on ttySC1 - * D8 - ttySC0 RTS (7100) - * D9 - ttySC0 DTR (7100) - * D10 - RTC SCLK - * D11 RTC DATA RTC DATA - * D12 - RTS RESET - */ - -#define SECUREEDGE_IOPORT_ADDR ((volatile short *) 0xb0000000) -extern unsigned short secureedge5410_ioport; - -#define SECUREEDGE_WRITE_IOPORT(val, mask) (*SECUREEDGE_IOPORT_ADDR = \ - (secureedge5410_ioport = \ - ((secureedge5410_ioport & ~(mask)) | ((val) & (mask))))) -#define SECUREEDGE_READ_IOPORT() \ - ((*SECUREEDGE_IOPORT_ADDR&0x0817) | (secureedge5410_ioport&~0x0817)) - -#endif /* _ASM_SH_IO_SNAPGEAR_H */ -- cgit v1.2.2 From 2504075d383fcefd746dac42a0cd1c3bdc006bd1 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 29 Oct 2010 19:11:56 +0900 Subject: sh: mach-systemh: Kill off dead board. This code has been untouched since it was merged many years ago, and has severely bitrotted since, suggesting that the board has no real users left. Notice of intent to remove has been sent out over the last few years, with no takers. Kill it off. Signed-off-by: Paul Mundt --- arch/sh/include/mach-common/mach/systemh7751.h | 71 -------------------------- 1 file changed, 71 deletions(-) delete mode 100644 arch/sh/include/mach-common/mach/systemh7751.h (limited to 'arch/sh/include') diff --git a/arch/sh/include/mach-common/mach/systemh7751.h b/arch/sh/include/mach-common/mach/systemh7751.h deleted file mode 100644 index 4161122c84ef..000000000000 --- a/arch/sh/include/mach-common/mach/systemh7751.h +++ /dev/null @@ -1,71 +0,0 @@ -#ifndef __ASM_SH_SYSTEMH_7751SYSTEMH_H -#define __ASM_SH_SYSTEMH_7751SYSTEMH_H - -/* - * linux/include/asm-sh/systemh/7751systemh.h - * - * Copyright (C) 2000 Kazumoto Kojima - * - * Hitachi SystemH support - - * Modified for 7751 SystemH by - * Jonathan Short, 2002. - */ - -/* Box specific addresses. */ - -#define PA_ROM 0x00000000 /* EPROM */ -#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ -#define PA_FROM 0x01000000 /* EPROM */ -#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */ -#define PA_EXT1 0x04000000 -#define PA_EXT1_SIZE 0x04000000 -#define PA_EXT2 0x08000000 -#define PA_EXT2_SIZE 0x04000000 -#define PA_SDRAM 0x0c000000 -#define PA_SDRAM_SIZE 0x04000000 - -#define PA_EXT4 0x12000000 -#define PA_EXT4_SIZE 0x02000000 -#define PA_EXT5 0x14000000 -#define PA_EXT5_SIZE 0x04000000 -#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */ - -#define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */ -#define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */ -#define PA_LED 0xba000000 /* LED */ -#define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */ - -#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */ -#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */ -#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */ -#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */ -#define MRSHPC_MODE (PA_MRSHPC + 4) -#define MRSHPC_OPTION (PA_MRSHPC + 6) -#define MRSHPC_CSR (PA_MRSHPC + 8) -#define MRSHPC_ISR (PA_MRSHPC + 10) -#define MRSHPC_ICR (PA_MRSHPC + 12) -#define MRSHPC_CPWCR (PA_MRSHPC + 14) -#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) -#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) -#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) -#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) -#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) -#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) -#define MRSHPC_CDCR (PA_MRSHPC + 28) -#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) - -#define BCR_ILCRA (PA_BCR + 0) -#define BCR_ILCRB (PA_BCR + 2) -#define BCR_ILCRC (PA_BCR + 4) -#define BCR_ILCRD (PA_BCR + 6) -#define BCR_ILCRE (PA_BCR + 8) -#define BCR_ILCRF (PA_BCR + 10) -#define BCR_ILCRG (PA_BCR + 12) - -#define IRQ_79C973 13 - -#define __IO_PREFIX sh7751systemh -#include - -#endif /* __ASM_SH_SYSTEMH_7751SYSTEMH_H */ -- cgit v1.2.2 From c819cc732267d6e46833a8d98bd7677b3d12d7d1 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 29 Oct 2010 19:38:19 +0900 Subject: sh: mach-edosk7705: Kill off machtype, consolidate board def. Trivial shuffling and tidying. Signed-off-by: Paul Mundt --- arch/sh/include/mach-common/mach/edosk7705.h | 7 ------- 1 file changed, 7 deletions(-) delete mode 100644 arch/sh/include/mach-common/mach/edosk7705.h (limited to 'arch/sh/include') diff --git a/arch/sh/include/mach-common/mach/edosk7705.h b/arch/sh/include/mach-common/mach/edosk7705.h deleted file mode 100644 index efc43b323466..000000000000 --- a/arch/sh/include/mach-common/mach/edosk7705.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __ASM_SH_EDOSK7705_H -#define __ASM_SH_EDOSK7705_H - -#define __IO_PREFIX sh_edosk7705 -#include - -#endif /* __ASM_SH_EDOSK7705_H */ -- cgit v1.2.2 From e2fcf74f3d3dabe8591732cd37869a0cc88ed7a5 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 4 Nov 2010 12:32:24 +0900 Subject: sh: nommu: use 32-bit phys mode. The nommu code has regressed somewhat in that 29BIT gets set for the SH-2/2A configs regardless of the fact that they are really 32BIT sans MMU or PMB. This does a bit of tidying to get nommu properly selecting 32BIT as it was before. Signed-off-by: Paul Mundt --- arch/sh/include/asm/addrspace.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/sh/include') diff --git a/arch/sh/include/asm/addrspace.h b/arch/sh/include/asm/addrspace.h index 446b3831c214..3d1ae2bfaa6f 100644 --- a/arch/sh/include/asm/addrspace.h +++ b/arch/sh/include/asm/addrspace.h @@ -44,10 +44,10 @@ /* * These will never work in 32-bit, don't even bother. */ -#define P1SEGADDR(a) __futile_remapping_attempt -#define P2SEGADDR(a) __futile_remapping_attempt -#define P3SEGADDR(a) __futile_remapping_attempt -#define P4SEGADDR(a) __futile_remapping_attempt +#define P1SEGADDR(a) ({ (void)(a); BUG(); NULL; }) +#define P2SEGADDR(a) ({ (void)(a); BUG(); NULL; }) +#define P3SEGADDR(a) ({ (void)(a); BUG(); NULL; }) +#define P4SEGADDR(a) ({ (void)(a); BUG(); NULL; }) #endif #endif /* P1SEG */ -- cgit v1.2.2 From edc9a958fd31ef1d89f9eaee82b2a3882c8e34c9 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 4 Nov 2010 12:46:19 +0900 Subject: sh: nommu: Support building without an uncached mapping. Now that nommu selects 32BIT we run in to the situation where SH-2A supports an uncached identity mapping by way of the BSC, while the SH-2 does not. This provides stubs for the PC manglers and tidies up some of the system*.h mess in the process. Signed-off-by: Paul Mundt --- arch/sh/include/asm/system.h | 4 +--- arch/sh/include/asm/system_32.h | 36 ------------------------------------ arch/sh/include/asm/system_64.h | 3 --- arch/sh/include/asm/uncached.h | 40 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 41 insertions(+), 42 deletions(-) (limited to 'arch/sh/include') diff --git a/arch/sh/include/asm/system.h b/arch/sh/include/asm/system.h index 1f1af5afff03..10c8b1823a18 100644 --- a/arch/sh/include/asm/system.h +++ b/arch/sh/include/asm/system.h @@ -10,6 +10,7 @@ #include #include #include +#include #define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */ @@ -137,9 +138,6 @@ extern unsigned int instruction_size(unsigned int insn); #define instruction_size(insn) (4) #endif -extern unsigned long cached_to_uncached; -extern unsigned long uncached_size; - void per_cpu_trap_init(void); void default_idle(void); void cpu_idle_wait(void); diff --git a/arch/sh/include/asm/system_32.h b/arch/sh/include/asm/system_32.h index c941b2739405..a4ad1cd9bc4d 100644 --- a/arch/sh/include/asm/system_32.h +++ b/arch/sh/include/asm/system_32.h @@ -145,42 +145,6 @@ do { \ __restore_dsp(prev); \ } while (0) -/* - * Jump to uncached area. - * When handling TLB or caches, we need to do it from an uncached area. - */ -#define jump_to_uncached() \ -do { \ - unsigned long __dummy; \ - \ - __asm__ __volatile__( \ - "mova 1f, %0\n\t" \ - "add %1, %0\n\t" \ - "jmp @%0\n\t" \ - " nop\n\t" \ - ".balign 4\n" \ - "1:" \ - : "=&z" (__dummy) \ - : "r" (cached_to_uncached)); \ -} while (0) - -/* - * Back to cached area. - */ -#define back_to_cached() \ -do { \ - unsigned long __dummy; \ - ctrl_barrier(); \ - __asm__ __volatile__( \ - "mov.l 1f, %0\n\t" \ - "jmp @%0\n\t" \ - " nop\n\t" \ - ".balign 4\n" \ - "1: .long 2f\n" \ - "2:" \ - : "=&r" (__dummy)); \ -} while (0) - #ifdef CONFIG_CPU_HAS_SR_RB #define lookup_exception_vector() \ ({ \ diff --git a/arch/sh/include/asm/system_64.h b/arch/sh/include/asm/system_64.h index 36338646dfc8..8593bc8d1a4e 100644 --- a/arch/sh/include/asm/system_64.h +++ b/arch/sh/include/asm/system_64.h @@ -34,9 +34,6 @@ do { \ &next->thread); \ } while (0) -#define jump_to_uncached() do { } while (0) -#define back_to_cached() do { } while (0) - #define __icbi(addr) __asm__ __volatile__ ( "icbi %0, 0\n\t" : : "r" (addr)) #define __ocbp(addr) __asm__ __volatile__ ( "ocbp %0, 0\n\t" : : "r" (addr)) #define __ocbi(addr) __asm__ __volatile__ ( "ocbi %0, 0\n\t" : : "r" (addr)) diff --git a/arch/sh/include/asm/uncached.h b/arch/sh/include/asm/uncached.h index e3419f96626a..6f8816b79cf1 100644 --- a/arch/sh/include/asm/uncached.h +++ b/arch/sh/include/asm/uncached.h @@ -4,15 +4,55 @@ #include #ifdef CONFIG_UNCACHED_MAPPING +extern unsigned long cached_to_uncached; +extern unsigned long uncached_size; extern unsigned long uncached_start, uncached_end; extern int virt_addr_uncached(unsigned long kaddr); extern void uncached_init(void); extern void uncached_resize(unsigned long size); + +/* + * Jump to uncached area. + * When handling TLB or caches, we need to do it from an uncached area. + */ +#define jump_to_uncached() \ +do { \ + unsigned long __dummy; \ + \ + __asm__ __volatile__( \ + "mova 1f, %0\n\t" \ + "add %1, %0\n\t" \ + "jmp @%0\n\t" \ + " nop\n\t" \ + ".balign 4\n" \ + "1:" \ + : "=&z" (__dummy) \ + : "r" (cached_to_uncached)); \ +} while (0) + +/* + * Back to cached area. + */ +#define back_to_cached() \ +do { \ + unsigned long __dummy; \ + ctrl_barrier(); \ + __asm__ __volatile__( \ + "mov.l 1f, %0\n\t" \ + "jmp @%0\n\t" \ + " nop\n\t" \ + ".balign 4\n" \ + "1: .long 2f\n" \ + "2:" \ + : "=&r" (__dummy)); \ +} while (0) #else #define virt_addr_uncached(kaddr) (0) #define uncached_init() do { } while (0) #define uncached_resize(size) BUG() +#define jump_to_uncached() do { } while (0) +#define back_to_cached() do { } while (0) #endif #endif /* __ASM_SH_UNCACHED_H */ -- cgit v1.2.2 From ccedb20c6879ac0237b95b3500d69822f1e5e2ea Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 4 Nov 2010 12:51:08 +0900 Subject: sh: Simplify phys_addr_mask()/PTE_PHYS_MASK for 29/32-bit. Given that __in_29bit_mode() is a constant for the non-PMB case, we can simply use the PMB-facing version of phys_addr_mask() and drop the other variants. Signed-off-by: Paul Mundt --- arch/sh/include/asm/pgtable.h | 12 ------------ 1 file changed, 12 deletions(-) (limited to 'arch/sh/include') diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h index a15f1058bbf4..083ea068e819 100644 --- a/arch/sh/include/asm/pgtable.h +++ b/arch/sh/include/asm/pgtable.h @@ -66,7 +66,6 @@ static inline unsigned long long neff_sign_extend(unsigned long val) #define PHYS_ADDR_MASK29 0x1fffffff #define PHYS_ADDR_MASK32 0xffffffff -#ifdef CONFIG_PMB static inline unsigned long phys_addr_mask(void) { /* Is the MMU in 29bit mode? */ @@ -75,17 +74,6 @@ static inline unsigned long phys_addr_mask(void) return PHYS_ADDR_MASK32; } -#elif defined(CONFIG_32BIT) -static inline unsigned long phys_addr_mask(void) -{ - return PHYS_ADDR_MASK32; -} -#else -static inline unsigned long phys_addr_mask(void) -{ - return PHYS_ADDR_MASK29; -} -#endif #define PTE_PHYS_MASK (phys_addr_mask() & PAGE_MASK) #define PTE_FLAGS_MASK (~(PTE_PHYS_MASK) << PAGE_SHIFT) -- cgit v1.2.2