From 4b218e9bb2fbbc57b5a05de41d77c056a134528c Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Tue, 21 Aug 2007 02:36:19 +1000 Subject: [POWERPC] Whitespace cleanup in arch/powerpc Signed-off-by: Scott Wood Signed-off-by: Paul Mackerras --- arch/powerpc/sysdev/cpm2_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/powerpc/sysdev/cpm2_common.c') diff --git a/arch/powerpc/sysdev/cpm2_common.c b/arch/powerpc/sysdev/cpm2_common.c index 924412974795..dbe8d1802189 100644 --- a/arch/powerpc/sysdev/cpm2_common.c +++ b/arch/powerpc/sysdev/cpm2_common.c @@ -201,7 +201,7 @@ int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode) } if (mode == CPM_CLK_RX) - shift +=3; + shift += 3; for (i=0; i<24; i++) { if (clk_map[i][0] == target && clk_map[i][1] == clock) { -- cgit v1.2.2 From 449012daa92a60e42f0d55478641cfa796d51528 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Fri, 14 Sep 2007 15:30:44 -0500 Subject: [POWERPC] cpm2: Infrastructure code cleanup. Mostly sparse fixes (__iomem annotations, etc); also, cpm2_immr is used rather than creating many temporary mappings. Signed-off-by: Scott Wood Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/cpm2_common.c | 56 ++++++++++++++++++++++++++++----------- 1 file changed, 41 insertions(+), 15 deletions(-) (limited to 'arch/powerpc/sysdev/cpm2_common.c') diff --git a/arch/powerpc/sysdev/cpm2_common.c b/arch/powerpc/sysdev/cpm2_common.c index 3bf89b324760..0330ca490928 100644 --- a/arch/powerpc/sysdev/cpm2_common.c +++ b/arch/powerpc/sysdev/cpm2_common.c @@ -33,6 +33,8 @@ #include #include #include +#include + #include #include #include @@ -45,13 +47,12 @@ #include static void cpm2_dpinit(void); -cpm_cpm2_t *cpmp; /* Pointer to comm processor space */ +cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor space */ /* We allocate this here because it is used almost exclusively for * the communication processor devices. */ -cpm2_map_t *cpm2_immr; -intctl_cpm2_t *cpm2_intctl; +cpm2_map_t __iomem *cpm2_immr; #define CPM_MAP_SIZE (0x40000) /* 256k - the PQ3 reserve this amount of space for CPM as it is larger @@ -60,8 +61,11 @@ intctl_cpm2_t *cpm2_intctl; void cpm2_reset(void) { - cpm2_immr = (cpm2_map_t *)ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE); - cpm2_intctl = cpm2_map(im_intctl); +#ifdef CONFIG_PPC_85xx + cpm2_immr = ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE); +#else + cpm2_immr = ioremap(get_immrbase(), CPM_MAP_SIZE); +#endif /* Reclaim the DP memory for our use. */ @@ -91,7 +95,7 @@ cpm2_reset(void) void cpm_setbrg(uint brg, uint rate) { - volatile uint *bp; + u32 __iomem *bp; /* This is good enough to get SMCs running..... */ @@ -113,7 +117,8 @@ cpm_setbrg(uint brg, uint rate) void cpm2_fastbrg(uint brg, uint rate, int div16) { - volatile uint *bp; + u32 __iomem *bp; + u32 val; if (brg < 4) { bp = cpm2_map_size(im_brgc1, 16); @@ -123,10 +128,11 @@ cpm2_fastbrg(uint brg, uint rate, int div16) brg -= 4; } bp += brg; - *bp = ((BRG_INT_CLK / rate) << 1) | CPM_BRG_EN; + val = ((BRG_INT_CLK / rate) << 1) | CPM_BRG_EN; if (div16) - *bp |= CPM_BRG_DIV16; + val |= CPM_BRG_DIV16; + out_be32(bp, val); cpm2_unmap(bp); } @@ -135,8 +141,8 @@ int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode) int ret = 0; int shift; int i, bits = 0; - cpmux_t *im_cpmux; - u32 *reg; + cpmux_t __iomem *im_cpmux; + u32 __iomem *reg; u32 mask = 7; u8 clk_map [24][3] = { {CPM_CLK_FCC1, CPM_BRG5, 0}, @@ -228,13 +234,33 @@ static spinlock_t cpm_dpmem_lock; * until the memory subsystem goes up... */ static rh_block_t cpm_boot_dpmem_rh_block[16]; static rh_info_t cpm_dpmem_info; -static u8* im_dprambase; +static u8 __iomem *im_dprambase; static void cpm2_dpinit(void) { - spin_lock_init(&cpm_dpmem_lock); + struct resource r; + +#ifdef CONFIG_PPC_CPM_NEW_BINDING + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "fsl,cpm2"); + if (!np) + panic("Cannot find CPM2 node"); - im_dprambase = ioremap(CPM_MAP_ADDR, CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE); + if (of_address_to_resource(np, 1, &r)) + panic("Cannot get CPM2 resource 1"); + + of_node_put(np); +#else + r.start = CPM_MAP_ADDR; + r.end = r.start + CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE - 1; +#endif + + im_dprambase = ioremap(r.start, r.end - r.start + 1); + if (!im_dprambase) + panic("Cannot map DPRAM"); + + spin_lock_init(&cpm_dpmem_lock); /* initialize the info header */ rh_init(&cpm_dpmem_info, 1, @@ -248,7 +274,7 @@ static void cpm2_dpinit(void) * varies with the processor and the microcode patches activated. * But the following should be at least safe. */ - rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE); + rh_attach_region(&cpm_dpmem_info, 0, r.end - r.start + 1); } /* This function returns an index into the DPRAM area. -- cgit v1.2.2 From 2652d4ec4a363487d0106a8bf51f1b081dd7e397 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Mon, 16 Jul 2007 13:26:35 -0500 Subject: [POWERPC] cpm2: Add SCCs to cpm2_clk_setup(), and cpm2_smc_clk_setup(). Signed-off-by: Scott Wood Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/cpm2_common.c | 100 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 95 insertions(+), 5 deletions(-) (limited to 'arch/powerpc/sysdev/cpm2_common.c') diff --git a/arch/powerpc/sysdev/cpm2_common.c b/arch/powerpc/sysdev/cpm2_common.c index 0330ca490928..c6dc0bf614b3 100644 --- a/arch/powerpc/sysdev/cpm2_common.c +++ b/arch/powerpc/sysdev/cpm2_common.c @@ -144,7 +144,8 @@ int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode) cpmux_t __iomem *im_cpmux; u32 __iomem *reg; u32 mask = 7; - u8 clk_map [24][3] = { + + u8 clk_map[][3] = { {CPM_CLK_FCC1, CPM_BRG5, 0}, {CPM_CLK_FCC1, CPM_BRG6, 1}, {CPM_CLK_FCC1, CPM_BRG7, 2}, @@ -168,8 +169,40 @@ int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode) {CPM_CLK_FCC3, CPM_CLK13, 4}, {CPM_CLK_FCC3, CPM_CLK14, 5}, {CPM_CLK_FCC3, CPM_CLK15, 6}, - {CPM_CLK_FCC3, CPM_CLK16, 7} - }; + {CPM_CLK_FCC3, CPM_CLK16, 7}, + {CPM_CLK_SCC1, CPM_BRG1, 0}, + {CPM_CLK_SCC1, CPM_BRG2, 1}, + {CPM_CLK_SCC1, CPM_BRG3, 2}, + {CPM_CLK_SCC1, CPM_BRG4, 3}, + {CPM_CLK_SCC1, CPM_CLK11, 4}, + {CPM_CLK_SCC1, CPM_CLK12, 5}, + {CPM_CLK_SCC1, CPM_CLK3, 6}, + {CPM_CLK_SCC1, CPM_CLK4, 7}, + {CPM_CLK_SCC2, CPM_BRG1, 0}, + {CPM_CLK_SCC2, CPM_BRG2, 1}, + {CPM_CLK_SCC2, CPM_BRG3, 2}, + {CPM_CLK_SCC2, CPM_BRG4, 3}, + {CPM_CLK_SCC2, CPM_CLK11, 4}, + {CPM_CLK_SCC2, CPM_CLK12, 5}, + {CPM_CLK_SCC2, CPM_CLK3, 6}, + {CPM_CLK_SCC2, CPM_CLK4, 7}, + {CPM_CLK_SCC3, CPM_BRG1, 0}, + {CPM_CLK_SCC3, CPM_BRG2, 1}, + {CPM_CLK_SCC3, CPM_BRG3, 2}, + {CPM_CLK_SCC3, CPM_BRG4, 3}, + {CPM_CLK_SCC3, CPM_CLK5, 4}, + {CPM_CLK_SCC3, CPM_CLK6, 5}, + {CPM_CLK_SCC3, CPM_CLK7, 6}, + {CPM_CLK_SCC3, CPM_CLK8, 7}, + {CPM_CLK_SCC4, CPM_BRG1, 0}, + {CPM_CLK_SCC4, CPM_BRG2, 1}, + {CPM_CLK_SCC4, CPM_BRG3, 2}, + {CPM_CLK_SCC4, CPM_BRG4, 3}, + {CPM_CLK_SCC4, CPM_CLK5, 4}, + {CPM_CLK_SCC4, CPM_CLK6, 5}, + {CPM_CLK_SCC4, CPM_CLK7, 6}, + {CPM_CLK_SCC4, CPM_CLK8, 7}, + }; im_cpmux = cpm2_map(im_cpmux); @@ -209,23 +242,80 @@ int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode) if (mode == CPM_CLK_RX) shift += 3; - for (i=0; i<24; i++) { + for (i = 0; i < ARRAY_SIZE(clk_map); i++) { if (clk_map[i][0] == target && clk_map[i][1] == clock) { bits = clk_map[i][2]; break; } } - if (i == sizeof(clk_map)/3) + if (i == ARRAY_SIZE(clk_map)) ret = -EINVAL; bits <<= shift; mask <<= shift; + out_be32(reg, (in_be32(reg) & ~mask) | bits); cpm2_unmap(im_cpmux); return ret; } +int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock) +{ + int ret = 0; + int shift; + int i, bits = 0; + cpmux_t __iomem *im_cpmux; + u8 __iomem *reg; + u8 mask = 3; + + u8 clk_map[][3] = { + {CPM_CLK_SMC1, CPM_BRG1, 0}, + {CPM_CLK_SMC1, CPM_BRG7, 1}, + {CPM_CLK_SMC1, CPM_CLK7, 2}, + {CPM_CLK_SMC1, CPM_CLK9, 3}, + {CPM_CLK_SMC2, CPM_BRG2, 0}, + {CPM_CLK_SMC2, CPM_BRG8, 1}, + {CPM_CLK_SMC2, CPM_CLK4, 2}, + {CPM_CLK_SMC2, CPM_CLK15, 3}, + }; + + im_cpmux = cpm2_map(im_cpmux); + + switch (target) { + case CPM_CLK_SMC1: + reg = &im_cpmux->cmx_smr; + mask = 3; + shift = 4; + break; + case CPM_CLK_SMC2: + reg = &im_cpmux->cmx_smr; + mask = 3; + shift = 0; + break; + default: + printk(KERN_ERR "cpm2_smc_clock_setup: invalid clock target\n"); + return -EINVAL; + } + + for (i = 0; i < ARRAY_SIZE(clk_map); i++) { + if (clk_map[i][0] == target && clk_map[i][1] == clock) { + bits = clk_map[i][2]; + break; + } + } + if (i == ARRAY_SIZE(clk_map)) + ret = -EINVAL; + + bits <<= shift; + mask <<= shift; + + out_8(reg, (in_8(reg) & ~mask) | bits); + + cpm2_unmap(im_cpmux); + return ret; +} + /* * dpalloc / dpfree bits. */ -- cgit v1.2.2 From 7f21f52940212c25b4387c2450018e161043549a Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Mon, 16 Jul 2007 13:32:24 -0500 Subject: [POWERPC] cpm2: Add cpm2_set_pin(). This provides a generic way for board code to set up CPM pins, rather than directly poking magic values into registers. Signed-off-by: Scott Wood Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/cpm2_common.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'arch/powerpc/sysdev/cpm2_common.c') diff --git a/arch/powerpc/sysdev/cpm2_common.c b/arch/powerpc/sysdev/cpm2_common.c index c6dc0bf614b3..fc4c99565381 100644 --- a/arch/powerpc/sysdev/cpm2_common.c +++ b/arch/powerpc/sysdev/cpm2_common.c @@ -422,3 +422,36 @@ void *cpm_dpram_addr(unsigned long offset) return (void *)(im_dprambase + offset); } EXPORT_SYMBOL(cpm_dpram_addr); + +struct cpm2_ioports { + u32 dir, par, sor, odr, dat; + u32 res[3]; +}; + +void cpm2_set_pin(int port, int pin, int flags) +{ + struct cpm2_ioports __iomem *iop = + (struct cpm2_ioports __iomem *)&cpm2_immr->im_ioport; + + pin = 1 << (31 - pin); + + if (flags & CPM_PIN_OUTPUT) + setbits32(&iop[port].dir, pin); + else + clrbits32(&iop[port].dir, pin); + + if (!(flags & CPM_PIN_GPIO)) + setbits32(&iop[port].par, pin); + else + clrbits32(&iop[port].par, pin); + + if (flags & CPM_PIN_SECONDARY) + setbits32(&iop[port].sor, pin); + else + clrbits32(&iop[port].sor, pin); + + if (flags & CPM_PIN_OPENDRAIN) + setbits32(&iop[port].odr, pin); + else + clrbits32(&iop[port].odr, pin); +} -- cgit v1.2.2 From 15f8c604a79c4840ed76eecf3af5d88b7c1dee9e Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Fri, 28 Sep 2007 14:06:16 -0500 Subject: [POWERPC] cpm: Describe multi-user ram in its own device node. The way the current CPM binding describes available multi-user (a.k.a. dual-ported) RAM doesn't work well when there are multiple free regions, and it doesn't work at all if the region doesn't begin at the start of the muram area (as the hardware needs to be programmed with offsets into this area). The latter situation can happen with SMC UARTs on CPM2, as its parameter RAM is relocatable, u-boot puts it at zero, and the kernel doesn't support moving it. It is now described with a muram node, similar to QE. The current CPM binding is sufficiently recent (i.e. never appeared in an official release) that compatibility with existing device trees is not an issue. The code supporting the new binding is shared between cpm1 and cpm2, rather than remain separated. QE should be able to use this code as well, once minor fixes are made to its device trees. Signed-off-by: Scott Wood Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/cpm2_common.c | 35 ++++++++++++----------------------- 1 file changed, 12 insertions(+), 23 deletions(-) (limited to 'arch/powerpc/sysdev/cpm2_common.c') diff --git a/arch/powerpc/sysdev/cpm2_common.c b/arch/powerpc/sysdev/cpm2_common.c index fc4c99565381..859362fecb7c 100644 --- a/arch/powerpc/sysdev/cpm2_common.c +++ b/arch/powerpc/sysdev/cpm2_common.c @@ -46,7 +46,10 @@ #include +#ifndef CONFIG_PPC_CPM_NEW_BINDING static void cpm2_dpinit(void); +#endif + cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor space */ /* We allocate this here because it is used almost exclusively for @@ -69,7 +72,11 @@ cpm2_reset(void) /* Reclaim the DP memory for our use. */ +#ifdef CONFIG_PPC_CPM_NEW_BINDING + cpm_muram_init(); +#else cpm2_dpinit(); +#endif /* Tell everyone where the comm processor resides. */ @@ -316,6 +323,7 @@ int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock) return ret; } +#ifndef CONFIG_PPC_CPM_NEW_BINDING /* * dpalloc / dpfree bits. */ @@ -328,28 +336,6 @@ static u8 __iomem *im_dprambase; static void cpm2_dpinit(void) { - struct resource r; - -#ifdef CONFIG_PPC_CPM_NEW_BINDING - struct device_node *np; - - np = of_find_compatible_node(NULL, NULL, "fsl,cpm2"); - if (!np) - panic("Cannot find CPM2 node"); - - if (of_address_to_resource(np, 1, &r)) - panic("Cannot get CPM2 resource 1"); - - of_node_put(np); -#else - r.start = CPM_MAP_ADDR; - r.end = r.start + CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE - 1; -#endif - - im_dprambase = ioremap(r.start, r.end - r.start + 1); - if (!im_dprambase) - panic("Cannot map DPRAM"); - spin_lock_init(&cpm_dpmem_lock); /* initialize the info header */ @@ -358,13 +344,15 @@ static void cpm2_dpinit(void) sizeof(cpm_boot_dpmem_rh_block[0]), cpm_boot_dpmem_rh_block); + im_dprambase = cpm2_immr; + /* Attach the usable dpmem area */ /* XXX: This is actually crap. CPM_DATAONLY_BASE and * CPM_DATAONLY_SIZE is only a subset of the available dpram. It * varies with the processor and the microcode patches activated. * But the following should be at least safe. */ - rh_attach_region(&cpm_dpmem_info, 0, r.end - r.start + 1); + rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE); } /* This function returns an index into the DPRAM area. @@ -422,6 +410,7 @@ void *cpm_dpram_addr(unsigned long offset) return (void *)(im_dprambase + offset); } EXPORT_SYMBOL(cpm_dpram_addr); +#endif /* !CONFIG_PPC_CPM_NEW_BINDING */ struct cpm2_ioports { u32 dir, par, sor, odr, dat; -- cgit v1.2.2