From dbdf04c40161f81d74e27f04e201acb3a5dfad69 Mon Sep 17 00:00:00 2001 From: Maxim Shchetynin Date: Fri, 20 Jul 2007 21:39:26 +0200 Subject: [CELL] driver for DDR2 memory on AXON The Axon bridge chip used on new Cell/B.E. based blade servers comes with a DDR2 memory controller that can be used to attach cheap memory modules, as opposed to the high-speed XDR memory that is used by the CPU itself. Since the memory controller does not participate in the cache coherency protocol, we can not use the memory direcly for Linux applications, but by providing a block device it can be used for swap space, temporary file storage and through the use of the direct_access block device operation for mapping into user addresses, when it is mounted with an appropriate file system. Signed-off-by: Maxim Shchetynin Signed-off-by: Arnd Bergmann --- arch/powerpc/sysdev/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/powerpc/sysdev/Makefile') diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile index f65078c3d3b3..484eb4e0e9db 100644 --- a/arch/powerpc/sysdev/Makefile +++ b/arch/powerpc/sysdev/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_QUICC_ENGINE) += qe_lib/ mv64x60-$(CONFIG_PCI) += mv64x60_pci.o obj-$(CONFIG_MV64X60) += $(mv64x60-y) mv64x60_pic.o mv64x60_dev.o obj-$(CONFIG_RTC_DRV_CMOS) += rtc_cmos_setup.o +obj-$(CONFIG_AXON_RAM) += axonram.o # contains only the suspend handler for time ifeq ($(CONFIG_RTC_CLASS),) -- cgit v1.2.2