From 7ac33417ecf8c012df0e957cfa0628a6a4347c7d Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Thu, 15 Nov 2007 21:47:06 +0300 Subject: [POWERPC] Fix potential NULL dereference This patch does fix potential NULL pointer dereference that could take place inside of strcmp() if of_get_property() call failed. Signed-off-by: Cyrill Gorcunov Signed-off-by: Kumar Gala --- arch/powerpc/platforms/83xx/usb.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/powerpc/platforms') diff --git a/arch/powerpc/platforms/83xx/usb.c b/arch/powerpc/platforms/83xx/usb.c index eafe7605cdac..b45160f8d084 100644 --- a/arch/powerpc/platforms/83xx/usb.c +++ b/arch/powerpc/platforms/83xx/usb.c @@ -130,7 +130,7 @@ int mpc831x_usb_cfg(void) out_be32(immap + MPC83XX_SCCR_OFFS, temp); /* Configure pin mux for ULPI. There is no pin mux for UTMI */ - if (!strcmp(prop, "ulpi")) { + if (prop && !strcmp(prop, "ulpi")) { temp = in_be32(immap + MPC83XX_SICRL_OFFS); temp &= ~MPC831X_SICRL_USB_MASK; temp |= MPC831X_SICRL_USB_ULPI; @@ -153,13 +153,13 @@ int mpc831x_usb_cfg(void) usb_regs = ioremap(res.start, res.end - res.start + 1); /* Using on-chip PHY */ - if (!strcmp(prop, "utmi_wide") || - !strcmp(prop, "utmi")) { + if (prop && (!strcmp(prop, "utmi_wide") || + !strcmp(prop, "utmi"))) { /* Set UTMI_PHY_EN, REFSEL to 48MHZ */ out_be32(usb_regs + FSL_USB2_CONTROL_OFFS, CONTROL_UTMI_PHY_EN | CONTROL_REFSEL_48MHZ); /* Using external UPLI PHY */ - } else if (!strcmp(prop, "ulpi")) { + } else if (prop && !strcmp(prop, "ulpi")) { /* Set PHY_CLK_SEL to ULPI */ temp = CONTROL_PHY_CLK_SEL_ULPI; #ifdef CONFIG_USB_OTG -- cgit v1.2.2 From d8ecbb93bece05df84e654c296c3c81b3d347c2d Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 19 Nov 2007 19:04:43 -0600 Subject: [POWERPC] 83xx: mpc832x mds: Fix board PHY reset code currently the board-level PHY reset code for the mpc832x MDS messes with reset configuration words source settings which is plain wrong (it looks like this board code was cut-n-pasted from the mpc8360 mds code, which has the PHY reset bits in a different BCSR); this patch points the PHY reset code to the proper mpc832x mds PHY reset bits in the BCSR. Signed-off-by: Peter Van Ackeren Signed-off-by: Kim Phillips Signed-off-by: Kumar Gala --- arch/powerpc/platforms/83xx/mpc832x_mds.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'arch/powerpc/platforms') diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c index 972fa8528a8c..9e3bfcca1cea 100644 --- a/arch/powerpc/platforms/83xx/mpc832x_mds.c +++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c @@ -90,10 +90,11 @@ static void __init mpc832x_sys_setup_arch(void) if ((np = of_find_compatible_node(NULL, "network", "ucc_geth")) != NULL){ - /* Reset the Ethernet PHY */ - bcsr_regs[9] &= ~0x20; + /* Reset the Ethernet PHYs */ +#define BCSR8_FETH_RST 0x50 + bcsr_regs[8] &= ~BCSR8_FETH_RST; udelay(1000); - bcsr_regs[9] |= 0x20; + bcsr_regs[8] |= BCSR8_FETH_RST; iounmap(bcsr_regs); of_node_put(np); } -- cgit v1.2.2 From 29a50a8bd04ce88efe530fad4d0e21d045c0f25a Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 5 Nov 2007 12:15:51 -0600 Subject: [POWERPC] 83xx: Handle mpc8360 rev. 2.1 RGMII timing erratum If on a rev. 2.1, adjust UCC clock and data timing characteristics as specified in the rev.2.1 erratum #2. Signed-off-by: Kim Phillips Signed-off-by: Kumar Gala --- arch/powerpc/platforms/83xx/mpc836x_mds.c | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) (limited to 'arch/powerpc/platforms') diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c index 0f3855c95ff5..0a722601a2f0 100644 --- a/arch/powerpc/platforms/83xx/mpc836x_mds.c +++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c @@ -96,14 +96,39 @@ static void __init mpc836x_mds_setup_arch(void) if ((np = of_find_compatible_node(NULL, "network", "ucc_geth")) != NULL){ + uint svid; + /* Reset the Ethernet PHY */ - bcsr_regs[9] &= ~0x20; +#define BCSR9_GETHRST 0x20 + clrbits8(&bcsr_regs[9], BCSR9_GETHRST); udelay(1000); - bcsr_regs[9] |= 0x20; + setbits8(&bcsr_regs[9], BCSR9_GETHRST); + + /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */ + svid = mfspr(SPRN_SVR); + if (svid == 0x80480021) { + void __iomem *immap; + + immap = ioremap(get_immrbase() + 0x14a8, 8); + + /* + * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) + * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) + */ + setbits32(immap, 0x0c003000); + + /* + * IMMR + 0x14AC[20:27] = 10101010 + * (data delay for both UCC's) + */ + clrsetbits_be32(immap + 4, 0xff0, 0xaa0); + + iounmap(immap); + } + iounmap(bcsr_regs); of_node_put(np); } - #endif /* CONFIG_QUICC_ENGINE */ } -- cgit v1.2.2