From a6f71745969d495d697d1ccd96385d2f7a963375 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 28 Jan 2008 13:23:42 -0600 Subject: [POWERPC] 85xx: Only invalidate TLB0 and TLB1 All current 85xx/e500 implementations only have two TLB arrays. We are wasting cycles by invalidating TLB2 and TLB3. Signed-off-by: Kumar Gala --- arch/powerpc/kernel/misc_32.S | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'arch/powerpc/kernel/misc_32.S') diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S index be09f0d2d90b..5c2e253ddfb1 100644 --- a/arch/powerpc/kernel/misc_32.S +++ b/arch/powerpc/kernel/misc_32.S @@ -275,12 +275,6 @@ _GLOBAL(_tlbia) /* Invalidate all entries in TLB1 */ li r3, 0x0c tlbivax 0,3 - /* Invalidate all entries in TLB2 */ - li r3, 0x14 - tlbivax 0,3 - /* Invalidate all entries in TLB3 */ - li r3, 0x1c - tlbivax 0,3 msync #ifdef CONFIG_SMP tlbsync @@ -375,12 +369,8 @@ _GLOBAL(_tlbie) #elif defined(CONFIG_FSL_BOOKE) rlwinm r4, r3, 0, 0, 19 ori r5, r4, 0x08 /* TLBSEL = 1 */ - ori r6, r4, 0x10 /* TLBSEL = 2 */ - ori r7, r4, 0x18 /* TLBSEL = 3 */ tlbivax 0, r4 tlbivax 0, r5 - tlbivax 0, r6 - tlbivax 0, r7 msync #if defined(CONFIG_SMP) tlbsync -- cgit v1.2.2