drivers/net/sgiseeq.h



1da177e4c3f4


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/*
 * sgiseeq.h: Defines for the Seeq8003 ethernet controller.
 *
 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
 */
#ifndef _SGISEEQ_H
#define _SGISEEQ_H

struct sgiseeq_wregs {
	volatile unsigned int multicase_high[2];
	volatile unsigned int frame_gap;
	volatile unsigned int control;
};

struct sgiseeq_rregs {
	volatile unsigned int collision_tx[2];
	volatile unsigned int collision_all[2];
	volatile unsigned int _unused0;
	volatile unsigned int rflags; 
};

struct sgiseeq_regs {
	union {
		volatile unsigned int eth_addr[6];
		volatile unsigned int multicast_low[6];
		struct sgiseeq_wregs wregs;
		struct sgiseeq_rregs rregs;
	} rw;
	volatile unsigned int rstat;
	volatile unsigned int tstat;
};

/* Seeq8003 receive status register */
#define SEEQ_RSTAT_OVERF   0x001 /* Overflow */
#define SEEQ_RSTAT_CERROR  0x002 /* CRC error */
#define SEEQ_RSTAT_DERROR  0x004 /* Dribble error */
#define SEEQ_RSTAT_SFRAME  0x008 /* Short frame */
#define SEEQ_RSTAT_REOF    0x010 /* Received end of frame */
#define SEEQ_RSTAT_FIG     0x020 /* Frame is good */
#define SEEQ_RSTAT_TIMEO   0x040 /* Timeout, or late receive */
#define SEEQ_RSTAT_WHICH   0x080 /* Which status, 1=old 0=new */
#define SEEQ_RSTAT_LITTLE  0x100 /* DMA is done in little endian format */
#define SEEQ_RSTAT_SDMA    0x200 /* DMA has started */
#define SEEQ_RSTAT_ADMA    0x400 /* DMA is active */
#define SEEQ_RSTAT_ROVERF  0x800 /* Receive buffer overflow */

/* Seeq8003 receive command register */
#define SEEQ_RCMD_RDISAB   0x000 /* Disable receiver on the Seeq8003 */
#define SEEQ_RCMD_IOVERF   0x001 /* IRQ on buffer overflows */
#define SEEQ_RCMD_ICRC     0x002 /* IRQ on CRC errors */
#define SEEQ_RCMD_IDRIB    0x004 /* IRQ on dribble errors */
#define SEEQ_RCMD_ISHORT   0x008 /* IRQ on short frames */
#define SEEQ_RCMD_IEOF     0x010 /* IRQ on end of frame */
#define SEEQ_RCMD_IGOOD    0x020 /* IRQ on good frames */
#define SEEQ_RCMD_RANY     0x040 /* Receive any frame */
#define SEEQ_RCMD_RBCAST   0x080 /* Receive broadcasts */
#define SEEQ_RCMD_RBMCAST  0x0c0 /* Receive broadcasts/multicasts */

/* Seeq8003 transmit status register */
#define SEEQ_TSTAT_UFLOW   0x001 /* Transmit buffer underflow */
#define SEEQ_TSTAT_CLS     0x002 /* Collision detected */
#define SEEQ_TSTAT_R16     0x004 /* Did 16 retries to tx a frame */
#define SEEQ_TSTAT_PTRANS  0x008 /* Packet was transmitted ok */
#define SEEQ_TSTAT_LCLS    0x010 /* Late collision occurred */
#define SEEQ_TSTAT_WHICH   0x080 /* Which status, 1=old 0=new */
#define SEEQ_TSTAT_TLE     0x100 /* DMA is done in little endian format */
#define SEEQ_TSTAT_SDMA    0x200 /* DMA has started */
#define SEEQ_TSTAT_ADMA    0x400 /* DMA is active */

/* Seeq8003 transmit command register */
#define SEEQ_TCMD_RB0      0x00 /* Register bank zero w/station addr */
#define SEEQ_TCMD_IUF      0x01 /* IRQ on tx underflow */
#define SEEQ_TCMD_IC       0x02 /* IRQ on collisions */