From 9ac4dd301eebb3cd8de801e02bfc91f296e56f63 Mon Sep 17 00:00:00 2001 From: Zang Roy-r61911 Date: Tue, 10 Jul 2007 18:46:35 +0800 Subject: [POWERPC] Rewrite Freescale PCI/PCIe support for 8{3,5,6}xx Rewrite the Freescale PCI code to support PCI on 83xx/85xx/86xx and PCIe on 85xx/86xx. Signed-off-by: Roy Zang Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/mpc8641_hpcn.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/powerpc/boot/dts') diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts index 6a78a2b37c08..5d82709cfcbb 100644 --- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts +++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts @@ -211,8 +211,8 @@ interrupt-parent = <&mpic>; }; - pci@8000 { - compatible = "86xx"; + pcie@8000 { + compatible = "fsl,mpc8641-pcie"; device_type = "pci"; #interrupt-cells = <1>; #size-cells = <2>; @@ -399,8 +399,8 @@ }; - pci@9000 { - compatible = "86xx"; + pcie@9000 { + compatible = "fsl,mpc8641-pcie"; device_type = "pci"; #interrupt-cells = <1>; #size-cells = <2>; -- cgit v1.2.2 From 02edff59c9383acd01f4f2205d663c8abc57070f Mon Sep 17 00:00:00 2001 From: Roy Zang Date: Tue, 10 Jul 2007 18:46:47 +0800 Subject: [POWERPC] Add 8548 CDS PCI express controller node and PCI-X device node Add 8548 CDS PCI express controller node and PCI-X device node. The current dts file is suitable for 8548 Rev 2.0 board with Arcadia 3.1. This kind of board combination is the most popular. Used the following compatible properties: PCI "fsl,mpc8540-pci" PCI-X: "fsl,mpc8540-pcix" PCIe: "fsl,mpc8548-pcie" Signed-off-by: Roy Zang Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/mpc8548cds.dts | 156 +++++++++++++++++++++++------------ 1 file changed, 105 insertions(+), 51 deletions(-) (limited to 'arch/powerpc/boot/dts') diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts index 9d0b84b66cd4..4770a5b96838 100644 --- a/arch/powerpc/boot/dts/mpc8548cds.dts +++ b/arch/powerpc/boot/dts/mpc8548cds.dts @@ -1,5 +1,5 @@ /* - * MPC8555 CDS Device Tree Source + * MPC8548 CDS Device Tree Source * * Copyright 2006 Freescale Semiconductor Inc. * @@ -186,67 +186,96 @@ pci1: pci@8000 { interrupt-map-mask = <1f800 0 0 7>; interrupt-map = < + /* IDSEL 0x4 (PCIX Slot 2) */ + 02000 0 0 1 &mpic 0 1 + 02000 0 0 2 &mpic 1 1 + 02000 0 0 3 &mpic 2 1 + 02000 0 0 4 &mpic 3 1 + + /* IDSEL 0x5 (PCIX Slot 3) */ + 02800 0 0 1 &mpic 1 1 + 02800 0 0 2 &mpic 2 1 + 02800 0 0 3 &mpic 3 1 + 02800 0 0 4 &mpic 0 1 + + /* IDSEL 0x6 (PCIX Slot 4) */ + 03000 0 0 1 &mpic 2 1 + 03000 0 0 2 &mpic 3 1 + 03000 0 0 3 &mpic 0 1 + 03000 0 0 4 &mpic 1 1 + + /* IDSEL 0x8 (PCIX Slot 5) */ + 04000 0 0 1 &mpic 0 1 + 04000 0 0 2 &mpic 1 1 + 04000 0 0 3 &mpic 2 1 + 04000 0 0 4 &mpic 3 1 + + /* IDSEL 0xC (Tsi310 bridge) */ + 06000 0 0 1 &mpic 0 1 + 06000 0 0 2 &mpic 1 1 + 06000 0 0 3 &mpic 2 1 + 06000 0 0 4 &mpic 3 1 + + /* IDSEL 0x14 (Slot 2) */ + 0a000 0 0 1 &mpic 0 1 + 0a000 0 0 2 &mpic 1 1 + 0a000 0 0 3 &mpic 2 1 + 0a000 0 0 4 &mpic 3 1 + + /* IDSEL 0x15 (Slot 3) */ + 0a800 0 0 1 &mpic 1 1 + 0a800 0 0 2 &mpic 2 1 + 0a800 0 0 3 &mpic 3 1 + 0a800 0 0 4 &mpic 0 1 + + /* IDSEL 0x16 (Slot 4) */ + 0b000 0 0 1 &mpic 2 1 + 0b000 0 0 2 &mpic 3 1 + 0b000 0 0 3 &mpic 0 1 + 0b000 0 0 4 &mpic 1 1 + + /* IDSEL 0x18 (Slot 5) */ + 0c000 0 0 1 &mpic 0 1 + 0c000 0 0 2 &mpic 1 1 + 0c000 0 0 3 &mpic 2 1 + 0c000 0 0 4 &mpic 3 1 + + /* IDSEL 0x1C (Tsi310 bridge PCI primary) */ + 0E000 0 0 1 &mpic 0 1 + 0E000 0 0 2 &mpic 1 1 + 0E000 0 0 3 &mpic 2 1 + 0E000 0 0 4 &mpic 3 1 + + /* bus 1 , idsel 0x2 Tsi310 bridge secondary */ + 11000 0 0 1 &mpic 2 1 + 11000 0 0 2 &mpic 3 1 + 11000 0 0 3 &mpic 0 1 + 11000 0 0 4 &mpic 1 1 + + /* VIA chip */ + 12000 0 0 1 &mpic 0 1 + 12000 0 0 2 &mpic 1 1 + 12000 0 0 3 &mpic 2 1 + 12000 0 0 4 &mpic 3 1>; - /* IDSEL 0x10 */ - 08000 0 0 1 &mpic 0 1 - 08000 0 0 2 &mpic 1 1 - 08000 0 0 3 &mpic 2 1 - 08000 0 0 4 &mpic 3 1 - - /* IDSEL 0x11 */ - 08800 0 0 1 &mpic 0 1 - 08800 0 0 2 &mpic 1 1 - 08800 0 0 3 &mpic 2 1 - 08800 0 0 4 &mpic 3 1 - - /* IDSEL 0x12 (Slot 1) */ - 09000 0 0 1 &mpic 0 1 - 09000 0 0 2 &mpic 1 1 - 09000 0 0 3 &mpic 2 1 - 09000 0 0 4 &mpic 3 1 - - /* IDSEL 0x13 (Slot 2) */ - 09800 0 0 1 &mpic 1 1 - 09800 0 0 2 &mpic 2 1 - 09800 0 0 3 &mpic 3 1 - 09800 0 0 4 &mpic 0 1 - - /* IDSEL 0x14 (Slot 3) */ - 0a000 0 0 1 &mpic 2 1 - 0a000 0 0 2 &mpic 3 1 - 0a000 0 0 3 &mpic 0 1 - 0a000 0 0 4 &mpic 1 1 - - /* IDSEL 0x15 (Slot 4) */ - 0a800 0 0 1 &mpic 3 1 - 0a800 0 0 2 &mpic 0 1 - 0a800 0 0 3 &mpic 1 1 - 0a800 0 0 4 &mpic 2 1 - - /* Bus 1 (Tundra Bridge) */ - /* IDSEL 0x12 (ISA bridge) */ - 19000 0 0 1 &mpic 0 1 - 19000 0 0 2 &mpic 1 1 - 19000 0 0 3 &mpic 2 1 - 19000 0 0 4 &mpic 3 1>; interrupt-parent = <&mpic>; interrupts = <18 2>; bus-range = <0 0>; - ranges = <02000000 0 80000000 80000000 0 20000000 - 01000000 0 00000000 e2000000 0 00100000>; + ranges = <02000000 0 80000000 80000000 0 10000000 + 01000000 0 00000000 e2000000 0 00800000>; clock-frequency = <3f940aa>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; reg = <8000 1000>; - compatible = "85xx"; + compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; device_type = "pci"; - i8259@19000 { + i8259@4 { clock-frequency = <0>; interrupt-controller; device_type = "interrupt-controller"; - reg = <19000 0 0 0 1>; + reg = <12000 0 0 0 1>; #address-cells = <0>; #interrupt-cells = <2>; built-in; @@ -266,17 +295,42 @@ a800 0 0 2 &mpic b 1 a800 0 0 3 &mpic b 1 a800 0 0 4 &mpic b 1>; + interrupt-parent = <&mpic>; interrupts = <19 2>; bus-range = <0 0>; - ranges = <02000000 0 a0000000 a0000000 0 20000000 - 01000000 0 00000000 e3000000 0 00100000>; + ranges = <02000000 0 90000000 90000000 0 10000000 + 01000000 0 00000000 e2800000 0 00800000>; clock-frequency = <3f940aa>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; reg = <9000 1000>; - compatible = "85xx"; + compatible = "fsl,mpc8540-pci"; + device_type = "pci"; + }; + /* PCI Express */ + pcie@a000 { + interrupt-map-mask = ; + interrupt-map = < + + /* IDSEL 0x0 (PEX) */ + 00000 0 0 1 &mpic 0 1 + 00000 0 0 2 &mpic 1 1 + 00000 0 0 3 &mpic 2 1 + 00000 0 0 4 &mpic 3 1>; + + interrupt-parent = <&mpic>; + interrupts = <1a 2>; + bus-range = <0 ff>; + ranges = <02000000 0 a0000000 a0000000 0 20000000 + 01000000 0 00000000 e3000000 0 08000000>; + clock-frequency = <1fca055>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + compatible = "fsl,mpc8548-pcie"; device_type = "pci"; }; -- cgit v1.2.2 From 344ffde71e65fb0ef4b73590015362005a59b3c0 Mon Sep 17 00:00:00 2001 From: Roy Zang Date: Tue, 10 Jul 2007 18:47:21 +0800 Subject: [POWERPC] Update PCI nodes in the 83xx/85xx boards device tree Updated the 83xx & 85xx device tree PCI related compartible property. Used the following compatible properties: PCI "fsl,mpc8349-pci" PCI "fsl,mpc8540-pci" PCI-X: "fsl,mpc8540-pcix" PCIe: "fsl,mpc8548-pcie" Signed-off-by: Roy Zang Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/mpc8313erdb.dts | 2 +- arch/powerpc/boot/dts/mpc832x_mds.dts | 2 +- arch/powerpc/boot/dts/mpc832x_rdb.dts | 2 +- arch/powerpc/boot/dts/mpc8349emitx.dts | 4 ++-- arch/powerpc/boot/dts/mpc8349emitxgp.dts | 2 +- arch/powerpc/boot/dts/mpc834x_mds.dts | 4 ++-- arch/powerpc/boot/dts/mpc836x_mds.dts | 2 +- arch/powerpc/boot/dts/mpc8540ads.dts | 2 +- arch/powerpc/boot/dts/mpc8541cds.dts | 4 ++-- arch/powerpc/boot/dts/mpc8555cds.dts | 4 ++-- arch/powerpc/boot/dts/mpc8560ads.dts | 2 +- 11 files changed, 15 insertions(+), 15 deletions(-) (limited to 'arch/powerpc/boot/dts') diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts index a1533cc07d09..c5adbe40364e 100644 --- a/arch/powerpc/boot/dts/mpc8313erdb.dts +++ b/arch/powerpc/boot/dts/mpc8313erdb.dts @@ -178,7 +178,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8500 100>; - compatible = "83xx"; + compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts index 4fc0c4d34aa8..f158ed781ba8 100644 --- a/arch/powerpc/boot/dts/mpc832x_mds.dts +++ b/arch/powerpc/boot/dts/mpc832x_mds.dts @@ -154,7 +154,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8500 100>; - compatible = "83xx"; + compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts index 447c03ffabbc..7c4beff3e200 100644 --- a/arch/powerpc/boot/dts/mpc832x_rdb.dts +++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts @@ -123,7 +123,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8500 100>; - compatible = "83xx"; + compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts index ae9bca575453..502f47c01797 100644 --- a/arch/powerpc/boot/dts/mpc8349emitx.dts +++ b/arch/powerpc/boot/dts/mpc8349emitx.dts @@ -197,7 +197,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8500 100>; - compatible = "83xx"; + compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; @@ -222,7 +222,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8600 100>; - compatible = "83xx"; + compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts index f636528a3c72..0b8387141d88 100644 --- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts +++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts @@ -154,7 +154,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8600 100>; - compatible = "83xx"; + compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts index 310e877826b4..481099756e44 100644 --- a/arch/powerpc/boot/dts/mpc834x_mds.dts +++ b/arch/powerpc/boot/dts/mpc834x_mds.dts @@ -241,7 +241,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8500 100>; - compatible = "83xx"; + compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; @@ -301,7 +301,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8600 100>; - compatible = "83xx"; + compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts index 1e914f31dd92..e3f7c1282068 100644 --- a/arch/powerpc/boot/dts/mpc836x_mds.dts +++ b/arch/powerpc/boot/dts/mpc836x_mds.dts @@ -169,7 +169,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8500 100>; - compatible = "83xx"; + compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts index 364a969f5c2f..fc8dff9f6201 100644 --- a/arch/powerpc/boot/dts/mpc8540ads.dts +++ b/arch/powerpc/boot/dts/mpc8540ads.dts @@ -258,7 +258,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8000 1000>; - compatible = "85xx"; + compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; device_type = "pci"; }; diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts index 070206fffe88..fb0b647f8c2a 100644 --- a/arch/powerpc/boot/dts/mpc8541cds.dts +++ b/arch/powerpc/boot/dts/mpc8541cds.dts @@ -193,7 +193,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8000 1000>; - compatible = "85xx"; + compatible = "fsl,mpc8540-pci"; device_type = "pci"; i8259@19000 { @@ -230,7 +230,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <9000 1000>; - compatible = "85xx"; + compatible = "fsl,mpc8540-pci"; device_type = "pci"; }; diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts index 17e45d9a382a..c3c888252121 100644 --- a/arch/powerpc/boot/dts/mpc8555cds.dts +++ b/arch/powerpc/boot/dts/mpc8555cds.dts @@ -193,7 +193,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <8000 1000>; - compatible = "85xx"; + compatible = "fsl,mpc8540-pci"; device_type = "pci"; i8259@19000 { @@ -230,7 +230,7 @@ #size-cells = <2>; #address-cells = <3>; reg = <9000 1000>; - compatible = "85xx"; + compatible = "fsl,mpc8540-pci"; device_type = "pci"; }; diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts index 21ccaaa27993..16dbe848cecf 100644 --- a/arch/powerpc/boot/dts/mpc8560ads.dts +++ b/arch/powerpc/boot/dts/mpc8560ads.dts @@ -136,7 +136,7 @@ #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - compatible = "85xx"; + compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; device_type = "pci"; reg = <8000 1000>; clock-frequency = <3f940aa>; -- cgit v1.2.2 From 66afe8780f297edb4c4716bc326e127ec2923422 Mon Sep 17 00:00:00 2001 From: Roy Zang Date: Tue, 10 Jul 2007 18:47:52 +0800 Subject: [POWERPC] Add basic PCI node for mpc8568mds board Signed-off-by: Haiying Wang Signed-off-by: Ebony Zhu Signed-off-by: Roy Zang Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/mpc8568mds.dts | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/powerpc/boot/dts') diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts index 6bb18f2807a8..54cde6879645 100644 --- a/arch/powerpc/boot/dts/mpc8568mds.dts +++ b/arch/powerpc/boot/dts/mpc8568mds.dts @@ -170,6 +170,35 @@ interrupt-parent = <&mpic>; }; + pci@8000 { + interrupt-map-mask = ; + interrupt-map = < + /* IDSEL 0x12 AD18 */ + 9000 0 0 1 &mpic 5 1 + 9000 0 0 2 &mpic 6 1 + 9000 0 0 3 &mpic 7 1 + 9000 0 0 4 &mpic 4 1 + + /* IDSEL 0x13 AD19 */ + 9800 0 0 1 &mpic 6 1 + 9800 0 0 2 &mpic 7 1 + 9800 0 0 3 &mpic 4 1 + 9800 0 0 4 &mpic 5 1>; + + interrupt-parent = <&mpic>; + interrupts = <18 2>; + bus-range = <0 ff>; + ranges = <02000000 0 80000000 80000000 0 20000000 + 01000000 0 00000000 e2000000 0 00800000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <8000 1000>; + compatible = "fsl,mpc8540-pci"; + device_type = "pci"; + }; + serial@4600 { device_type = "serial"; compatible = "ns16550"; -- cgit v1.2.2 From aa3c112146e387dcd68bea2a8354514fe725da0d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 16 Jul 2007 10:45:07 -0500 Subject: [POWERPC] 85xx: Added 8568 PCIe support Added the PCIe device node to the 8568 dts and the needed quirk entries. Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/mpc8568mds.dts | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch/powerpc/boot/dts') diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts index 54cde6879645..99fa5a0ea425 100644 --- a/arch/powerpc/boot/dts/mpc8568mds.dts +++ b/arch/powerpc/boot/dts/mpc8568mds.dts @@ -199,6 +199,31 @@ device_type = "pci"; }; + /* PCI Express */ + pcie@a000 { + interrupt-map-mask = ; + interrupt-map = < + + /* IDSEL 0x0 (PEX) */ + 00000 0 0 1 &mpic 0 1 + 00000 0 0 2 &mpic 1 1 + 00000 0 0 3 &mpic 2 1 + 00000 0 0 4 &mpic 3 1>; + + interrupt-parent = <&mpic>; + interrupts = <1a 2>; + bus-range = <0 ff>; + ranges = <02000000 0 a0000000 a0000000 0 20000000 + 01000000 0 00000000 e3000000 0 08000000>; + clock-frequency = <1fca055>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + }; + serial@4600 { device_type = "serial"; compatible = "ns16550"; -- cgit v1.2.2 From f16dab981aa9d423bdfe096e3422acd33d905c1e Mon Sep 17 00:00:00 2001 From: Roy Zang Date: Fri, 13 Jul 2007 18:05:08 +0800 Subject: [POWERPC] Add basic PCI/PCI Express support for 8544DS board Add basic support for the PCIe PHB and enable the ULI bridge. Signed-off-by: York Sun Signed-off-by: Roy Zang Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/mpc8544ds.dts | 211 ++++++++++++++++++++++++++++++++++++ 1 file changed, 211 insertions(+) (limited to 'arch/powerpc/boot/dts') diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts index 828592592460..4a900c6df762 100644 --- a/arch/powerpc/boot/dts/mpc8544ds.dts +++ b/arch/powerpc/boot/dts/mpc8544ds.dts @@ -137,6 +137,217 @@ interrupt-parent = <&mpic>; }; + pci@8000 { + compatible = "fsl,mpc8540-pci"; + device_type = "pci"; + interrupt-map-mask = ; + interrupt-map = < + + /* IDSEL 0x11 J17 Slot 1 */ + 8800 0 0 1 &mpic 2 1 + 8800 0 0 2 &mpic 3 1 + 8800 0 0 3 &mpic 4 1 + 8800 0 0 4 &mpic 1 1 + + /* IDSEL 0x12 J16 Slot 2 */ + + 9000 0 0 1 &mpic 3 1 + 9000 0 0 2 &mpic 4 1 + 9000 0 0 3 &mpic 2 1 + 9000 0 0 4 &mpic 1 1>; + + interrupt-parent = <&mpic>; + interrupts = <18 2>; + bus-range = <0 ff>; + ranges = <02000000 0 80000000 80000000 0 10000000 + 01000000 0 00000000 e2000000 0 00800000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <8000 1000>; + }; + + pcie@9000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <9000 1000>; + bus-range = <0 ff>; + ranges = <02000000 0 90000000 90000000 0 10000000 + 01000000 0 00000000 e3000000 0 00800000>; + clock-frequency = <1fca055>; + interrupt-parent = <&mpic>; + interrupts = <1a 2>; + interrupt-map-mask = ; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 4 1 + 0000 0 0 2 &mpic 5 1 + 0000 0 0 3 &mpic 6 1 + 0000 0 0 4 &mpic 7 1 + >; + }; + + pcie@a000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + bus-range = <0 ff>; + ranges = <02000000 0 a0000000 a0000000 0 10000000 + 01000000 0 00000000 e2800000 0 00800000>; + clock-frequency = <1fca055>; + interrupt-parent = <&mpic>; + interrupts = <19 2>; + interrupt-map-mask = ; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 0 1 + 0000 0 0 2 &mpic 1 1 + 0000 0 0 3 &mpic 2 1 + 0000 0 0 4 &mpic 3 1 + >; + }; + + pcie@b000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + bus-range = <0 ff>; + ranges = <02000000 0 b0000000 b0000000 0 10000000 + 01000000 0 00000000 e3800000 0 00800000>; + clock-frequency = <1fca055>; + interrupt-parent = <&mpic>; + interrupts = <1b 2>; + interrupt-map-mask = ; + interrupt-map = < + + // IDSEL 0x1a + d000 0 0 1 &i8259 6 2 + d000 0 0 2 &i8259 3 2 + d000 0 0 3 &i8259 4 2 + d000 0 0 4 &i8259 5 2 + + // IDSEL 0x1b + d800 0 0 1 &i8259 5 2 + d800 0 0 2 &i8259 0 0 + d800 0 0 3 &i8259 0 0 + d800 0 0 4 &i8259 0 0 + + // IDSEL 0x1c USB + e000 0 0 1 &i8259 9 2 + e000 0 0 2 &i8259 a 2 + e000 0 0 3 &i8259 c 2 + e000 0 0 4 &i8259 7 2 + + // IDSEL 0x1d Audio + e800 0 0 1 &i8259 9 2 + e800 0 0 2 &i8259 a 2 + e800 0 0 3 &i8259 b 2 + e800 0 0 4 &i8259 0 0 + + // IDSEL 0x1e Legacy + f000 0 0 1 &i8259 c 2 + f000 0 0 2 &i8259 0 0 + f000 0 0 3 &i8259 0 0 + f000 0 0 4 &i8259 0 0 + + // IDSEL 0x1f IDE/SATA + f800 0 0 1 &i8259 6 2 + f800 0 0 2 &i8259 0 0 + f800 0 0 3 &i8259 0 0 + f800 0 0 4 &i8259 0 0 + >; + uli1575@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + ranges = <02000000 0 b0000000 + 02000000 0 b0000000 + 0 10000000 + 01000000 0 00000000 + 01000000 0 00000000 + 0 00080000>; + + pci_bridge@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + ranges = <02000000 0 b0000000 + 02000000 0 b0000000 + 0 20000000 + 01000000 0 00000000 + 01000000 0 00000000 + 0 00100000>; + + isa@1e { + device_type = "isa"; + #interrupt-cells = <2>; + #size-cells = <1>; + #address-cells = <2>; + reg = ; + ranges = <1 0 01000000 0 0 + 00001000>; + interrupt-parent = <&i8259>; + + i8259: interrupt-controller@20 { + reg = <1 20 2 + 1 a0 2 + 1 4d0 2>; + clock-frequency = <0>; + interrupt-controller; + device_type = "interrupt-controller"; + #address-cells = <0>; + #interrupt-cells = <2>; + built-in; + compatible = "chrp,iic"; + interrupts = <9 2>; + interrupt-parent = + <&mpic>; + }; + + i8042@60 { + #size-cells = <0>; + #address-cells = <1>; + reg = <1 60 1 1 64 1>; + interrupts = <1 3 c 3>; + interrupt-parent = + <&i8259>; + + keyboard@0 { + reg = <0>; + compatible = "pnpPNP,303"; + }; + + mouse@1 { + reg = <1>; + compatible = "pnpPNP,f03"; + }; + }; + + rtc@70 { + compatible = + "pnpPNP,b00"; + reg = <1 70 2>; + }; + + gpio@400 { + reg = <1 400 80>; + }; + }; + }; + }; + + }; + mpic: pic@40000 { clock-frequency = <0>; interrupt-controller; -- cgit v1.2.2 From 6af012574207bd35455f4a4ba0437cf5b9deaee5 Mon Sep 17 00:00:00 2001 From: Randy Vinson Date: Tue, 17 Jul 2007 16:37:12 -0700 Subject: [POWERPC] 85xxCDS: MPC8548 DTS cleanup. Added the P2P bridge present on the Arcadia base board and moved the VIA Southbridge behind the bridge to reflect its actual position in the bus organization. Added the RTC that's in the VIA Southbridge and expanded the ranges array for the SOC node to allow proper address translation of the RTC registers. Signed-off-by: Randy Vinson Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/mpc8548cds.dts | 124 +++++++++++++++++++++++++---------- 1 file changed, 89 insertions(+), 35 deletions(-) (limited to 'arch/powerpc/boot/dts') diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts index 4770a5b96838..d215d21fff42 100644 --- a/arch/powerpc/boot/dts/mpc8548cds.dts +++ b/arch/powerpc/boot/dts/mpc8548cds.dts @@ -44,8 +44,14 @@ #size-cells = <1>; #interrupt-cells = <2>; device_type = "soc"; - ranges = <0 e0000000 00100000>; - reg = ; // CCSRBAR 1M + ranges = <00001000 e0001000 000ff000 + 80000000 80000000 10000000 + e2000000 e2000000 00800000 + 90000000 90000000 10000000 + e2800000 e2800000 00800000 + a0000000 a0000000 20000000 + e3000000 e3000000 01000000>; + reg = ; // CCSRBAR bus-frequency = <0>; memory-controller@2000 { @@ -162,8 +168,8 @@ serial@4500 { device_type = "serial"; compatible = "ns16550"; - reg = <4500 100>; // reg base, size - clock-frequency = <0>; // should we fill in in uboot? + reg = <4500 100>; // reg base, size + clock-frequency = <0>; // should we fill in in uboot? interrupts = <2a 2>; interrupt-parent = <&mpic>; }; @@ -172,7 +178,7 @@ device_type = "serial"; compatible = "ns16550"; reg = <4600 100>; // reg base, size - clock-frequency = <0>; // should we fill in in uboot? + clock-frequency = <0>; // should we fill in in uboot? interrupts = <2a 2>; interrupt-parent = <&mpic>; }; @@ -183,8 +189,8 @@ fsl,has-rstcr; }; - pci1: pci@8000 { - interrupt-map-mask = <1f800 0 0 7>; + pci@8000 { + interrupt-map-mask = ; interrupt-map = < /* IDSEL 0x4 (PCIX Slot 2) */ 02000 0 0 1 &mpic 0 1 @@ -244,19 +250,7 @@ 0E000 0 0 1 &mpic 0 1 0E000 0 0 2 &mpic 1 1 0E000 0 0 3 &mpic 2 1 - 0E000 0 0 4 &mpic 3 1 - - /* bus 1 , idsel 0x2 Tsi310 bridge secondary */ - 11000 0 0 1 &mpic 2 1 - 11000 0 0 2 &mpic 3 1 - 11000 0 0 3 &mpic 0 1 - 11000 0 0 4 &mpic 1 1 - - /* VIA chip */ - 12000 0 0 1 &mpic 0 1 - 12000 0 0 2 &mpic 1 1 - 12000 0 0 3 &mpic 2 1 - 12000 0 0 4 &mpic 3 1>; + 0E000 0 0 4 &mpic 3 1>; interrupt-parent = <&mpic>; interrupts = <18 2>; @@ -271,18 +265,78 @@ compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; device_type = "pci"; - i8259@4 { - clock-frequency = <0>; - interrupt-controller; - device_type = "interrupt-controller"; - reg = <12000 0 0 0 1>; - #address-cells = <0>; - #interrupt-cells = <2>; - built-in; - compatible = "chrp,iic"; - big-endian; - interrupts = <1>; - interrupt-parent = <&pci1>; + pci_bridge@1c { + interrupt-map-mask = ; + interrupt-map = < + + /* IDSEL 0x00 (PrPMC Site) */ + 0000 0 0 1 &mpic 0 1 + 0000 0 0 2 &mpic 1 1 + 0000 0 0 3 &mpic 2 1 + 0000 0 0 4 &mpic 3 1 + + /* IDSEL 0x04 (VIA chip) */ + 2000 0 0 1 &mpic 0 1 + 2000 0 0 2 &mpic 1 1 + 2000 0 0 3 &mpic 2 1 + 2000 0 0 4 &mpic 3 1 + + /* IDSEL 0x05 (8139) */ + 2800 0 0 1 &mpic 1 1 + + /* IDSEL 0x06 (Slot 6) */ + 3000 0 0 1 &mpic 2 1 + 3000 0 0 2 &mpic 3 1 + 3000 0 0 3 &mpic 0 1 + 3000 0 0 4 &mpic 1 1 + + /* IDESL 0x07 (Slot 7) */ + 3800 0 0 1 &mpic 3 1 + 3800 0 0 2 &mpic 0 1 + 3800 0 0 3 &mpic 1 1 + 3800 0 0 4 &mpic 2 1>; + + reg = ; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + ranges = <02000000 0 80000000 + 02000000 0 80000000 + 0 20000000 + 01000000 0 00000000 + 01000000 0 00000000 + 0 00080000>; + clock-frequency = <1fca055>; + + isa@4 { + device_type = "isa"; + #interrupt-cells = <2>; + #size-cells = <1>; + #address-cells = <2>; + reg = <2000 0 0 0 0>; + ranges = <1 0 01000000 0 0 00001000>; + interrupt-parent = <&i8259>; + + i8259: interrupt-controller@20 { + clock-frequency = <0>; + interrupt-controller; + device_type = "interrupt-controller"; + reg = <1 20 2 + 1 a0 2 + 1 4d0 2>; + #address-cells = <0>; + #interrupt-cells = <2>; + built-in; + compatible = "chrp,iic"; + interrupts = <0 1>; + interrupt-parent = <&mpic>; + }; + + rtc@70 { + compatible = "pnpPNP,b00"; + reg = <1 70 2>; + }; + }; }; }; @@ -292,9 +346,9 @@ /* IDSEL 0x15 */ a800 0 0 1 &mpic b 1 - a800 0 0 2 &mpic b 1 - a800 0 0 3 &mpic b 1 - a800 0 0 4 &mpic b 1>; + a800 0 0 2 &mpic 1 1 + a800 0 0 3 &mpic 2 1 + a800 0 0 4 &mpic 3 1>; interrupt-parent = <&mpic>; interrupts = <19 2>; -- cgit v1.2.2