From 86a04d9c850787040ba63261cfa5eb9a48b58e5a Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 2 Oct 2007 09:51:32 -0500 Subject: [POWERPC] Fixup MPC8568 dts The PCI nodes on the MPC8568 dts didn't get moved up to be sibilings of the SOC node when we did that clean up for some reason. Fix that up and some minor whitespace and adjusting the size of the soc reg property. Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/mpc8568mds.dts | 125 ++++++++++++++++++++--------------- 1 file changed, 70 insertions(+), 55 deletions(-) (limited to 'arch/powerpc/boot/dts/mpc8568mds.dts') diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts index 6923e42af4fd..b064a2ff2306 100644 --- a/arch/powerpc/boot/dts/mpc8568mds.dts +++ b/arch/powerpc/boot/dts/mpc8568mds.dts @@ -52,7 +52,7 @@ #size-cells = <1>; device_type = "soc"; ranges = <0 e0000000 00100000>; - reg = ; + reg = ; bus-frequency = <0>; memory-controller@2000 { @@ -183,60 +183,6 @@ fsl,has-rstcr; }; - pci@8000 { - interrupt-map-mask = ; - interrupt-map = < - /* IDSEL 0x12 AD18 */ - 9000 0 0 1 &mpic 5 1 - 9000 0 0 2 &mpic 6 1 - 9000 0 0 3 &mpic 7 1 - 9000 0 0 4 &mpic 4 1 - - /* IDSEL 0x13 AD19 */ - 9800 0 0 1 &mpic 6 1 - 9800 0 0 2 &mpic 7 1 - 9800 0 0 3 &mpic 4 1 - 9800 0 0 4 &mpic 5 1>; - - interrupt-parent = <&mpic>; - interrupts = <18 2>; - bus-range = <0 ff>; - ranges = <02000000 0 80000000 80000000 0 20000000 - 01000000 0 00000000 e2000000 0 00800000>; - clock-frequency = <3f940aa>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <8000 1000>; - compatible = "fsl,mpc8540-pci"; - device_type = "pci"; - }; - - /* PCI Express */ - pcie@a000 { - interrupt-map-mask = ; - interrupt-map = < - - /* IDSEL 0x0 (PEX) */ - 00000 0 0 1 &mpic 0 1 - 00000 0 0 2 &mpic 1 1 - 00000 0 0 3 &mpic 2 1 - 00000 0 0 4 &mpic 3 1>; - - interrupt-parent = <&mpic>; - interrupts = <1a 2>; - bus-range = <0 ff>; - ranges = <02000000 0 a0000000 a0000000 0 10000000 - 01000000 0 00000000 e2800000 0 00800000>; - clock-frequency = <1fca055>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = ; - compatible = "fsl,mpc8548-pcie"; - device_type = "pci"; - }; - serial@4600 { device_type = "serial"; compatible = "ns16550"; @@ -269,6 +215,7 @@ device_type = "open-pic"; big-endian; }; + par_io@e0100 { reg = ; device_type = "par_io"; @@ -301,6 +248,7 @@ 4 13 1 0 2 0 /* GTX_CLK */ 1 1f 2 0 3 0>; /* GTX125 */ }; + pio2: ucc_pin@02 { pio-map = < /* port pin dir open_drain assignment has_irq */ @@ -461,4 +409,71 @@ }; }; + + pci@e0008000 { + interrupt-map-mask = ; + interrupt-map = < + /* IDSEL 0x12 AD18 */ + 9000 0 0 1 &mpic 5 1 + 9000 0 0 2 &mpic 6 1 + 9000 0 0 3 &mpic 7 1 + 9000 0 0 4 &mpic 4 1 + + /* IDSEL 0x13 AD19 */ + 9800 0 0 1 &mpic 6 1 + 9800 0 0 2 &mpic 7 1 + 9800 0 0 3 &mpic 4 1 + 9800 0 0 4 &mpic 5 1>; + + interrupt-parent = <&mpic>; + interrupts = <18 2>; + bus-range = <0 ff>; + ranges = <02000000 0 80000000 80000000 0 20000000 + 01000000 0 00000000 e2000000 0 00800000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + compatible = "fsl,mpc8540-pci"; + device_type = "pci"; + }; + + /* PCI Express */ + pcie@e000a000 { + interrupt-map-mask = ; + interrupt-map = < + + /* IDSEL 0x0 (PEX) */ + 00000 0 0 1 &mpic 0 1 + 00000 0 0 2 &mpic 1 1 + 00000 0 0 3 &mpic 2 1 + 00000 0 0 4 &mpic 3 1>; + + interrupt-parent = <&mpic>; + interrupts = <1a 2>; + bus-range = <0 ff>; + ranges = <02000000 0 a0000000 a0000000 0 10000000 + 01000000 0 00000000 e2800000 0 00800000>; + clock-frequency = <1fca055>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + pcie@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <02000000 0 a0000000 + 02000000 0 a0000000 + 0 10000000 + + 01000000 0 00000000 + 01000000 0 00000000 + 0 00800000>; + }; + }; }; -- cgit v1.2.2