From 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Sat, 16 Apr 2005 15:20:36 -0700 Subject: Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip! --- arch/mips/sibyte/swarm/Makefile | 3 + arch/mips/sibyte/swarm/dbg_io.c | 76 ++++++++++ arch/mips/sibyte/swarm/rtc_m41t81.c | 224 ++++++++++++++++++++++++++++++ arch/mips/sibyte/swarm/rtc_xicor1241.c | 203 +++++++++++++++++++++++++++ arch/mips/sibyte/swarm/setup.c | 163 ++++++++++++++++++++++ arch/mips/sibyte/swarm/time.c | 244 +++++++++++++++++++++++++++++++++ 6 files changed, 913 insertions(+) create mode 100644 arch/mips/sibyte/swarm/Makefile create mode 100644 arch/mips/sibyte/swarm/dbg_io.c create mode 100644 arch/mips/sibyte/swarm/rtc_m41t81.c create mode 100644 arch/mips/sibyte/swarm/rtc_xicor1241.c create mode 100644 arch/mips/sibyte/swarm/setup.c create mode 100644 arch/mips/sibyte/swarm/time.c (limited to 'arch/mips/sibyte/swarm') diff --git a/arch/mips/sibyte/swarm/Makefile b/arch/mips/sibyte/swarm/Makefile new file mode 100644 index 000000000000..2d626039195c --- /dev/null +++ b/arch/mips/sibyte/swarm/Makefile @@ -0,0 +1,3 @@ +lib-y = setup.o rtc_xicor1241.o rtc_m41t81.o + +lib-$(CONFIG_KGDB) += dbg_io.o diff --git a/arch/mips/sibyte/swarm/dbg_io.c b/arch/mips/sibyte/swarm/dbg_io.c new file mode 100644 index 000000000000..75ce14c8eb69 --- /dev/null +++ b/arch/mips/sibyte/swarm/dbg_io.c @@ -0,0 +1,76 @@ +/* + * kgdb debug routines for SiByte boards. + * + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +/* -------------------- BEGINNING OF CONFIG --------------------- */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * We use the second serial port for kgdb traffic. + * 115200, 8, N, 1. + */ + +#define BAUD_RATE 115200 +#define CLK_DIVISOR V_DUART_BAUD_RATE(BAUD_RATE) +#define DATA_BITS V_DUART_BITS_PER_CHAR_8 /* or 7 */ +#define PARITY V_DUART_PARITY_MODE_NONE /* or even */ +#define STOP_BITS M_DUART_STOP_BIT_LEN_1 /* or 2 */ + +static int duart_initialized = 0; /* 0: need to be init'ed by kgdb */ + +/* -------------------- END OF CONFIG --------------------- */ +extern int kgdb_port; + +#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg))) +#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg))) + +void putDebugChar(unsigned char c); +unsigned char getDebugChar(void); +static void +duart_init(int clk_divisor, int data, int parity, int stop) +{ + duart_out(R_DUART_MODE_REG_1, data | parity); + duart_out(R_DUART_MODE_REG_2, stop); + duart_out(R_DUART_CLK_SEL, clk_divisor); + + duart_out(R_DUART_CMD, M_DUART_RX_EN | M_DUART_TX_EN); /* enable rx and tx */ +} + +void +putDebugChar(unsigned char c) +{ + if (!duart_initialized) { + duart_initialized = 1; + duart_init(CLK_DIVISOR, DATA_BITS, PARITY, STOP_BITS); + } + while ((duart_in(R_DUART_STATUS) & M_DUART_TX_RDY) == 0); + duart_out(R_DUART_TX_HOLD, c); +} + +unsigned char +getDebugChar(void) +{ + if (!duart_initialized) { + duart_initialized = 1; + duart_init(CLK_DIVISOR, DATA_BITS, PARITY, STOP_BITS); + } + while ((duart_in(R_DUART_STATUS) & M_DUART_RX_RDY) == 0) ; + return duart_in(R_DUART_RX_HOLD); +} + diff --git a/arch/mips/sibyte/swarm/rtc_m41t81.c b/arch/mips/sibyte/swarm/rtc_m41t81.c new file mode 100644 index 000000000000..0e633ee8d83c --- /dev/null +++ b/arch/mips/sibyte/swarm/rtc_m41t81.c @@ -0,0 +1,224 @@ +/* + * Copyright (C) 2000, 2001 Broadcom Corporation + * + * Copyright (C) 2002 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + + +/* M41T81 definitions */ + +/* + * Register bits + */ + +#define M41T81REG_SC_ST 0x80 /* stop bit */ +#define M41T81REG_HR_CB 0x40 /* century bit */ +#define M41T81REG_HR_CEB 0x80 /* century enable bit */ +#define M41T81REG_CTL_S 0x20 /* sign bit */ +#define M41T81REG_CTL_FT 0x40 /* frequency test bit */ +#define M41T81REG_CTL_OUT 0x80 /* output level */ +#define M41T81REG_WD_RB0 0x01 /* watchdog resolution bit 0 */ +#define M41T81REG_WD_RB1 0x02 /* watchdog resolution bit 1 */ +#define M41T81REG_WD_BMB0 0x04 /* watchdog multiplier bit 0 */ +#define M41T81REG_WD_BMB1 0x08 /* watchdog multiplier bit 1 */ +#define M41T81REG_WD_BMB2 0x10 /* watchdog multiplier bit 2 */ +#define M41T81REG_WD_BMB3 0x20 /* watchdog multiplier bit 3 */ +#define M41T81REG_WD_BMB4 0x40 /* watchdog multiplier bit 4 */ +#define M41T81REG_AMO_ABE 0x20 /* alarm in "battery back-up mode" enable bit */ +#define M41T81REG_AMO_SQWE 0x40 /* square wave enable */ +#define M41T81REG_AMO_AFE 0x80 /* alarm flag enable flag */ +#define M41T81REG_ADT_RPT5 0x40 /* alarm repeat mode bit 5 */ +#define M41T81REG_ADT_RPT4 0x80 /* alarm repeat mode bit 4 */ +#define M41T81REG_AHR_RPT3 0x80 /* alarm repeat mode bit 3 */ +#define M41T81REG_AHR_HT 0x40 /* halt update bit */ +#define M41T81REG_AMN_RPT2 0x80 /* alarm repeat mode bit 2 */ +#define M41T81REG_ASC_RPT1 0x80 /* alarm repeat mode bit 1 */ +#define M41T81REG_FLG_AF 0x40 /* alarm flag (read only) */ +#define M41T81REG_FLG_WDF 0x80 /* watchdog flag (read only) */ +#define M41T81REG_SQW_RS0 0x10 /* sqw frequency bit 0 */ +#define M41T81REG_SQW_RS1 0x20 /* sqw frequency bit 1 */ +#define M41T81REG_SQW_RS2 0x40 /* sqw frequency bit 2 */ +#define M41T81REG_SQW_RS3 0x80 /* sqw frequency bit 3 */ + + +/* + * Register numbers + */ + +#define M41T81REG_TSC 0x00 /* tenths/hundredths of second */ +#define M41T81REG_SC 0x01 /* seconds */ +#define M41T81REG_MN 0x02 /* minute */ +#define M41T81REG_HR 0x03 /* hour/century */ +#define M41T81REG_DY 0x04 /* day of week */ +#define M41T81REG_DT 0x05 /* date of month */ +#define M41T81REG_MO 0x06 /* month */ +#define M41T81REG_YR 0x07 /* year */ +#define M41T81REG_CTL 0x08 /* control */ +#define M41T81REG_WD 0x09 /* watchdog */ +#define M41T81REG_AMO 0x0A /* alarm: month */ +#define M41T81REG_ADT 0x0B /* alarm: date */ +#define M41T81REG_AHR 0x0C /* alarm: hour */ +#define M41T81REG_AMN 0x0D /* alarm: minute */ +#define M41T81REG_ASC 0x0E /* alarm: second */ +#define M41T81REG_FLG 0x0F /* flags */ +#define M41T81REG_SQW 0x13 /* square wave register */ + +#define M41T81_CCR_ADDRESS 0x68 +#define SMB_CSR(reg) ((u8 *) (IOADDR(A_SMB_REGISTER(1, reg)))) + +static int m41t81_read(uint8_t addr) +{ + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + bus_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); + bus_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE), + SMB_CSR(R_SMB_START)); + + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + bus_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), + SMB_CSR(R_SMB_START)); + + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + /* Clear error bit by writing a 1 */ + bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + return -1; + } + + return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff); +} + +static int m41t81_write(uint8_t addr, int b) +{ + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + bus_writeq((addr & 0xFF), SMB_CSR(R_SMB_CMD)); + bus_writeq((b & 0xff), SMB_CSR(R_SMB_DATA)); + bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, + SMB_CSR(R_SMB_START)); + + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + /* Clear error bit by writing a 1 */ + bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + return -1; + } + + /* read the same byte again to make sure it is written */ + bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, + SMB_CSR(R_SMB_START)); + + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + return 0; +} + +int m41t81_set_time(unsigned long t) +{ + struct rtc_time tm; + + to_tm(t, &tm); + + /* + * Note the write order matters as it ensures the correctness. + * When we write sec, 10th sec is clear. It is reasonable to + * believe we should finish writing min within a second. + */ + + tm.tm_sec = BIN2BCD(tm.tm_sec); + m41t81_write(M41T81REG_SC, tm.tm_sec); + + tm.tm_min = BIN2BCD(tm.tm_min); + m41t81_write(M41T81REG_MN, tm.tm_min); + + tm.tm_hour = BIN2BCD(tm.tm_hour); + tm.tm_hour = (tm.tm_hour & 0x3f) | (m41t81_read(M41T81REG_HR) & 0xc0); + m41t81_write(M41T81REG_HR, tm.tm_hour); + + /* tm_wday starts from 0 to 6 */ + if (tm.tm_wday == 0) tm.tm_wday = 7; + tm.tm_wday = BIN2BCD(tm.tm_wday); + m41t81_write(M41T81REG_DY, tm.tm_wday); + + tm.tm_mday = BIN2BCD(tm.tm_mday); + m41t81_write(M41T81REG_DT, tm.tm_mday); + + /* tm_mon starts from 0, *ick* */ + tm.tm_mon ++; + tm.tm_mon = BIN2BCD(tm.tm_mon); + m41t81_write(M41T81REG_MO, tm.tm_mon); + + /* we don't do century, everything is beyond 2000 */ + tm.tm_year %= 100; + tm.tm_year = BIN2BCD(tm.tm_year); + m41t81_write(M41T81REG_YR, tm.tm_year); + + return 0; +} + +unsigned long m41t81_get_time(void) +{ + unsigned int year, mon, day, hour, min, sec; + + /* + * min is valid if two reads of sec are the same. + */ + for (;;) { + sec = m41t81_read(M41T81REG_SC); + min = m41t81_read(M41T81REG_MN); + if (sec == m41t81_read(M41T81REG_SC)) break; + } + hour = m41t81_read(M41T81REG_HR) & 0x3f; + day = m41t81_read(M41T81REG_DT); + mon = m41t81_read(M41T81REG_MO); + year = m41t81_read(M41T81REG_YR); + + sec = BCD2BIN(sec); + min = BCD2BIN(min); + hour = BCD2BIN(hour); + day = BCD2BIN(day); + mon = BCD2BIN(mon); + year = BCD2BIN(year); + + year += 2000; + + return mktime(year, mon, day, hour, min, sec); +} + +int m41t81_probe(void) +{ + unsigned int tmp; + + /* enable chip if it is not enabled yet */ + tmp = m41t81_read(M41T81REG_SC); + m41t81_write(M41T81REG_SC, tmp & 0x7f); + + return (m41t81_read(M41T81REG_SC) != -1); +} diff --git a/arch/mips/sibyte/swarm/rtc_xicor1241.c b/arch/mips/sibyte/swarm/rtc_xicor1241.c new file mode 100644 index 000000000000..981d21f16e64 --- /dev/null +++ b/arch/mips/sibyte/swarm/rtc_xicor1241.c @@ -0,0 +1,203 @@ +/* + * Copyright (C) 2000, 2001 Broadcom Corporation + * + * Copyright (C) 2002 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + + +/* Xicor 1241 definitions */ + +/* + * Register bits + */ + +#define X1241REG_SR_BAT 0x80 /* currently on battery power */ +#define X1241REG_SR_RWEL 0x04 /* r/w latch is enabled, can write RTC */ +#define X1241REG_SR_WEL 0x02 /* r/w latch is unlocked, can enable r/w now */ +#define X1241REG_SR_RTCF 0x01 /* clock failed */ +#define X1241REG_BL_BP2 0x80 /* block protect 2 */ +#define X1241REG_BL_BP1 0x40 /* block protect 1 */ +#define X1241REG_BL_BP0 0x20 /* block protect 0 */ +#define X1241REG_BL_WD1 0x10 +#define X1241REG_BL_WD0 0x08 +#define X1241REG_HR_MIL 0x80 /* military time format */ + +/* + * Register numbers + */ + +#define X1241REG_BL 0x10 /* block protect bits */ +#define X1241REG_INT 0x11 /* */ +#define X1241REG_SC 0x30 /* Seconds */ +#define X1241REG_MN 0x31 /* Minutes */ +#define X1241REG_HR 0x32 /* Hours */ +#define X1241REG_DT 0x33 /* Day of month */ +#define X1241REG_MO 0x34 /* Month */ +#define X1241REG_YR 0x35 /* Year */ +#define X1241REG_DW 0x36 /* Day of Week */ +#define X1241REG_Y2K 0x37 /* Year 2K */ +#define X1241REG_SR 0x3F /* Status register */ + +#define X1241_CCR_ADDRESS 0x6F + +#define SMB_CSR(reg) ((u8 *) (IOADDR(A_SMB_REGISTER(1, reg)))) + +static int xicor_read(uint8_t addr) +{ + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + bus_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); + bus_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA)); + bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE), + SMB_CSR(R_SMB_START)); + + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), + SMB_CSR(R_SMB_START)); + + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + /* Clear error bit by writing a 1 */ + bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + return -1; + } + + return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff); +} + +static int xicor_write(uint8_t addr, int b) +{ + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + bus_writeq(addr, SMB_CSR(R_SMB_CMD)); + bus_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); + bus_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, + SMB_CSR(R_SMB_START)); + + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + /* Clear error bit by writing a 1 */ + bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + return -1; + } else { + return 0; + } +} + +int xicor_set_time(unsigned long t) +{ + struct rtc_time tm; + int tmp; + + to_tm(t, &tm); + + /* unlock writes to the CCR */ + xicor_write(X1241REG_SR, X1241REG_SR_WEL); + xicor_write(X1241REG_SR, X1241REG_SR_WEL | X1241REG_SR_RWEL); + + /* trivial ones */ + tm.tm_sec = BIN2BCD(tm.tm_sec); + xicor_write(X1241REG_SC, tm.tm_sec); + + tm.tm_min = BIN2BCD(tm.tm_min); + xicor_write(X1241REG_MN, tm.tm_min); + + tm.tm_mday = BIN2BCD(tm.tm_mday); + xicor_write(X1241REG_DT, tm.tm_mday); + + /* tm_mon starts from 0, *ick* */ + tm.tm_mon ++; + tm.tm_mon = BIN2BCD(tm.tm_mon); + xicor_write(X1241REG_MO, tm.tm_mon); + + /* year is split */ + tmp = tm.tm_year / 100; + tm.tm_year %= 100; + xicor_write(X1241REG_YR, tm.tm_year); + xicor_write(X1241REG_Y2K, tmp); + + /* hour is the most tricky one */ + tmp = xicor_read(X1241REG_HR); + if (tmp & X1241REG_HR_MIL) { + /* 24 hour format */ + tm.tm_hour = BIN2BCD(tm.tm_hour); + tmp = (tmp & ~0x3f) | (tm.tm_hour & 0x3f); + } else { + /* 12 hour format, with 0x2 for pm */ + tmp = tmp & ~0x3f; + if (tm.tm_hour >= 12) { + tmp |= 0x20; + tm.tm_hour -= 12; + } + tm.tm_hour = BIN2BCD(tm.tm_hour); + tmp |= tm.tm_hour; + } + xicor_write(X1241REG_HR, tmp); + + xicor_write(X1241REG_SR, 0); + + return 0; +} + +unsigned long xicor_get_time(void) +{ + unsigned int year, mon, day, hour, min, sec, y2k; + + sec = xicor_read(X1241REG_SC); + min = xicor_read(X1241REG_MN); + hour = xicor_read(X1241REG_HR); + + if (hour & X1241REG_HR_MIL) { + hour &= 0x3f; + } else { + if (hour & 0x20) + hour = (hour & 0xf) + 0x12; + } + + day = xicor_read(X1241REG_DT); + mon = xicor_read(X1241REG_MO); + year = xicor_read(X1241REG_YR); + y2k = xicor_read(X1241REG_Y2K); + + sec = BCD2BIN(sec); + min = BCD2BIN(min); + hour = BCD2BIN(hour); + day = BCD2BIN(day); + mon = BCD2BIN(mon); + year = BCD2BIN(year); + y2k = BCD2BIN(y2k); + + year += (y2k * 100); + + return mktime(year, mon, day, hour, min, sec); +} + +int xicor_probe(void) +{ + return (xicor_read(X1241REG_SC) != -1); +} diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c new file mode 100644 index 000000000000..457aeb7be858 --- /dev/null +++ b/arch/mips/sibyte/swarm/setup.c @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation + * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* + * Setup code for the SWARM board + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern void sb1250_setup(void); + +extern int xicor_probe(void); +extern int xicor_set_time(unsigned long); +extern unsigned long xicor_get_time(void); + +extern int m41t81_probe(void); +extern int m41t81_set_time(unsigned long); +extern unsigned long m41t81_get_time(void); + +const char *get_system_type(void) +{ + return "SiByte " SIBYTE_BOARD_NAME; +} + +void __init swarm_timer_setup(struct irqaction *irq) +{ + /* + * we don't set up irqaction, because we will deliver timer + * interrupts through low-level (direct) meachanism. + */ + + /* We only need to setup the generic timer */ + sb1250_time_init(); +} + +int swarm_be_handler(struct pt_regs *regs, int is_fixup) +{ + if (!is_fixup && (regs->cp0_cause & 4)) { + /* Data bus error - print PA */ +#ifdef CONFIG_MIPS64 + printk("DBE physical address: %010lx\n", + __read_64bit_c0_register($26, 1)); +#else + printk("DBE physical address: %010llx\n", + __read_64bit_c0_split($26, 1)); +#endif + } + return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL); +} + +static int __init swarm_setup(void) +{ + sb1250_setup(); + + panic_timeout = 5; /* For debug. */ + + board_timer_setup = swarm_timer_setup; + board_be_handler = swarm_be_handler; + + if (xicor_probe()) { + printk("swarm setup: Xicor 1241 RTC detected.\n"); + rtc_get_time = xicor_get_time; + rtc_set_time = xicor_set_time; + } + + if (m41t81_probe()) { + printk("swarm setup: M41T81 RTC detected.\n"); + rtc_get_time = m41t81_get_time; + rtc_set_time = m41t81_set_time; + } + + printk("This kernel optimized for " +#ifdef CONFIG_SIMULATION + "simulation" +#else + "board" +#endif + " runs " +#ifdef CONFIG_SIBYTE_CFE + "with" +#else + "without" +#endif + " CFE\n"); + +#ifdef CONFIG_VT + screen_info = (struct screen_info) { + 0, 0, /* orig-x, orig-y */ + 0, /* unused */ + 52, /* orig_video_page */ + 3, /* orig_video_mode */ + 80, /* orig_video_cols */ + 4626, 3, 9, /* unused, ega_bx, unused */ + 25, /* orig_video_lines */ + 0x22, /* orig_video_isVGA */ + 16 /* orig_video_points */ + }; + /* XXXKW for CFE, get lines/cols from environment */ +#endif + + return 0; +} + +early_initcall(swarm_setup); + +#ifdef LEDS_PHYS + +#ifdef CONFIG_SIBYTE_CARMEL +/* XXXKW need to detect Monterey/LittleSur/etc */ +#undef LEDS_PHYS +#define LEDS_PHYS MLEDS_PHYS +#endif + +#define setled(index, c) \ + ((unsigned char *)(IOADDR(LEDS_PHYS)+0x20))[(3-(index))<<3] = (c) +void setleds(char *str) +{ + int i; + for (i = 0; i < 4; i++) { + if (!str[i]) { + setled(i, ' '); + } else { + setled(i, str[i]); + } + } +} +#endif diff --git a/arch/mips/sibyte/swarm/time.c b/arch/mips/sibyte/swarm/time.c new file mode 100644 index 000000000000..c1f1a9defeeb --- /dev/null +++ b/arch/mips/sibyte/swarm/time.c @@ -0,0 +1,244 @@ +/* + * Copyright (C) 2000, 2001 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* + * Time routines for the swarm board. We pass all the hard stuff + * through to the sb1250 handling code. Only thing we really keep + * track of here is what time of day we think it is. And we don't + * really even do a good job of that... + */ + + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +static unsigned long long sec_bias = 0; +static unsigned int usec_bias = 0; + +/* Xicor 1241 definitions */ + +/* + * Register bits + */ + +#define X1241REG_SR_BAT 0x80 /* currently on battery power */ +#define X1241REG_SR_RWEL 0x04 /* r/w latch is enabled, can write RTC */ +#define X1241REG_SR_WEL 0x02 /* r/w latch is unlocked, can enable r/w now */ +#define X1241REG_SR_RTCF 0x01 /* clock failed */ +#define X1241REG_BL_BP2 0x80 /* block protect 2 */ +#define X1241REG_BL_BP1 0x40 /* block protect 1 */ +#define X1241REG_BL_BP0 0x20 /* block protect 0 */ +#define X1241REG_BL_WD1 0x10 +#define X1241REG_BL_WD0 0x08 +#define X1241REG_HR_MIL 0x80 /* military time format */ + +/* + * Register numbers + */ + +#define X1241REG_BL 0x10 /* block protect bits */ +#define X1241REG_INT 0x11 /* */ +#define X1241REG_SC 0x30 /* Seconds */ +#define X1241REG_MN 0x31 /* Minutes */ +#define X1241REG_HR 0x32 /* Hours */ +#define X1241REG_DT 0x33 /* Day of month */ +#define X1241REG_MO 0x34 /* Month */ +#define X1241REG_YR 0x35 /* Year */ +#define X1241REG_DW 0x36 /* Day of Week */ +#define X1241REG_Y2K 0x37 /* Year 2K */ +#define X1241REG_SR 0x3F /* Status register */ + +#define X1241_CCR_ADDRESS 0x6F + +#define SMB_CSR(reg) (IOADDR(A_SMB_REGISTER(1, reg))) + +static int xicor_read(uint8_t addr) +{ + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + bus_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); + bus_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA)); + bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE), + SMB_CSR(R_SMB_START)); + + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), + SMB_CSR(R_SMB_START)); + + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + /* Clear error bit by writing a 1 */ + bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + return -1; + } + + return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff); +} + +static int xicor_write(uint8_t addr, int b) +{ + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + bus_writeq(addr, SMB_CSR(R_SMB_CMD)); + bus_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); + bus_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, + SMB_CSR(R_SMB_START)); + + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + /* Clear error bit by writing a 1 */ + bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + return -1; + } else { + return 0; + } +} + +/* + * In order to set the CMOS clock precisely, set_rtc_mmss has to be + * called 500 ms after the second nowtime has started, because when + * nowtime is written into the registers of the CMOS clock, it will + * jump to the next second precisely 500 ms later. Check the Motorola + * MC146818A or Dallas DS12887 data sheet for details. + * + * BUG: This routine does not handle hour overflow properly; it just + * sets the minutes. Usually you'll only notice that after reboot! + */ +int set_rtc_mmss(unsigned long nowtime) +{ + int retval = 0; + int real_seconds, real_minutes, cmos_minutes; + + cmos_minutes = xicor_read(X1241REG_MN); + cmos_minutes = BCD2BIN(cmos_minutes); + + /* + * since we're only adjusting minutes and seconds, + * don't interfere with hour overflow. This avoids + * messing with unknown time zones but requires your + * RTC not to be off by more than 15 minutes + */ + real_seconds = nowtime % 60; + real_minutes = nowtime / 60; + if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) + real_minutes += 30; /* correct for half hour time zone */ + real_minutes %= 60; + + /* unlock writes to the CCR */ + xicor_write(X1241REG_SR, X1241REG_SR_WEL); + xicor_write(X1241REG_SR, X1241REG_SR_WEL | X1241REG_SR_RWEL); + + if (abs(real_minutes - cmos_minutes) < 30) { + real_seconds = BIN2BCD(real_seconds); + real_minutes = BIN2BCD(real_minutes); + xicor_write(X1241REG_SC, real_seconds); + xicor_write(X1241REG_MN, real_minutes); + } else { + printk(KERN_WARNING + "set_rtc_mmss: can't update from %d to %d\n", + cmos_minutes, real_minutes); + retval = -1; + } + + xicor_write(X1241REG_SR, 0); + + printk("set_rtc_mmss: %02d:%02d\n", real_minutes, real_seconds); + + return retval; +} + +static unsigned long __init get_swarm_time(void) +{ + unsigned int year, mon, day, hour, min, sec, y2k; + + sec = xicor_read(X1241REG_SC); + min = xicor_read(X1241REG_MN); + hour = xicor_read(X1241REG_HR); + + if (hour & X1241REG_HR_MIL) { + hour &= 0x3f; + } else { + if (hour & 0x20) + hour = (hour & 0xf) + 0x12; + } + + sec = BCD2BIN(sec); + min = BCD2BIN(min); + hour = BCD2BIN(hour); + + day = xicor_read(X1241REG_DT); + mon = xicor_read(X1241REG_MO); + year = xicor_read(X1241REG_YR); + y2k = xicor_read(X1241REG_Y2K); + + day = BCD2BIN(day); + mon = BCD2BIN(mon); + year = BCD2BIN(year); + y2k = BCD2BIN(y2k); + + year += (y2k * 100); + + return mktime(year, mon, day, hour, min, sec); +} + +/* + * Bring up the timer at 100 Hz. + */ +void __init swarm_time_init(void) +{ + unsigned int flags; + int status; + + /* Set up the scd general purpose timer 0 to cpu 0 */ + sb1250_time_init(); + + /* Establish communication with the Xicor 1241 RTC */ + /* XXXKW how do I share the SMBus with the I2C subsystem? */ + + bus_writeq(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ)); + bus_writeq(0, SMB_CSR(R_SMB_CONTROL)); + + if ((status = xicor_read(X1241REG_SR_RTCF)) < 0) { + printk("x1241: couldn't detect on SWARM SMBus 1\n"); + } else { + if (status & X1241REG_SR_RTCF) + printk("x1241: battery failed -- time is probably wrong\n"); + write_seqlock_irqsave(&xtime_lock, flags); + xtime.tv_sec = get_swarm_time(); + xtime.tv_nsec = 0; + write_sequnlock_irqrestore(&xtime_lock, flags); + } +} -- cgit v1.2.2