From 7bcf7717b6a047c272410d0cd00213185fe6b99d Mon Sep 17 00:00:00 2001
From: Ralf Baechle <ralf@linux-mips.org>
Date: Thu, 11 Oct 2007 23:46:09 +0100
Subject: [MIPS] Implement clockevents for R4000-style cp0 count/compare
 interrupt

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
 arch/mips/qemu/q-irq.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'arch/mips/qemu/q-irq.c')

diff --git a/arch/mips/qemu/q-irq.c b/arch/mips/qemu/q-irq.c
index 89891e984b3b..4681757460a1 100644
--- a/arch/mips/qemu/q-irq.c
+++ b/arch/mips/qemu/q-irq.c
@@ -2,6 +2,7 @@
 #include <linux/linkage.h>
 
 #include <asm/i8259.h>
+#include <asm/irq_cpu.h>
 #include <asm/mipsregs.h>
 #include <asm/qemu.h>
 #include <asm/system.h>
@@ -12,7 +13,7 @@ asmlinkage void plat_irq_dispatch(void)
 	unsigned int pending = read_c0_status() & read_c0_cause();
 
 	if (pending & 0x8000) {
-		ll_timer_interrupt(Q_COUNT_COMPARE_IRQ);
+		do_IRQ(Q_COUNT_COMPARE_IRQ);
 		return;
 	}
 	if (pending & 0x0400) {
@@ -29,6 +30,7 @@ void __init arch_init_irq(void)
 {
 	mips_hpt_frequency = QEMU_C0_COUNTER_CLOCK;		/* 100MHz */
 
+	mips_cpu_irq_init();
 	init_i8259_irqs();
 	set_c0_status(0x8400);
 }
-- 
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