From 93373ed4d87fb02554ce020d929388ac16913664 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sat, 1 Apr 2006 21:17:45 +0100 Subject: [MIPS] Rewrite spurious_interrupt from assembler to C. Signed-off-by: Ralf Baechle --- arch/mips/momentum/ocelot_3/int-handler.S | 4 +++- arch/mips/momentum/ocelot_c/int-handler.S | 3 ++- 2 files changed, 5 insertions(+), 2 deletions(-) (limited to 'arch/mips/momentum') diff --git a/arch/mips/momentum/ocelot_3/int-handler.S b/arch/mips/momentum/ocelot_3/int-handler.S index 4522f09ed769..b1207262984a 100644 --- a/arch/mips/momentum/ocelot_3/int-handler.S +++ b/arch/mips/momentum/ocelot_3/int-handler.S @@ -78,8 +78,10 @@ .set reorder /* wrong alarm or masked ... */ - j spurious_interrupt + jal spurious_interrupt nop + j ret_from_irq + nop END(ocelot3_handle_int) .align 5 diff --git a/arch/mips/momentum/ocelot_c/int-handler.S b/arch/mips/momentum/ocelot_c/int-handler.S index 52349d9bf1be..f77834193c3c 100644 --- a/arch/mips/momentum/ocelot_c/int-handler.S +++ b/arch/mips/momentum/ocelot_c/int-handler.S @@ -52,8 +52,9 @@ .set reorder /* wrong alarm or masked ... */ - j spurious_interrupt + jal spurious_interrupt nop + j ret_from_irq END(ocelot_handle_int) .align 5 -- cgit v1.2.2 From b56bce9a25e8c117794fe74c1b9bf790de10d554 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sun, 2 Apr 2006 13:16:45 +0100 Subject: [MIPS] Jaguar: Fix build errors after the recent move of Marvell headers. Some things were renamed because the PPC variant of the MV-643XX now uses the same header and the Jaguar code didn't catch up on that. Signed-off-by: Ralf Baechle --- arch/mips/momentum/jaguar_atx/setup.c | 36 +++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) (limited to 'arch/mips/momentum') diff --git a/arch/mips/momentum/jaguar_atx/setup.c b/arch/mips/momentum/jaguar_atx/setup.c index 91d9637143d7..1379c76845dc 100644 --- a/arch/mips/momentum/jaguar_atx/setup.c +++ b/arch/mips/momentum/jaguar_atx/setup.c @@ -381,24 +381,24 @@ void __init plat_setup(void) * shut down ethernet ports, just to be sure our memory doesn't get * corrupted by random ethernet traffic. */ - MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8); - MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8); - MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(2), 0xff << 8); - MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8); - MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8); - MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0xff << 8); - while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff); - while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff); - while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(2)) & 0xff); - while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff); - while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff); - while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(2)) & 0xff); - MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0), - MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1); - MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1), - MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1); - MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(2), - MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(2)) & ~1); + MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8); + MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8); + MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2), 0xff << 8); + MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8); + MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8); + MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0xff << 8); + while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff); + while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff); + while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2)) & 0xff); + while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff); + while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff); + while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2)) & 0xff); + MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0), + MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1); + MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1), + MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1); + MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2), + MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2)) & ~1); /* Turn off the Bit-Error LED */ JAGUAR_FPGA_WRITE(0x80, CLR); -- cgit v1.2.2 From c40b92e09c029ef2cb0b2287cbd222ff14ae3de8 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sun, 2 Apr 2006 18:43:09 +0100 Subject: [MIPS] Ocelot 3: Fix build errors after the recent move of Marvell headers. Signed-off-by: Ralf Baechle --- arch/mips/momentum/ocelot_3/setup.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'arch/mips/momentum') diff --git a/arch/mips/momentum/ocelot_3/setup.c b/arch/mips/momentum/ocelot_3/setup.c index 370e75d0e75c..c69195234309 100644 --- a/arch/mips/momentum/ocelot_3/setup.c +++ b/arch/mips/momentum/ocelot_3/setup.c @@ -329,22 +329,22 @@ void __init plat_setup(void) /* shut down ethernet ports, just to be sure our memory doesn't get * corrupted by random ethernet traffic. */ - MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8); - MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8); - MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8); - MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8); + MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8); + MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8); + MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8); + MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8); do {} - while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff); + while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff); do {} - while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff); + while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff); do {} - while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff); + while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff); do {} - while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff); - MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0), - MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1); - MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1), - MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1); + while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff); + MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0), + MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1); + MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1), + MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1); /* Turn off the Bit-Error LED */ OCELOT_FPGA_WRITE(0x80, CLR); -- cgit v1.2.2 From e4ac58afdfac792c0583af30dbd9eae53e24c78b Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 3 Apr 2006 17:56:36 +0100 Subject: [MIPS] Rewrite all the assembler interrupt handlers to C. Saves like 1,600 lines of code, is way easier to debug, compilers frequently do a better job than the cut and paste type of handlers many boards had. And finally having all the stuff done in a single place also means alot of bug potencial for the MT ASE is gone. The only surviving handler in assembler is the DECstation one; I hope Maciej will rewrite it. Signed-off-by: Ralf Baechle --- arch/mips/momentum/jaguar_atx/Makefile | 2 +- arch/mips/momentum/jaguar_atx/int-handler.S | 128 ------------------------- arch/mips/momentum/jaguar_atx/irq.c | 35 ++++++- arch/mips/momentum/ocelot_3/Makefile | 2 +- arch/mips/momentum/ocelot_3/int-handler.S | 139 ---------------------------- arch/mips/momentum/ocelot_3/irq.c | 38 +++++++- arch/mips/momentum/ocelot_c/Makefile | 2 +- arch/mips/momentum/ocelot_c/int-handler.S | 103 --------------------- arch/mips/momentum/ocelot_c/irq.c | 30 +++++- arch/mips/momentum/ocelot_g/Makefile | 2 +- arch/mips/momentum/ocelot_g/int-handler.S | 131 -------------------------- arch/mips/momentum/ocelot_g/irq.c | 38 +++++++- 12 files changed, 130 insertions(+), 520 deletions(-) delete mode 100644 arch/mips/momentum/jaguar_atx/int-handler.S delete mode 100644 arch/mips/momentum/ocelot_3/int-handler.S delete mode 100644 arch/mips/momentum/ocelot_c/int-handler.S delete mode 100644 arch/mips/momentum/ocelot_g/int-handler.S (limited to 'arch/mips/momentum') diff --git a/arch/mips/momentum/jaguar_atx/Makefile b/arch/mips/momentum/jaguar_atx/Makefile index 20bbd3ea44a8..67372f3f9654 100644 --- a/arch/mips/momentum/jaguar_atx/Makefile +++ b/arch/mips/momentum/jaguar_atx/Makefile @@ -6,7 +6,7 @@ # unless it's something special (ie not a .c file). # -obj-y += int-handler.o irq.o prom.o reset.o setup.o +obj-y += irq.o prom.o reset.o setup.o obj-$(CONFIG_SERIAL_8250_CONSOLE) += ja-console.o obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o diff --git a/arch/mips/momentum/jaguar_atx/int-handler.S b/arch/mips/momentum/jaguar_atx/int-handler.S deleted file mode 100644 index 55bc789733f2..000000000000 --- a/arch/mips/momentum/jaguar_atx/int-handler.S +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright 2002 Momentum Computer Inc. - * Author: Matthew Dharm - * - * Based on work: - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * First-level interrupt dispatcher for Jaguar-ATX board. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include -#include -#include - -/* - * First level interrupt dispatcher for Ocelot-CS board - */ - .align 5 - NESTED(jaguar_handle_int, PT_SIZE, sp) - SAVE_ALL - CLI - .set at - mfc0 t0, CP0_CAUSE - mfc0 t2, CP0_STATUS - - and t0, t2 - - andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */ - bnez t1, ll_sw0_irq - andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */ - bnez t1, ll_sw1_irq - andi t1, t0, STATUSF_IP2 /* int0 hardware line */ - bnez t1, ll_pcixa_irq - andi t1, t0, STATUSF_IP3 /* int1 hardware line */ - bnez t1, ll_pcixb_irq - andi t1, t0, STATUSF_IP4 /* int2 hardware line */ - bnez t1, ll_pcia_irq - andi t1, t0, STATUSF_IP5 /* int3 hardware line */ - bnez t1, ll_pcib_irq - andi t1, t0, STATUSF_IP6 /* int4 hardware line */ - bnez t1, ll_uart_irq - andi t1, t0, STATUSF_IP7 /* cpu timer */ - bnez t1, ll_cputimer_irq - - nop - nop - - /* now look at extended interrupts */ - mfc0 t0, CP0_CAUSE - cfc0 t1, CP0_S1_INTCONTROL - - /* shift the mask 8 bits left to line up the bits */ - sll t2, t1, 8 - - and t0, t2 - srl t0, t0, 16 - - andi t1, t0, STATUSF_IP8 /* int6 hardware line */ - bnez t1, ll_mv64340_decode_irq - - nop - nop - - .set reorder - - /* wrong alarm or masked ... */ - j spurious_interrupt - nop - END(jaguar_handle_int) - - .align 5 -ll_sw0_irq: - li a0, 0 - move a1, sp - jal do_IRQ - j ret_from_irq -ll_sw1_irq: - li a0, 1 - move a1, sp - jal do_IRQ - j ret_from_irq -ll_pcixa_irq: - li a0, 2 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_pcixb_irq: - li a0, 3 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_pcia_irq: - li a0, 4 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_pcib_irq: - li a0, 5 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_uart_irq: - li a0, 6 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cputimer_irq: - li a0, 7 - move a1, sp - jal ll_timer_interrupt - j ret_from_irq - -ll_mv64340_decode_irq: - move a0, sp - jal ll_mv64340_irq - j ret_from_irq diff --git a/arch/mips/momentum/jaguar_atx/irq.c b/arch/mips/momentum/jaguar_atx/irq.c index 15588f91ace2..ec4032b38f19 100644 --- a/arch/mips/momentum/jaguar_atx/irq.c +++ b/arch/mips/momentum/jaguar_atx/irq.c @@ -10,7 +10,7 @@ * Copyright 2001 MontaVista Software Inc. * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net * - * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 2000, 01, 06 Ralf Baechle (ralf@linux-mips.org) * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -38,8 +38,37 @@ #include #include #include +#include -extern asmlinkage void jaguar_handle_int(void); +asmlinkage void plat_irq_dispatch(struct pt_regs *regs) +{ + unsigned int pending = read_c0_cause() & read_c0_status(); + + if (pending & STATUSF_IP0) + do_IRQ(0, regs); + else if (pending & STATUSF_IP1) + do_IRQ(1, regs); + else if (pending & STATUSF_IP2) + do_IRQ(2, regs); + else if (pending & STATUSF_IP3) + do_IRQ(3, regs); + else if (pending & STATUSF_IP4) + do_IRQ(4, regs); + else if (pending & STATUSF_IP5) + do_IRQ(5, regs); + else if (pending & STATUSF_IP6) + do_IRQ(6, regs); + else if (pending & STATUSF_IP7) + ll_timer_interrupt(7, regs); + else { + /* + * Now look at the extended interrupts + */ + pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16; + if (pending & STATUSF_IP8) + ll_mv64340_irq(regs); + } +} static struct irqaction cascade_mv64340 = { no_action, SA_INTERRUPT, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL @@ -53,8 +82,6 @@ void __init arch_init_irq(void) */ clear_c0_status(ST0_IM); - /* Sets the first-level interrupt dispatcher. */ - set_except_vector(0, jaguar_handle_int); mips_cpu_irq_init(0); rm7k_cpu_irq_init(8); diff --git a/arch/mips/momentum/ocelot_3/Makefile b/arch/mips/momentum/ocelot_3/Makefile index aab8fd89f830..8bcea64dd27b 100644 --- a/arch/mips/momentum/ocelot_3/Makefile +++ b/arch/mips/momentum/ocelot_3/Makefile @@ -5,4 +5,4 @@ # removes any old dependencies. DON'T put your own dependencies here # unless it's something special (ie not a .c file). # -obj-y += int-handler.o irq.o prom.o reset.o setup.o +obj-y += irq.o prom.o reset.o setup.o diff --git a/arch/mips/momentum/ocelot_3/int-handler.S b/arch/mips/momentum/ocelot_3/int-handler.S deleted file mode 100644 index b1207262984a..000000000000 --- a/arch/mips/momentum/ocelot_3/int-handler.S +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright 2002 Momentum Computer Inc. - * Author: Matthew Dharm - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright 2004 PMC-Sierra - * Author: Manish Lachwani (lachwani@pmc-sierra.com) - * - * Copyright (C) 2004 MontaVista Software Inc. - * Author: Manish Lachwani, mlachwani@mvista.com - * - * First-level interrupt dispatcher for Ocelot-3 board. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include -#include -#include - -/* - * First level interrupt dispatcher for Ocelot-3 board - */ - .align 5 - NESTED(ocelot3_handle_int, PT_SIZE, sp) - SAVE_ALL - CLI - .set at - - mfc0 t0, CP0_CAUSE - mfc0 t2, CP0_STATUS - - and t0, t2 - - andi t1, t0, STATUSF_IP0 /* sw0 software interrupt (IRQ0) */ - bnez t1, ll_sw0_irq - - andi t1, t0, STATUSF_IP1 /* sw1 software interrupt (IRQ1) */ - bnez t1, ll_sw1_irq - - andi t1, t0, STATUSF_IP2 /* int0 hardware line (IRQ2) */ - bnez t1, ll_pci0slot1_irq - - andi t1, t0, STATUSF_IP3 /* int1 hardware line (IRQ3) */ - bnez t1, ll_pci0slot2_irq - - andi t1, t0, STATUSF_IP4 /* int2 hardware line (IRQ4) */ - bnez t1, ll_pci1slot1_irq - - andi t1, t0, STATUSF_IP5 /* int3 hardware line (IRQ5) */ - bnez t1, ll_pci1slot2_irq - - andi t1, t0, STATUSF_IP6 /* int4 hardware line (IRQ6) */ - bnez t1, ll_uart_irq - - andi t1, t0, STATUSF_IP7 /* cpu timer (IRQ7) */ - bnez t1, ll_cputimer_irq - - /* now look at extended interrupts */ - mfc0 t0, CP0_CAUSE - cfc0 t1, CP0_S1_INTCONTROL - - /* shift the mask 8 bits left to line up the bits */ - sll t2, t1, 8 - - and t0, t2 - srl t0, t0, 16 - - andi t1, t0, STATUSF_IP8 /* int6 hardware line (IRQ9) */ - bnez t1, ll_mv64340_decode_irq - - .set reorder - - /* wrong alarm or masked ... */ - jal spurious_interrupt - nop - j ret_from_irq - nop - END(ocelot3_handle_int) - - .align 5 -ll_sw0_irq: - li a0, 0 /* IRQ 1 */ - move a1, sp - jal do_IRQ - j ret_from_irq -ll_sw1_irq: - li a0, 1 /* IRQ 2 */ - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_pci0slot1_irq: - li a0, 2 /* IRQ 3 */ - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_pci0slot2_irq: - li a0, 3 /* IRQ 4 */ - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_pci1slot1_irq: - li a0, 4 /* IRQ 5 */ - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_pci1slot2_irq: - li a0, 5 /* IRQ 6 */ - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_uart_irq: - li a0, 6 /* IRQ 7 */ - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cputimer_irq: - li a0, 7 /* IRQ 8 */ - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_mv64340_decode_irq: - move a0, sp - jal ll_mv64340_irq - j ret_from_irq - diff --git a/arch/mips/momentum/ocelot_3/irq.c b/arch/mips/momentum/ocelot_3/irq.c index 42464dbd4ad2..87c63c340ae3 100644 --- a/arch/mips/momentum/ocelot_3/irq.c +++ b/arch/mips/momentum/ocelot_3/irq.c @@ -53,8 +53,6 @@ #include #include -extern asmlinkage void ocelot3_handle_int(void); - static struct irqaction cascade_mv64340 = { no_action, SA_INTERRUPT, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL }; @@ -67,9 +65,6 @@ void __init arch_init_irq(void) */ clear_c0_status(ST0_IM | ST0_BEV); - /* Sets the first-level interrupt dispatcher. */ - set_except_vector(0, ocelot3_handle_int); - mips_cpu_irq_init(0); rm7k_cpu_irq_init(8); /* set up the cascading interrupts */ @@ -79,3 +74,36 @@ void __init arch_init_irq(void) set_c0_status(ST0_IM); /* IE in the status register */ } + +asmlinkage void plat_irq_dispatch(struct pt_regs *regs) +{ + unsigned int pending = read_c0_cause() & read_c0_status(); + + if (pending & STATUSF_IP0) + do_IRQ(0, regs); + else if (pending & STATUSF_IP1) + do_IRQ(1, regs); + else if (pending & STATUSF_IP2) + do_IRQ(2, regs); + else if (pending & STATUSF_IP3) + do_IRQ(3, regs); + else if (pending & STATUSF_IP4) + do_IRQ(4, regs); + else if (pending & STATUSF_IP5) + do_IRQ(5, regs); + else if (pending & STATUSF_IP6) + do_IRQ(6, regs); + else if (pending & STATUSF_IP7) + do_IRQ(7, regs); + else { + /* + * Now look at the extended interrupts + */ + pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16; + + if (pending & STATUSF_IP8) + ll_mv64340_irq(regs); + else + spurious_interrupt(regs); + } +} diff --git a/arch/mips/momentum/ocelot_c/Makefile b/arch/mips/momentum/ocelot_c/Makefile index 91240777f978..94802b4db472 100644 --- a/arch/mips/momentum/ocelot_c/Makefile +++ b/arch/mips/momentum/ocelot_c/Makefile @@ -2,7 +2,7 @@ # Makefile for Momentum Computer's Ocelot-C and -CS boards. # -obj-y += cpci-irq.o int-handler.o irq.o prom.o reset.o \ +obj-y += cpci-irq.o irq.o prom.o reset.o \ setup.o uart-irq.o obj-$(CONFIG_KGDB) += dbg_io.o diff --git a/arch/mips/momentum/ocelot_c/int-handler.S b/arch/mips/momentum/ocelot_c/int-handler.S deleted file mode 100644 index f77834193c3c..000000000000 --- a/arch/mips/momentum/ocelot_c/int-handler.S +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright 2002 Momentum Computer Inc. - * Author: Matthew Dharm - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * First-level interrupt dispatcher for Ocelot-CS board. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include -#include -#include -#include "ocelot_c_fpga.h" - -/* - * First level interrupt dispatcher for Ocelot-CS board - */ - .align 5 - NESTED(ocelot_handle_int, PT_SIZE, sp) - SAVE_ALL - CLI - .set at - mfc0 t0, CP0_CAUSE - mfc0 t2, CP0_STATUS - - and t0, t2 - - andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */ - bnez t1, ll_sw0_irq - andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */ - bnez t1, ll_sw1_irq - andi t1, t0, STATUSF_IP2 /* int0 hardware line */ - bnez t1, ll_scsi_irq - andi t1, t0, STATUSF_IP3 /* int1 hardware line */ - bnez t1, ll_uart_decode_irq - andi t1, t0, STATUSF_IP4 /* int2 hardware line */ - bnez t1, ll_pmc_irq - andi t1, t0, STATUSF_IP5 /* int3 hardware line */ - bnez t1, ll_cpci_decode_irq - andi t1, t0, STATUSF_IP6 /* int4 hardware line */ - bnez t1, ll_mv64340_decode_irq - andi t1, t0, STATUSF_IP7 /* cpu timer */ - bnez t1, ll_cputimer_irq - - .set reorder - - /* wrong alarm or masked ... */ - jal spurious_interrupt - nop - j ret_from_irq - END(ocelot_handle_int) - - .align 5 -ll_sw0_irq: - li a0, 0 - move a1, sp - jal do_IRQ - j ret_from_irq -ll_sw1_irq: - li a0, 1 - move a1, sp - jal do_IRQ - j ret_from_irq -ll_scsi_irq: - li a0, 2 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_uart_decode_irq: - move a0, sp - jal ll_uart_irq - j ret_from_irq - -ll_pmc_irq: - li a0, 4 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpci_decode_irq: - move a0, sp - jal ll_cpci_irq - j ret_from_irq - -ll_mv64340_decode_irq: - move a0, sp - jal ll_mv64340_irq - j ret_from_irq - -ll_cputimer_irq: - li a0, 7 - move a1, sp - jal do_IRQ - j ret_from_irq - diff --git a/arch/mips/momentum/ocelot_c/irq.c b/arch/mips/momentum/ocelot_c/irq.c index a5764bc20e36..86f61ce59e53 100644 --- a/arch/mips/momentum/ocelot_c/irq.c +++ b/arch/mips/momentum/ocelot_c/irq.c @@ -48,7 +48,6 @@ #include #include -extern asmlinkage void ocelot_handle_int(void); extern void uart_irq_init(void); extern void cpci_irq_init(void); @@ -60,6 +59,33 @@ static struct irqaction cascade_mv64340 = { no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL }; +extern void ll_uart_irq(struct pt_regs *regs); +extern void ll_cpci_irq(struct pt_regs *regs); + +asmlinkage void plat_irq_dispatch(struct pt_regs *regs) +{ + unsigned int pending = read_c0_cause() & read_c0_status(); + + if (pending & STATUSF_IP0) + do_IRQ(0, regs); + else if (pending & STATUSF_IP1) + do_IRQ(1, regs); + else if (pending & STATUSF_IP2) + do_IRQ(2, regs); + else if (pending & STATUSF_IP3) + ll_uart_irq(regs); + else if (pending & STATUSF_IP4) + do_IRQ(4, regs); + else if (pending & STATUSF_IP5) + ll_cpci_irq(regs); + else if (pending & STATUSF_IP6) + ll_mv64340_irq(regs); + else if (pending & STATUSF_IP7) + do_IRQ(7, regs); + else + spurious_interrupt(regs); +} + void __init arch_init_irq(void) { /* @@ -68,8 +94,6 @@ void __init arch_init_irq(void) */ clear_c0_status(ST0_IM); - /* Sets the first-level interrupt dispatcher. */ - set_except_vector(0, ocelot_handle_int); mips_cpu_irq_init(0); /* set up the cascading interrupts */ diff --git a/arch/mips/momentum/ocelot_g/Makefile b/arch/mips/momentum/ocelot_g/Makefile index e5f1cb086973..adb5665d40a9 100644 --- a/arch/mips/momentum/ocelot_g/Makefile +++ b/arch/mips/momentum/ocelot_g/Makefile @@ -2,7 +2,7 @@ # Makefile for Momentum Computer's Ocelot-G board. # -obj-y += int-handler.o irq.o gt-irq.o prom.o reset.o setup.o +obj-y += irq.o gt-irq.o prom.o reset.o setup.o obj-$(CONFIG_KGDB) += dbg_io.o EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/momentum/ocelot_g/int-handler.S b/arch/mips/momentum/ocelot_g/int-handler.S deleted file mode 100644 index 772e8f713176..000000000000 --- a/arch/mips/momentum/ocelot_g/int-handler.S +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * First-level interrupt dispatcher for ocelot board. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include -#include -#include - -/* - * first level interrupt dispatcher for ocelot board - - * We check for the timer first, then check PCI ints A and D. - * Then check for serial IRQ and fall through. - */ - .align 5 - NESTED(ocelot_handle_int, PT_SIZE, sp) - SAVE_ALL - CLI - .set at - mfc0 t0, CP0_CAUSE - mfc0 t2, CP0_STATUS - - and t0, t2 - - andi t1, t0, STATUSF_IP2 /* int0 hardware line */ - bnez t1, ll_pri_enet_irq - andi t1, t0, STATUSF_IP3 /* int1 hardware line */ - bnez t1, ll_sec_enet_irq - andi t1, t0, STATUSF_IP4 /* int2 hardware line */ - bnez t1, ll_uart_irq - andi t1, t0, STATUSF_IP5 /* int3 hardware line */ - bnez t1, ll_cpci_irq - andi t1, t0, STATUSF_IP6 /* int4 hardware line */ - bnez t1, ll_galileo_p0_irq - andi t1, t0, STATUSF_IP7 /* cpu timer */ - bnez t1, ll_cputimer_irq - - /* now look at the extended interrupts */ - mfc0 t0, CP0_CAUSE - cfc0 t1, CP0_S1_INTCONTROL - - /* shift the mask 8 bits left to line up the bits */ - sll t2, t1, 8 - - and t0, t2 - srl t0, t0, 16 - - andi t1, t0, STATUSF_IP8 /* int6 hardware line */ - bnez t1, ll_galileo_p1_irq - andi t1, t0, STATUSF_IP9 /* int7 hardware line */ - bnez t1, ll_pmc_irq - andi t1, t0, STATUSF_IP10 /* int8 hardware line */ - bnez t1, ll_cpci_abcd_irq - andi t1, t0, STATUSF_IP11 /* int9 hardware line */ - bnez t1, ll_testpoint_irq - - .set reorder - - /* wrong alarm or masked ... */ - j spurious_interrupt - nop - END(ocelot_handle_int) - - .align 5 -ll_pri_enet_irq: - li a0, 2 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_sec_enet_irq: - li a0, 3 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_uart_irq: - li a0, 4 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpci_irq: - li a0, 5 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_galileo_p0_irq: - li a0, 6 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cputimer_irq: - li a0, 7 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_galileo_p1_irq: - li a0, 8 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_pmc_irq: - li a0, 9 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpci_abcd_irq: - li a0, 10 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_testpoint_irq: - li a0, 11 - move a1, sp - jal do_IRQ - j ret_from_irq diff --git a/arch/mips/momentum/ocelot_g/irq.c b/arch/mips/momentum/ocelot_g/irq.c index 5eb85b164205..7a4a419804f1 100644 --- a/arch/mips/momentum/ocelot_g/irq.c +++ b/arch/mips/momentum/ocelot_g/irq.c @@ -48,7 +48,41 @@ #include #include -extern asmlinkage void ocelot_handle_int(void); +asmlinkage void plat_irq_dispatch(struct pt_regs *regs) +{ + unsigned int pending = read_c0_cause() & read_c0_status(); + + if (pending & STATUSF_IP2) + do_IRQ(2, regs); + else if (pending & STATUSF_IP3) + do_IRQ(3, regs); + else if (pending & STATUSF_IP4) + do_IRQ(4, regs); + else if (pending & STATUSF_IP5) + do_IRQ(5, regs); + else if (pending & STATUSF_IP6) + do_IRQ(6, regs); + else if (pending & STATUSF_IP7) + do_IRQ(7, regs); + else { + /* + * Now look at the extended interrupts + */ + pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16; + + if (pending & STATUSF_IP8) + do_IRQ(8, regs); + else if (pending & STATUSF_IP9) + do_IRQ(9, regs); + else if (pending & STATUSF_IP10) + do_IRQ(10, regs); + else if (pending & STATUSF_IP11) + do_IRQ(11, regs); + else + spurious_interrupt(regs); + } +} + extern void gt64240_irq_init(void); void __init arch_init_irq(void) @@ -60,8 +94,6 @@ void __init arch_init_irq(void) clear_c0_status(ST0_IM); local_irq_disable(); - /* Sets the first-level interrupt dispatcher. */ - set_except_vector(0, ocelot_handle_int); mips_cpu_irq_init(0); rm7k_cpu_irq_init(8); -- cgit v1.2.2 From e853534e6b94f87e48f29e1701c3f6f8a63669c5 Mon Sep 17 00:00:00 2001 From: Horst Schirmeier Date: Mon, 5 Jun 2006 10:45:30 +0100 Subject: [SERIAL] typo: buad -> baud Replacing mistyped "buad" with "baud" where applicable. Signed-off-by: Horst Schirmeier Signed-off-by: Russell King --- arch/mips/momentum/jaguar_atx/dbg_io.c | 2 +- arch/mips/momentum/ocelot_c/dbg_io.c | 2 +- arch/mips/momentum/ocelot_g/dbg_io.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/mips/momentum') diff --git a/arch/mips/momentum/jaguar_atx/dbg_io.c b/arch/mips/momentum/jaguar_atx/dbg_io.c index 542eac82b63c..d7dea0a136aa 100644 --- a/arch/mips/momentum/jaguar_atx/dbg_io.c +++ b/arch/mips/momentum/jaguar_atx/dbg_io.c @@ -73,7 +73,7 @@ void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) /* disable interrupts */ UART16550_WRITE(OFS_INTR_ENABLE, 0); - /* set up buad rate */ + /* set up baud rate */ { uint32 divisor; diff --git a/arch/mips/momentum/ocelot_c/dbg_io.c b/arch/mips/momentum/ocelot_c/dbg_io.c index 8720bccfdea2..f0a6a38fcf4d 100644 --- a/arch/mips/momentum/ocelot_c/dbg_io.c +++ b/arch/mips/momentum/ocelot_c/dbg_io.c @@ -73,7 +73,7 @@ void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) /* disable interrupts */ UART16550_WRITE(OFS_INTR_ENABLE, 0); - /* set up buad rate */ + /* set up baud rate */ { uint32 divisor; diff --git a/arch/mips/momentum/ocelot_g/dbg_io.c b/arch/mips/momentum/ocelot_g/dbg_io.c index 8720bccfdea2..f0a6a38fcf4d 100644 --- a/arch/mips/momentum/ocelot_g/dbg_io.c +++ b/arch/mips/momentum/ocelot_g/dbg_io.c @@ -73,7 +73,7 @@ void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) /* disable interrupts */ UART16550_WRITE(OFS_INTR_ENABLE, 0); - /* set up buad rate */ + /* set up baud rate */ { uint32 divisor; -- cgit v1.2.2