From fe00f943e0ef98b4057abcc2940d631a975b43cd Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 1 Mar 2005 19:22:29 +0000 Subject: Sparseify MIPS. Signed-off-by: Ralf Baechle --- arch/mips/mm/cache.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'arch/mips/mm/cache.c') diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 1d95cdb77bed..c0ac4f97e1ae 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -24,7 +24,8 @@ void (*flush_cache_mm)(struct mm_struct *mm); void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start, unsigned long end); void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn); -void (*flush_icache_range)(unsigned long start, unsigned long end); +void (*flush_icache_range)(unsigned long __user start, + unsigned long __user end); void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page); /* MIPS specific cache operations */ @@ -49,10 +50,10 @@ EXPORT_SYMBOL(_dma_cache_inv); * We could optimize the case where the cache argument is not BCACHE but * that seems very atypical use ... */ -asmlinkage int sys_cacheflush(unsigned long addr, unsigned long int bytes, - unsigned int cache) +asmlinkage int sys_cacheflush(unsigned long __user addr, + unsigned long bytes, unsigned int cache) { - if (!access_ok(VERIFY_WRITE, (void *) addr, bytes)) + if (!access_ok(VERIFY_WRITE, (void __user *) addr, bytes)) return -EFAULT; flush_icache_range(addr, addr + bytes); -- cgit v1.2.2 From 9ff77c469ed16221c6a4e882e48e4f0dcf451bda Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 8 Mar 2005 14:39:39 +0000 Subject: Export shm_align_mask and flush_data_cache_page. Signed-off-by: Ralf Baechle --- arch/mips/mm/cache.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/mips/mm/cache.c') diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index c0ac4f97e1ae..fe0110074902 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -33,6 +33,8 @@ void (*flush_cache_sigtramp)(unsigned long addr); void (*flush_data_cache_page)(unsigned long addr); void (*flush_icache_all)(void); +EXPORT_SYMBOL(flush_data_cache_page); + #ifdef CONFIG_DMA_NONCOHERENT /* DMA cache operations. */ -- cgit v1.2.2 From 53de0d471fe8ddbbeca938cffedb4cc94e04da10 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Fri, 18 Mar 2005 17:36:42 +0000 Subject: Reformat; cosmetic cleanups. Signed-off-by: Ralf Baechle --- arch/mips/mm/cache.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/mips/mm/cache.c') diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index fe0110074902..eaecb8631973 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -23,7 +23,8 @@ void (*__flush_cache_all)(void); void (*flush_cache_mm)(struct mm_struct *mm); void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start, unsigned long end); -void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn); +void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, + unsigned long pfn); void (*flush_icache_range)(unsigned long __user start, unsigned long __user end); void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page); -- cgit v1.2.2 From 6e760c8dae7d6c47eff011dd4aad53c94d30494b Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 6 Jul 2005 12:08:11 +0000 Subject: Rename CONFIG_CPU_MIPS{32,64} to CONFIG_CPU_MIPS{32|64}_R1. Signed-off-by: Ralf Baechle --- arch/mips/mm/cache.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/mips/mm/cache.c') diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index eaecb8631973..172293b58390 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -118,8 +118,8 @@ void __init cpu_cache_init(void) #if defined(CONFIG_CPU_R4X00) || defined(CONFIG_CPU_VR41XX) || \ defined(CONFIG_CPU_R4300) || defined(CONFIG_CPU_R5000) || \ defined(CONFIG_CPU_NEVADA) || defined(CONFIG_CPU_R5432) || \ - defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_MIPS32) || \ - defined(CONFIG_CPU_MIPS64) || defined(CONFIG_CPU_TX49XX) || \ + defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_MIPS32_R1) || \ + defined(CONFIG_CPU_MIPS64_R1) || defined(CONFIG_CPU_TX49XX) || \ defined(CONFIG_CPU_RM7000) || defined(CONFIG_CPU_RM9000) ld_mmu_r4xx0(); #endif -- cgit v1.2.2 From 02cf2119684e52e97a8a90bd7630386e0f1a250a Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sat, 1 Oct 2005 13:06:32 +0100 Subject: Cleanup the mess in cpu_cache_init. Signed-off-by: Ralf Baechle --- arch/mips/mm/cache.c | 90 +++++++++++++++++++++++----------------------------- 1 file changed, 40 insertions(+), 50 deletions(-) (limited to 'arch/mips/mm/cache.c') diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 172293b58390..611b48dde737 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -104,58 +104,48 @@ void __update_cache(struct vm_area_struct *vma, unsigned long address, } } -extern void ld_mmu_r23000(void); -extern void ld_mmu_r4xx0(void); -extern void ld_mmu_tx39(void); -extern void ld_mmu_r6000(void); -extern void ld_mmu_tfp(void); -extern void ld_mmu_andes(void); -extern void ld_mmu_sb1(void); +#define __weak __attribute__((weak)) + +static char cache_panic[] __initdata = "Yeee, unsupported cache architecture."; void __init cpu_cache_init(void) { - if (cpu_has_4ktlb) { -#if defined(CONFIG_CPU_R4X00) || defined(CONFIG_CPU_VR41XX) || \ - defined(CONFIG_CPU_R4300) || defined(CONFIG_CPU_R5000) || \ - defined(CONFIG_CPU_NEVADA) || defined(CONFIG_CPU_R5432) || \ - defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_MIPS32_R1) || \ - defined(CONFIG_CPU_MIPS64_R1) || defined(CONFIG_CPU_TX49XX) || \ - defined(CONFIG_CPU_RM7000) || defined(CONFIG_CPU_RM9000) - ld_mmu_r4xx0(); -#endif - } else switch (current_cpu_data.cputype) { -#ifdef CONFIG_CPU_R3000 - case CPU_R2000: - case CPU_R3000: - case CPU_R3000A: - case CPU_R3081E: - ld_mmu_r23000(); - break; -#endif -#ifdef CONFIG_CPU_TX39XX - case CPU_TX3912: - case CPU_TX3922: - case CPU_TX3927: - ld_mmu_tx39(); - break; -#endif -#ifdef CONFIG_CPU_R10000 - case CPU_R10000: - case CPU_R12000: - ld_mmu_r4xx0(); - break; -#endif -#ifdef CONFIG_CPU_SB1 - case CPU_SB1: - ld_mmu_sb1(); - break; -#endif - - case CPU_R8000: - panic("R8000 is unsupported"); - break; - - default: - panic("Yeee, unsupported cache architecture."); + if (cpu_has_3k_cache) { + extern void __weak r3k_cache_init(void); + + r3k_cache_init(); + return; + } + if (cpu_has_6k_cache) { + extern void __weak r6k_cache_init(void); + + r6k_cache_init(); + return; } + if (cpu_has_4k_cache) { + extern void __weak r4k_cache_init(void); + + r4k_cache_init(); + return; + } + if (cpu_has_8k_cache) { + extern void __weak r8k_cache_init(void); + + r8k_cache_init(); + return; + } + if (cpu_has_tx39_cache) { + extern void __weak tx39_cache_init(void); + + tx39_cache_init(); + return; + } + if (cpu_has_sb1_cache) { + extern void __weak sb1_cache_init(void); + + sb1_cache_init(); + return; + } + + panic(cache_panic); } -- cgit v1.2.2 From 750ccf687ff9adbf2a16066a3a2757d0f761384c Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Wed, 19 Oct 2005 19:57:14 +0900 Subject: Fix zero length sys_cacheflush Cacheflush(0, 0, 0) was crashing the system. This is because flush_icache_range(start, end) tries to flushing whole address space (0 - ~0UL) if both start and end are zero. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/mm/cache.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/mips/mm/cache.c') diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 611b48dde737..314701a66b13 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -56,6 +56,8 @@ EXPORT_SYMBOL(_dma_cache_inv); asmlinkage int sys_cacheflush(unsigned long __user addr, unsigned long bytes, unsigned int cache) { + if (bytes == 0) + return 0; if (!access_ok(VERIFY_WRITE, (void __user *) addr, bytes)) return -EFAULT; -- cgit v1.2.2