From 9bdcf336d0c061e77f4c45c7b2bc32e3ed6b57e3 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Sun, 4 Oct 2009 14:55:24 +0200 Subject: MIPS: Alchemy: devboard register abstraction All Alchemy development boards have external CPLDs with a few registers in them. They all share an identical register layout with only a few minor differences (except the PB1000) in bit functions and base addresses. This patch - adds a primitive facility to initialize and use these external registers, - replaces all occurrences of bcsr->xxx accesses with calls to the new functions (the pb1200 cascade irq handling code is special). - collects BCSR register information scattered throughout the board headers in a central place. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-db1x00/bcsr.h | 235 +++++++++++++++++++++++++++++ arch/mips/include/asm/mach-db1x00/db1200.h | 109 +------------ arch/mips/include/asm/mach-db1x00/db1x00.h | 92 ----------- arch/mips/include/asm/mach-pb1x00/pb1100.h | 49 ------ arch/mips/include/asm/mach-pb1x00/pb1200.h | 109 +------------ arch/mips/include/asm/mach-pb1x00/pb1500.h | 13 -- arch/mips/include/asm/mach-pb1x00/pb1550.h | 89 ----------- 7 files changed, 238 insertions(+), 458 deletions(-) create mode 100644 arch/mips/include/asm/mach-db1x00/bcsr.h (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h new file mode 100644 index 000000000000..ecbe19e3c14e --- /dev/null +++ b/arch/mips/include/asm/mach-db1x00/bcsr.h @@ -0,0 +1,235 @@ +/* + * bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction. + * + * All Alchemy development boards (except, of course, the weird PB1000) + * have a few registers in a CPLD with standardised layout; they mostly + * only differ in base address and bit meanings in the RESETS and BOARD + * registers. + * + * All data taken from the official AMD board documentation sheets. + */ + +#ifndef _DB1XXX_BCSR_H_ +#define _DB1XXX_BCSR_H_ + + +/* BCSR base addresses on various boards. BCSR base 2 refers to the + * physical address of the first HEXLEDS register, which is usually + * a variable offset from the WHOAMI register. + */ + +/* DB1000, DB1100, DB1500, PB1100, PB1500 */ +#define DB1000_BCSR_PHYS_ADDR 0x0E000000 +#define DB1000_BCSR_HEXLED_OFS 0x01000000 + +#define DB1550_BCSR_PHYS_ADDR 0x0F000000 +#define DB1550_BCSR_HEXLED_OFS 0x00400000 + +#define PB1550_BCSR_PHYS_ADDR 0x0F000000 +#define PB1550_BCSR_HEXLED_OFS 0x00800000 + +#define DB1200_BCSR_PHYS_ADDR 0x19800000 +#define DB1200_BCSR_HEXLED_OFS 0x00400000 + +#define PB1200_BCSR_PHYS_ADDR 0x0D800000 +#define PB1200_BCSR_HEXLED_OFS 0x00400000 + + +enum bcsr_id { + /* BCSR base 1 */ + BCSR_WHOAMI = 0, + BCSR_STATUS, + BCSR_SWITCHES, + BCSR_RESETS, + BCSR_PCMCIA, + BCSR_BOARD, + BCSR_LEDS, + BCSR_SYSTEM, + /* Au1200/1300 based boards */ + BCSR_INTCLR, + BCSR_INTSET, + BCSR_MASKCLR, + BCSR_MASKSET, + BCSR_SIGSTAT, + BCSR_INTSTAT, + + /* BCSR base 2 */ + BCSR_HEXLEDS, + BCSR_RSVD1, + BCSR_HEXCLEAR, + + BCSR_CNT, +}; + +/* register offsets, valid for all Db1xxx/Pb1xxx boards */ +#define BCSR_REG_WHOAMI 0x00 +#define BCSR_REG_STATUS 0x04 +#define BCSR_REG_SWITCHES 0x08 +#define BCSR_REG_RESETS 0x0c +#define BCSR_REG_PCMCIA 0x10 +#define BCSR_REG_BOARD 0x14 +#define BCSR_REG_LEDS 0x18 +#define BCSR_REG_SYSTEM 0x1c +/* Au1200/Au1300 based boards: CPLD IRQ muxer */ +#define BCSR_REG_INTCLR 0x20 +#define BCSR_REG_INTSET 0x24 +#define BCSR_REG_MASKCLR 0x28 +#define BCSR_REG_MASKSET 0x2c +#define BCSR_REG_SIGSTAT 0x30 +#define BCSR_REG_INTSTAT 0x34 + +/* hexled control, offset from BCSR base 2 */ +#define BCSR_REG_HEXLEDS 0x00 +#define BCSR_REG_HEXCLEAR 0x08 + +/* + * Register Bits and Pieces. + */ +#define BCSR_WHOAMI_DCID(x) ((x) & 0xf) +#define BCSR_WHOAMI_CPLD(x) (((x) >> 4) & 0xf) +#define BCSR_WHOAMI_BOARD(x) (((x) >> 8) & 0xf) + +/* register "WHOAMI" bits 11:8 identify the board */ +enum bcsr_whoami_boards { + BCSR_WHOAMI_PB1500 = 1, + BCSR_WHOAMI_PB1500R2, + BCSR_WHOAMI_PB1100, + BCSR_WHOAMI_DB1000, + BCSR_WHOAMI_DB1100, + BCSR_WHOAMI_DB1500, + BCSR_WHOAMI_DB1550, + BCSR_WHOAMI_PB1550_DDR, + BCSR_WHOAMI_PB1550 = BCSR_WHOAMI_PB1550_DDR, + BCSR_WHOAMI_PB1550_SDR, + BCSR_WHOAMI_PB1200_DDR1, + BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1, + BCSR_WHOAMI_PB1200_DDR2, + BCSR_WHOAMI_DB1200, +}; + +/* STATUS reg. Unless otherwise noted, they're valid on all boards. + * PB1200 = DB1200. + */ +#define BCSR_STATUS_PC0VS 0x0003 +#define BCSR_STATUS_PC1VS 0x000C +#define BCSR_STATUS_PC0FI 0x0010 +#define BCSR_STATUS_PC1FI 0x0020 +#define BCSR_STATUS_PB1550_SWAPBOOT 0x0040 +#define BCSR_STATUS_SRAMWIDTH 0x0080 +#define BCSR_STATUS_FLASHBUSY 0x0100 +#define BCSR_STATUS_ROMBUSY 0x0400 +#define BCSR_STATUS_SD0WP 0x0400 /* DB1200 */ +#define BCSR_STATUS_SD1WP 0x0800 +#define BCSR_STATUS_USBOTGID 0x0800 /* PB/DB1550 */ +#define BCSR_STATUS_DB1000_SWAPBOOT 0x2000 +#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200 */ +#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200 */ +#define BCSR_STATUS_DB1200_U0RXD 0x1000 /* DB1200 */ +#define BCSR_STATUS_DB1200_U1RXD 0x2000 /* DB1200 */ +#define BCSR_STATUS_FLASHDEN 0xC000 +#define BCSR_STATUS_DB1550_U0RXD 0x1000 /* DB1550 */ +#define BCSR_STATUS_DB1550_U3RXD 0x2000 /* DB1550 */ +#define BCSR_STATUS_PB1550_U0RXD 0x1000 /* PB1550 */ +#define BCSR_STATUS_PB1550_U1RXD 0x2000 /* PB1550 */ +#define BCSR_STATUS_PB1550_U3RXD 0x8000 /* PB1550 */ + + +/* DB/PB1000,1100,1500,1550 */ +#define BCSR_RESETS_PHY0 0x0001 +#define BCSR_RESETS_PHY1 0x0002 +#define BCSR_RESETS_DC 0x0004 +#define BCSR_RESETS_FIR_SEL 0x2000 +#define BCSR_RESETS_IRDA_MODE_MASK 0xC000 +#define BCSR_RESETS_IRDA_MODE_FULL 0x0000 +#define BCSR_RESETS_PB1550_WSCFSM 0x2000 +#define BCSR_RESETS_IRDA_MODE_OFF 0x4000 +#define BCSR_RESETS_IRDA_MODE_2_3 0x8000 +#define BCSR_RESETS_IRDA_MODE_1_3 0xC000 +#define BCSR_RESETS_DMAREQ 0x8000 /* PB1550 */ + +#define BCSR_BOARD_PCIM66EN 0x0001 +#define BCSR_BOARD_SD0PWR 0x0040 +#define BCSR_BOARD_SD1PWR 0x0080 +#define BCSR_BOARD_PCIM33 0x0100 +#define BCSR_BOARD_PCIEXTARB 0x0200 +#define BCSR_BOARD_GPIO200RST 0x0400 +#define BCSR_BOARD_PCICLKOUT 0x0800 +#define BCSR_BOARD_PCICFG 0x1000 +#define BCSR_BOARD_SPISEL 0x4000 /* PB/DB1550 */ +#define BCSR_BOARD_SD0WP 0x4000 /* DB1100 */ +#define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */ + + +/* DB/PB1200 */ +#define BCSR_RESETS_ETH 0x0001 +#define BCSR_RESETS_CAMERA 0x0002 +#define BCSR_RESETS_DC 0x0004 +#define BCSR_RESETS_IDE 0x0008 +#define BCSR_RESETS_TV 0x0010 /* DB1200 */ +/* Not resets but in the same register */ +#define BCSR_RESETS_PWMR1MUX 0x0800 /* DB1200 */ +#define BCSR_RESETS_PB1200_WSCFSM 0x0800 /* PB1200 */ +#define BCSR_RESETS_PSC0MUX 0x1000 +#define BCSR_RESETS_PSC1MUX 0x2000 +#define BCSR_RESETS_SPISEL 0x4000 +#define BCSR_RESETS_SD1MUX 0x8000 /* PB1200 */ + +#define BCSR_BOARD_LCDVEE 0x0001 +#define BCSR_BOARD_LCDVDD 0x0002 +#define BCSR_BOARD_LCDBL 0x0004 +#define BCSR_BOARD_CAMSNAP 0x0010 +#define BCSR_BOARD_CAMPWR 0x0020 +#define BCSR_BOARD_SD0PWR 0x0040 + + +#define BCSR_SWITCHES_DIP 0x00FF +#define BCSR_SWITCHES_DIP_1 0x0080 +#define BCSR_SWITCHES_DIP_2 0x0040 +#define BCSR_SWITCHES_DIP_3 0x0020 +#define BCSR_SWITCHES_DIP_4 0x0010 +#define BCSR_SWITCHES_DIP_5 0x0008 +#define BCSR_SWITCHES_DIP_6 0x0004 +#define BCSR_SWITCHES_DIP_7 0x0002 +#define BCSR_SWITCHES_DIP_8 0x0001 +#define BCSR_SWITCHES_ROTARY 0x0F00 + + +#define BCSR_PCMCIA_PC0VPP 0x0003 +#define BCSR_PCMCIA_PC0VCC 0x000C +#define BCSR_PCMCIA_PC0DRVEN 0x0010 +#define BCSR_PCMCIA_PC0RST 0x0080 +#define BCSR_PCMCIA_PC1VPP 0x0300 +#define BCSR_PCMCIA_PC1VCC 0x0C00 +#define BCSR_PCMCIA_PC1DRVEN 0x1000 +#define BCSR_PCMCIA_PC1RST 0x8000 + + +#define BCSR_LEDS_DECIMALS 0x0003 +#define BCSR_LEDS_LED0 0x0100 +#define BCSR_LEDS_LED1 0x0200 +#define BCSR_LEDS_LED2 0x0400 +#define BCSR_LEDS_LED3 0x0800 + + +#define BCSR_SYSTEM_RESET 0x8000 /* clear to reset */ +#define BCSR_SYSTEM_PWROFF 0x4000 /* set to power off */ +#define BCSR_SYSTEM_VDDI 0x001F /* PB1xxx boards */ + + + + +/* initialize BCSR for a board. Provide the PHYSICAL addresses of both + * BCSR spaces. + */ +void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys); + +/* read a board register */ +unsigned short bcsr_read(enum bcsr_id reg); + +/* write to a board register */ +void bcsr_write(enum bcsr_id reg, unsigned short val); + +/* modify a register. clear bits set in 'clr', set bits set in 'set' */ +void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set); + +#endif diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h index 27f26102b1bb..2909b834e4af 100644 --- a/arch/mips/include/asm/mach-db1x00/db1200.h +++ b/arch/mips/include/asm/mach-db1x00/db1200.h @@ -45,113 +45,6 @@ #define AC97_PSC_BASE PSC1_BASE_ADDR #define I2S_PSC_BASE PSC1_BASE_ADDR -#define BCSR_KSEG1_ADDR 0xB9800000 - -typedef volatile struct -{ - /*00*/ u16 whoami; - u16 reserved0; - /*04*/ u16 status; - u16 reserved1; - /*08*/ u16 switches; - u16 reserved2; - /*0C*/ u16 resets; - u16 reserved3; - - /*10*/ u16 pcmcia; - u16 reserved4; - /*14*/ u16 board; - u16 reserved5; - /*18*/ u16 disk_leds; - u16 reserved6; - /*1C*/ u16 system; - u16 reserved7; - - /*20*/ u16 intclr; - u16 reserved8; - /*24*/ u16 intset; - u16 reserved9; - /*28*/ u16 intclr_mask; - u16 reserved10; - /*2C*/ u16 intset_mask; - u16 reserved11; - - /*30*/ u16 sig_status; - u16 reserved12; - /*34*/ u16 int_status; - u16 reserved13; - /*38*/ u16 reserved14; - u16 reserved15; - /*3C*/ u16 reserved16; - u16 reserved17; - -} BCSR; - -static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; - -/* - * Register bit definitions for the BCSRs - */ -#define BCSR_WHOAMI_DCID 0x000F -#define BCSR_WHOAMI_CPLD 0x00F0 -#define BCSR_WHOAMI_BOARD 0x0F00 - -#define BCSR_STATUS_PCMCIA0VS 0x0003 -#define BCSR_STATUS_PCMCIA1VS 0x000C -#define BCSR_STATUS_SWAPBOOT 0x0040 -#define BCSR_STATUS_FLASHBUSY 0x0100 -#define BCSR_STATUS_IDECBLID 0x0200 -#define BCSR_STATUS_SD0WP 0x0400 -#define BCSR_STATUS_U0RXD 0x1000 -#define BCSR_STATUS_U1RXD 0x2000 - -#define BCSR_SWITCHES_OCTAL 0x00FF -#define BCSR_SWITCHES_DIP_1 0x0080 -#define BCSR_SWITCHES_DIP_2 0x0040 -#define BCSR_SWITCHES_DIP_3 0x0020 -#define BCSR_SWITCHES_DIP_4 0x0010 -#define BCSR_SWITCHES_DIP_5 0x0008 -#define BCSR_SWITCHES_DIP_6 0x0004 -#define BCSR_SWITCHES_DIP_7 0x0002 -#define BCSR_SWITCHES_DIP_8 0x0001 -#define BCSR_SWITCHES_ROTARY 0x0F00 - -#define BCSR_RESETS_ETH 0x0001 -#define BCSR_RESETS_CAMERA 0x0002 -#define BCSR_RESETS_DC 0x0004 -#define BCSR_RESETS_IDE 0x0008 -#define BCSR_RESETS_TV 0x0010 -/* Not resets but in the same register */ -#define BCSR_RESETS_PWMR1MUX 0x0800 -#define BCSR_RESETS_PCS0MUX 0x1000 -#define BCSR_RESETS_PCS1MUX 0x2000 -#define BCSR_RESETS_SPISEL 0x4000 - -#define BCSR_PCMCIA_PC0VPP 0x0003 -#define BCSR_PCMCIA_PC0VCC 0x000C -#define BCSR_PCMCIA_PC0DRVEN 0x0010 -#define BCSR_PCMCIA_PC0RST 0x0080 -#define BCSR_PCMCIA_PC1VPP 0x0300 -#define BCSR_PCMCIA_PC1VCC 0x0C00 -#define BCSR_PCMCIA_PC1DRVEN 0x1000 -#define BCSR_PCMCIA_PC1RST 0x8000 - -#define BCSR_BOARD_LCDVEE 0x0001 -#define BCSR_BOARD_LCDVDD 0x0002 -#define BCSR_BOARD_LCDBL 0x0004 -#define BCSR_BOARD_CAMSNAP 0x0010 -#define BCSR_BOARD_CAMPWR 0x0020 -#define BCSR_BOARD_SD0PWR 0x0040 - -#define BCSR_LEDS_DECIMALS 0x0003 -#define BCSR_LEDS_LED0 0x0100 -#define BCSR_LEDS_LED1 0x0200 -#define BCSR_LEDS_LED2 0x0400 -#define BCSR_LEDS_LED3 0x0800 - -#define BCSR_SYSTEM_POWEROFF 0x4000 -#define BCSR_SYSTEM_RESET 0x8000 - /* Bit positions for the different interrupt sources */ #define BCSR_INT_IDE 0x0001 #define BCSR_INT_ETH 0x0002 @@ -222,7 +115,7 @@ enum external_pb1200_ints { #define BOARD_PC0_INT DB1200_PC0_INT #define BOARD_PC1_INT DB1200_PC1_INT -#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET))) +#define BOARD_CARD_INSERTED(SOCKET) (bcsr_read(BCSR_SIGSTAT) & (1 << (8 + (2 * SOCKET)))) /* NAND chip select */ #define NAND_CS 1 diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h index 1a515b8c870f..cfa64297da08 100644 --- a/arch/mips/include/asm/mach-db1x00/db1x00.h +++ b/arch/mips/include/asm/mach-db1x00/db1x00.h @@ -41,102 +41,10 @@ #define SMBUS_PSC_BASE PSC2_BASE_ADDR #define I2S_PSC_BASE PSC3_BASE_ADDR -#define BCSR_KSEG1_ADDR 0xAF000000 #define NAND_PHYS_ADDR 0x20000000 -#else -#define BCSR_KSEG1_ADDR 0xAE000000 #endif -/* - * Overlay data structure of the DBAu1x00 board registers. - * Registers are located at physical 0E0000xx, KSEG1 0xAE0000xx. - */ -typedef volatile struct -{ - /*00*/ unsigned short whoami; - unsigned short reserved0; - /*04*/ unsigned short status; - unsigned short reserved1; - /*08*/ unsigned short switches; - unsigned short reserved2; - /*0C*/ unsigned short resets; - unsigned short reserved3; - /*10*/ unsigned short pcmcia; - unsigned short reserved4; - /*14*/ unsigned short specific; - unsigned short reserved5; - /*18*/ unsigned short leds; - unsigned short reserved6; - /*1C*/ unsigned short swreset; - unsigned short reserved7; - -} BCSR; - - -/* - * Register/mask bit definitions for the BCSRs - */ -#define BCSR_WHOAMI_DCID 0x000F -#define BCSR_WHOAMI_CPLD 0x00F0 -#define BCSR_WHOAMI_BOARD 0x0F00 - -#define BCSR_STATUS_PC0VS 0x0003 -#define BCSR_STATUS_PC1VS 0x000C -#define BCSR_STATUS_PC0FI 0x0010 -#define BCSR_STATUS_PC1FI 0x0020 -#define BCSR_STATUS_FLASHBUSY 0x0100 -#define BCSR_STATUS_ROMBUSY 0x0400 -#define BCSR_STATUS_SWAPBOOT 0x2000 -#define BCSR_STATUS_FLASHDEN 0xC000 - -#define BCSR_SWITCHES_DIP 0x00FF -#define BCSR_SWITCHES_DIP_1 0x0080 -#define BCSR_SWITCHES_DIP_2 0x0040 -#define BCSR_SWITCHES_DIP_3 0x0020 -#define BCSR_SWITCHES_DIP_4 0x0010 -#define BCSR_SWITCHES_DIP_5 0x0008 -#define BCSR_SWITCHES_DIP_6 0x0004 -#define BCSR_SWITCHES_DIP_7 0x0002 -#define BCSR_SWITCHES_DIP_8 0x0001 -#define BCSR_SWITCHES_ROTARY 0x0F00 - -#define BCSR_RESETS_PHY0 0x0001 -#define BCSR_RESETS_PHY1 0x0002 -#define BCSR_RESETS_DC 0x0004 -#define BCSR_RESETS_FIR_SEL 0x2000 -#define BCSR_RESETS_IRDA_MODE_MASK 0xC000 -#define BCSR_RESETS_IRDA_MODE_FULL 0x0000 -#define BCSR_RESETS_IRDA_MODE_OFF 0x4000 -#define BCSR_RESETS_IRDA_MODE_2_3 0x8000 -#define BCSR_RESETS_IRDA_MODE_1_3 0xC000 - -#define BCSR_PCMCIA_PC0VPP 0x0003 -#define BCSR_PCMCIA_PC0VCC 0x000C -#define BCSR_PCMCIA_PC0DRVEN 0x0010 -#define BCSR_PCMCIA_PC0RST 0x0080 -#define BCSR_PCMCIA_PC1VPP 0x0300 -#define BCSR_PCMCIA_PC1VCC 0x0C00 -#define BCSR_PCMCIA_PC1DRVEN 0x1000 -#define BCSR_PCMCIA_PC1RST 0x8000 - -#define BCSR_BOARD_PCIM66EN 0x0001 -#define BCSR_BOARD_SD0_PWR 0x0040 -#define BCSR_BOARD_SD1_PWR 0x0080 -#define BCSR_BOARD_PCIM33 0x0100 -#define BCSR_BOARD_GPIO200RST 0x0400 -#define BCSR_BOARD_PCICFG 0x1000 -#define BCSR_BOARD_SD0_WP 0x4000 -#define BCSR_BOARD_SD1_WP 0x8000 - -#define BCSR_LEDS_DECIMALS 0x0003 -#define BCSR_LEDS_LED0 0x0100 -#define BCSR_LEDS_LED1 0x0200 -#define BCSR_LEDS_LED2 0x0400 -#define BCSR_LEDS_LED3 0x0800 - -#define BCSR_SWRESET_RESET 0x0080 - /* PCMCIA DBAu1x00 specific defines */ #define PCMCIA_MAX_SOCK 1 #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) diff --git a/arch/mips/include/asm/mach-pb1x00/pb1100.h b/arch/mips/include/asm/mach-pb1x00/pb1100.h index b1a60f1cbd02..f2bf73a11fb2 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1100.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1100.h @@ -26,55 +26,6 @@ #ifndef __ASM_PB1100_H #define __ASM_PB1100_H -#define PB1100_IDENT 0xAE000000 -#define BOARD_STATUS_REG 0xAE000004 -# define PB1100_ROM_SEL (1 << 15) -# define PB1100_ROM_SIZ (1 << 14) -# define PB1100_SWAP_BOOT (1 << 13) -# define PB1100_FLASH_WP (1 << 12) -# define PB1100_ROM_H_STS (1 << 11) -# define PB1100_ROM_L_STS (1 << 10) -# define PB1100_FLASH_H_STS (1 << 9) -# define PB1100_FLASH_L_STS (1 << 8) -# define PB1100_SRAM_SIZ (1 << 7) -# define PB1100_TSC_BUSY (1 << 6) -# define PB1100_PCMCIA_VS_MASK (3 << 4) -# define PB1100_RS232_CD (1 << 3) -# define PB1100_RS232_CTS (1 << 2) -# define PB1100_RS232_DSR (1 << 1) -# define PB1100_RS232_RI (1 << 0) - -#define PB1100_IRDA_RS232 0xAE00000C -# define PB1100_IRDA_FULL (0 << 14) /* full power */ -# define PB1100_IRDA_SHUTDOWN (1 << 14) -# define PB1100_IRDA_TT (2 << 14) /* 2/3 power */ -# define PB1100_IRDA_OT (3 << 14) /* 1/3 power */ -# define PB1100_IRDA_FIR (1 << 13) - -#define PCMCIA_BOARD_REG 0xAE000010 -# define PB1100_SD_WP1_RO (1 << 15) /* read only */ -# define PB1100_SD_WP0_RO (1 << 14) /* read only */ -# define PB1100_SD_PWR1 (1 << 11) /* applies power to SD1 */ -# define PB1100_SD_PWR0 (1 << 10) /* applies power to SD0 */ -# define PB1100_SEL_SD_CONN1 (1 << 9) -# define PB1100_SEL_SD_CONN0 (1 << 8) -# define PC_DEASSERT_RST (1 << 7) -# define PC_DRV_EN (1 << 4) - -#define PB1100_G_CONTROL 0xAE000014 /* graphics control */ - -#define PB1100_RST_VDDI 0xAE00001C -# define PB1100_SOFT_RESET (1 << 15) /* clear to reset the board */ -# define PB1100_VDDI_MASK 0x1F - -#define PB1100_LEDS 0xAE000018 - -/* - * 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED. - * 7:0 is the LED Display's decimal points. - */ -#define PB1100_HEX_LED 0xAE000018 - /* PCMCIA Pb1100 specific defines */ #define PCMCIA_MAX_SOCK 0 #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h index c8618df88cb5..a51512c68177 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1200.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h @@ -43,113 +43,8 @@ * Refer to board documentation. */ #define AC97_PSC_BASE PSC1_BASE_ADDR -#define I2S_PSC_BASE PSC1_BASE_ADDR +#define I2S_PSC_BASE PSC1_BASE_ADDR -#define BCSR_KSEG1_ADDR 0xAD800000 - -typedef volatile struct -{ - /*00*/ u16 whoami; - u16 reserved0; - /*04*/ u16 status; - u16 reserved1; - /*08*/ u16 switches; - u16 reserved2; - /*0C*/ u16 resets; - u16 reserved3; - - /*10*/ u16 pcmcia; - u16 reserved4; - /*14*/ u16 board; - u16 reserved5; - /*18*/ u16 disk_leds; - u16 reserved6; - /*1C*/ u16 system; - u16 reserved7; - - /*20*/ u16 intclr; - u16 reserved8; - /*24*/ u16 intset; - u16 reserved9; - /*28*/ u16 intclr_mask; - u16 reserved10; - /*2C*/ u16 intset_mask; - u16 reserved11; - - /*30*/ u16 sig_status; - u16 reserved12; - /*34*/ u16 int_status; - u16 reserved13; - /*38*/ u16 reserved14; - u16 reserved15; - /*3C*/ u16 reserved16; - u16 reserved17; - -} BCSR; - -static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; - -/* - * Register bit definitions for the BCSRs - */ -#define BCSR_WHOAMI_DCID 0x000F -#define BCSR_WHOAMI_CPLD 0x00F0 -#define BCSR_WHOAMI_BOARD 0x0F00 - -#define BCSR_STATUS_PCMCIA0VS 0x0003 -#define BCSR_STATUS_PCMCIA1VS 0x000C -#define BCSR_STATUS_SWAPBOOT 0x0040 -#define BCSR_STATUS_FLASHBUSY 0x0100 -#define BCSR_STATUS_IDECBLID 0x0200 -#define BCSR_STATUS_SD0WP 0x0400 -#define BCSR_STATUS_SD1WP 0x0800 -#define BCSR_STATUS_U0RXD 0x1000 -#define BCSR_STATUS_U1RXD 0x2000 - -#define BCSR_SWITCHES_OCTAL 0x00FF -#define BCSR_SWITCHES_DIP_1 0x0080 -#define BCSR_SWITCHES_DIP_2 0x0040 -#define BCSR_SWITCHES_DIP_3 0x0020 -#define BCSR_SWITCHES_DIP_4 0x0010 -#define BCSR_SWITCHES_DIP_5 0x0008 -#define BCSR_SWITCHES_DIP_6 0x0004 -#define BCSR_SWITCHES_DIP_7 0x0002 -#define BCSR_SWITCHES_DIP_8 0x0001 -#define BCSR_SWITCHES_ROTARY 0x0F00 - -#define BCSR_RESETS_ETH 0x0001 -#define BCSR_RESETS_CAMERA 0x0002 -#define BCSR_RESETS_DC 0x0004 -#define BCSR_RESETS_IDE 0x0008 -/* not resets but in the same register */ -#define BCSR_RESETS_WSCFSM 0x0800 -#define BCSR_RESETS_PCS0MUX 0x1000 -#define BCSR_RESETS_PCS1MUX 0x2000 -#define BCSR_RESETS_SPISEL 0x4000 -#define BCSR_RESETS_SD1MUX 0x8000 - -#define BCSR_PCMCIA_PC0VPP 0x0003 -#define BCSR_PCMCIA_PC0VCC 0x000C -#define BCSR_PCMCIA_PC0DRVEN 0x0010 -#define BCSR_PCMCIA_PC0RST 0x0080 -#define BCSR_PCMCIA_PC1VPP 0x0300 -#define BCSR_PCMCIA_PC1VCC 0x0C00 -#define BCSR_PCMCIA_PC1DRVEN 0x1000 -#define BCSR_PCMCIA_PC1RST 0x8000 - -#define BCSR_BOARD_LCDVEE 0x0001 -#define BCSR_BOARD_LCDVDD 0x0002 -#define BCSR_BOARD_LCDBL 0x0004 -#define BCSR_BOARD_CAMSNAP 0x0010 -#define BCSR_BOARD_CAMPWR 0x0020 -#define BCSR_BOARD_SD0PWR 0x0040 -#define BCSR_BOARD_SD1PWR 0x0080 - -#define BCSR_LEDS_DECIMALS 0x00FF -#define BCSR_LEDS_LED0 0x0100 -#define BCSR_LEDS_LED1 0x0200 -#define BCSR_LEDS_LED2 0x0400 -#define BCSR_LEDS_LED3 0x0800 #define BCSR_SYSTEM_VDDI 0x001F #define BCSR_SYSTEM_POWEROFF 0x4000 @@ -251,7 +146,7 @@ enum external_pb1200_ints { #define BOARD_PC0_INT PB1200_PC0_INT #define BOARD_PC1_INT PB1200_PC1_INT -#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET))) +#define BOARD_CARD_INSERTED(SOCKET) (bcsr_read(BCSR_SIGSTAT & (1 << (8 + (2 * SOCKET)))) /* NAND chip select */ #define NAND_CS 1 diff --git a/arch/mips/include/asm/mach-pb1x00/pb1500.h b/arch/mips/include/asm/mach-pb1x00/pb1500.h index da51a2eb7b82..82431a7ab942 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1500.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1500.h @@ -26,19 +26,6 @@ #ifndef __ASM_PB1500_H #define __ASM_PB1500_H -#define IDENT_BOARD_REG 0xAE000000 -#define BOARD_STATUS_REG 0xAE000004 -#define PCI_BOARD_REG 0xAE000010 -#define PCMCIA_BOARD_REG 0xAE000010 -# define PC_DEASSERT_RST 0x80 -# define PC_DRV_EN 0x10 -#define PB1500_G_CONTROL 0xAE000014 -#define PB1500_RST_VDDI 0xAE00001C -#define PB1500_LEDS 0xAE000018 - -#define PB1500_HEX_LED 0xAF000004 -#define PB1500_HEX_LED_BLANK 0xAF000008 - /* PCMCIA Pb1500 specific defines */ #define PCMCIA_MAX_SOCK 0 #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h index 6704a11497db..306d584abbd4 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1550.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h @@ -40,95 +40,6 @@ #define SMBUS_PSC_BASE PSC2_BASE_ADDR #define I2S_PSC_BASE PSC3_BASE_ADDR -#define BCSR_PHYS_ADDR 0xAF000000 - -typedef volatile struct -{ - /*00*/ u16 whoami; - u16 reserved0; - /*04*/ u16 status; - u16 reserved1; - /*08*/ u16 switches; - u16 reserved2; - /*0C*/ u16 resets; - u16 reserved3; - /*10*/ u16 pcmcia; - u16 reserved4; - /*14*/ u16 pci; - u16 reserved5; - /*18*/ u16 leds; - u16 reserved6; - /*1C*/ u16 system; - u16 reserved7; - -} BCSR; - -static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR; - -/* - * Register bit definitions for the BCSRs - */ -#define BCSR_WHOAMI_DCID 0x000F -#define BCSR_WHOAMI_CPLD 0x00F0 -#define BCSR_WHOAMI_BOARD 0x0F00 - -#define BCSR_STATUS_PCMCIA0VS 0x0003 -#define BCSR_STATUS_PCMCIA1VS 0x000C -#define BCSR_STATUS_PCMCIA0FI 0x0010 -#define BCSR_STATUS_PCMCIA1FI 0x0020 -#define BCSR_STATUS_SWAPBOOT 0x0040 -#define BCSR_STATUS_SRAMWIDTH 0x0080 -#define BCSR_STATUS_FLASHBUSY 0x0100 -#define BCSR_STATUS_ROMBUSY 0x0200 -#define BCSR_STATUS_USBOTGID 0x0800 -#define BCSR_STATUS_U0RXD 0x1000 -#define BCSR_STATUS_U1RXD 0x2000 -#define BCSR_STATUS_U3RXD 0x8000 - -#define BCSR_SWITCHES_OCTAL 0x00FF -#define BCSR_SWITCHES_DIP_1 0x0080 -#define BCSR_SWITCHES_DIP_2 0x0040 -#define BCSR_SWITCHES_DIP_3 0x0020 -#define BCSR_SWITCHES_DIP_4 0x0010 -#define BCSR_SWITCHES_DIP_5 0x0008 -#define BCSR_SWITCHES_DIP_6 0x0004 -#define BCSR_SWITCHES_DIP_7 0x0002 -#define BCSR_SWITCHES_DIP_8 0x0001 -#define BCSR_SWITCHES_ROTARY 0x0F00 - -#define BCSR_RESETS_PHY0 0x0001 -#define BCSR_RESETS_PHY1 0x0002 -#define BCSR_RESETS_DC 0x0004 -#define BCSR_RESETS_WSC 0x2000 -#define BCSR_RESETS_SPISEL 0x4000 -#define BCSR_RESETS_DMAREQ 0x8000 - -#define BCSR_PCMCIA_PC0VPP 0x0003 -#define BCSR_PCMCIA_PC0VCC 0x000C -#define BCSR_PCMCIA_PC0DRVEN 0x0010 -#define BCSR_PCMCIA_PC0RST 0x0080 -#define BCSR_PCMCIA_PC1VPP 0x0300 -#define BCSR_PCMCIA_PC1VCC 0x0C00 -#define BCSR_PCMCIA_PC1DRVEN 0x1000 -#define BCSR_PCMCIA_PC1RST 0x8000 - -#define BCSR_PCI_M66EN 0x0001 -#define BCSR_PCI_M33 0x0100 -#define BCSR_PCI_EXTERNARB 0x0200 -#define BCSR_PCI_GPIO200RST 0x0400 -#define BCSR_PCI_CLKOUT 0x0800 -#define BCSR_PCI_CFGHOST 0x1000 - -#define BCSR_LEDS_DECIMALS 0x00FF -#define BCSR_LEDS_LED0 0x0100 -#define BCSR_LEDS_LED1 0x0200 -#define BCSR_LEDS_LED2 0x0400 -#define BCSR_LEDS_LED3 0x0800 - -#define BCSR_SYSTEM_VDDI 0x001F -#define BCSR_SYSTEM_POWEROFF 0x4000 -#define BCSR_SYSTEM_RESET 0x8000 - #define PCMCIA_MAX_SOCK 1 #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) -- cgit v1.2.2 From 95a437966dba642870a93d16bf82af8926bb2082 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Sun, 4 Oct 2009 14:55:25 +0200 Subject: MIPS: Alchemy: devboards: factor out PB1200 IRQ cascade code. Move the PB1200 IRQ cascade code out to the BCSR support code: upcoming DB1300 support can use it too. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-db1x00/bcsr.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h index ecbe19e3c14e..618d2de02ed3 100644 --- a/arch/mips/include/asm/mach-db1x00/bcsr.h +++ b/arch/mips/include/asm/mach-db1x00/bcsr.h @@ -232,4 +232,7 @@ void bcsr_write(enum bcsr_id reg, unsigned short val); /* modify a register. clear bits set in 'clr', set bits set in 'set' */ void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set); +/* install CPLD IRQ demuxer (DB1200/PB1200) */ +void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq); + #endif -- cgit v1.2.2 From 7e50b2b741bb4f9dbddc9f56972ef82a7d4b33ed Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Sun, 4 Oct 2009 14:55:26 +0200 Subject: MIPS: Alchemy: remove board_init_irq() function. remove board_init_irq(): On all in-kernel boards it is sufficient to initialize board interrupts in an arch_initcall by using the default linux irq functions. Some small irqmap.c files have been folded into board_setup files. Run-tested on DB1200; compile-tested on all other affected boards. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-au1x00/au1000.h | 15 --------------- arch/mips/include/asm/mach-db1x00/db1200.h | 1 + arch/mips/include/asm/mach-pb1x00/pb1200.h | 1 + 3 files changed, 2 insertions(+), 15 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 854e95f1b07c..05078224e933 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -143,21 +143,6 @@ void au_sleep(void); void save_au1xxx_intctl(void); void restore_au1xxx_intctl(void); -/* - * Every board describes its IRQ mapping with this table. - */ -struct au1xxx_irqmap { - int im_irq; - int im_type; - int im_request; -}; - -/* core calls this function to let boards initialize other IRQ sources */ -void board_init_irq(void); - -/* boards call this to register additional (GPIO) interrupts */ -void au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count); - #endif /* !defined (_LANGUAGE_ASSEMBLY) */ /* diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h index 2909b834e4af..b7f18e1af50c 100644 --- a/arch/mips/include/asm/mach-db1x00/db1200.h +++ b/arch/mips/include/asm/mach-db1x00/db1200.h @@ -25,6 +25,7 @@ #define __ASM_DB1200_H #include +#include #include #define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h index a51512c68177..2458eb436a0c 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1200.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h @@ -25,6 +25,7 @@ #define __ASM_PB1200_H #include +#include #include #define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX -- cgit v1.2.2 From 66213b3ccfc770704025ce9465fa3aaedde21b55 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Sun, 4 Oct 2009 14:55:27 +0200 Subject: MIPS: PCMCIA: new socket driver for Au1000 demoboards. New PCMCIA socket driver for all Db/Pb1xxx boards (except Pb1000), which replaces au1000_db1x00.c and (most of) au1000_pb1x00.c. Notable improvements: - supports Db1000, DB/PB1100/1500/1550/1200. - support for carddetect and statuschange IRQs. - pcmcia socket mem/io/attr areas and irqs passed through platform resource information. - doesn't freeze system during card insertion/ejection like the one it replaces. - boardtype is automatically detected using BCSR ID register. Run-tested on the DB1200. Cc: Linux-PCMCIA Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-au1x00/au1000.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 05078224e933..fceeca883359 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -1724,6 +1724,20 @@ enum soc_au1200_ints { #endif +/* + * All Au1xx0 SOCs have a PCMCIA controller. + * We setup our 32-bit pseudo addresses to be equal to the + * 36-bit addr >> 4, to make it easier to check the address + * and fix it. + * The PCMCIA socket 0 physical attribute address is 0xF 4000 0000. + * The pseudo address we use is 0xF400 0000. Any address over + * 0xF400 0000 is a PCMCIA pseudo address. + */ +#define PCMCIA_IO_PSEUDO_PHYS (PCMCIA_IO_PHYS_ADDR >> 4) +#define PCMCIA_ATTR_PSEUDO_PHYS (PCMCIA_ATTR_PHYS_ADDR >> 4) +#define PCMCIA_MEM_PSEUDO_PHYS (PCMCIA_MEM_PHYS_ADDR >> 4) +#define PCMCIA_PSEUDO_END (0xffffffff) + #ifndef _LANGUAGE_ASSEMBLY typedef volatile struct { /* 0x0000 */ u32 toytrim; -- cgit v1.2.2 From 27dd65ac9afabc8e67ab73f7c2f575eddbb47167 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Sun, 4 Oct 2009 14:55:28 +0200 Subject: MIPS: Alchemy: devboards: wire up new PCMCIA driver. Register the PCMCIA driver on all boards supported by it, get rid of now-unused pcmcia macros in the board headers (and subsequently empty pb1100/pb1500 ones). Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-db1x00/db1200.h | 15 ------------- arch/mips/include/asm/mach-db1x00/db1x00.h | 8 ------- arch/mips/include/asm/mach-pb1x00/pb1100.h | 36 ------------------------------ arch/mips/include/asm/mach-pb1x00/pb1200.h | 14 ------------ arch/mips/include/asm/mach-pb1x00/pb1500.h | 36 ------------------------------ arch/mips/include/asm/mach-pb1x00/pb1550.h | 7 ------ 6 files changed, 116 deletions(-) delete mode 100644 arch/mips/include/asm/mach-pb1x00/pb1100.h delete mode 100644 arch/mips/include/asm/mach-pb1x00/pb1500.h (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h index b7f18e1af50c..52b1d84a92c7 100644 --- a/arch/mips/include/asm/mach-db1x00/db1200.h +++ b/arch/mips/include/asm/mach-db1x00/db1200.h @@ -103,21 +103,6 @@ enum external_pb1200_ints { DB1200_INT_END = DB1200_INT_BEGIN + 15, }; - -/* - * DBAu1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c - */ -#define PCMCIA_MAX_SOCK 1 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) - -/* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP, SLOT) \ - ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) - -#define BOARD_PC0_INT DB1200_PC0_INT -#define BOARD_PC1_INT DB1200_PC1_INT -#define BOARD_CARD_INSERTED(SOCKET) (bcsr_read(BCSR_SIGSTAT) & (1 << (8 + (2 * SOCKET)))) - /* NAND chip select */ #define NAND_CS 1 diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h index cfa64297da08..a919dac525a1 100644 --- a/arch/mips/include/asm/mach-db1x00/db1x00.h +++ b/arch/mips/include/asm/mach-db1x00/db1x00.h @@ -45,14 +45,6 @@ #endif -/* PCMCIA DBAu1x00 specific defines */ -#define PCMCIA_MAX_SOCK 1 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) - -/* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP, SLOT)\ - ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) - /* * NAND defines * diff --git a/arch/mips/include/asm/mach-pb1x00/pb1100.h b/arch/mips/include/asm/mach-pb1x00/pb1100.h deleted file mode 100644 index f2bf73a11fb2..000000000000 --- a/arch/mips/include/asm/mach-pb1x00/pb1100.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Alchemy Semi Pb1100 Referrence Board - * - * Copyright 2001, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * - */ -#ifndef __ASM_PB1100_H -#define __ASM_PB1100_H - -/* PCMCIA Pb1100 specific defines */ -#define PCMCIA_MAX_SOCK 0 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) - -/* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0)) - -#endif /* __ASM_PB1100_H */ diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h index 2458eb436a0c..962eb55dc880 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1200.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h @@ -135,20 +135,6 @@ enum external_pb1200_ints { PB1200_INT_END = PB1200_INT_BEGIN + 15 }; -/* - * Pb1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c - */ -#define PCMCIA_MAX_SOCK 1 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) - -/* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP, SLOT) \ - ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) - -#define BOARD_PC0_INT PB1200_PC0_INT -#define BOARD_PC1_INT PB1200_PC1_INT -#define BOARD_CARD_INSERTED(SOCKET) (bcsr_read(BCSR_SIGSTAT & (1 << (8 + (2 * SOCKET)))) - /* NAND chip select */ #define NAND_CS 1 diff --git a/arch/mips/include/asm/mach-pb1x00/pb1500.h b/arch/mips/include/asm/mach-pb1x00/pb1500.h deleted file mode 100644 index 82431a7ab942..000000000000 --- a/arch/mips/include/asm/mach-pb1x00/pb1500.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Alchemy Semi Pb1500 Referrence Board - * - * Copyright 2001, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * - */ -#ifndef __ASM_PB1500_H -#define __ASM_PB1500_H - -/* PCMCIA Pb1500 specific defines */ -#define PCMCIA_MAX_SOCK 0 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) - -/* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0)) - -#endif /* __ASM_PB1500_H */ diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h index 306d584abbd4..58796410bd6e 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1550.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h @@ -40,13 +40,6 @@ #define SMBUS_PSC_BASE PSC2_BASE_ADDR #define I2S_PSC_BASE PSC3_BASE_ADDR -#define PCMCIA_MAX_SOCK 1 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) - -/* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP, SLOT) \ - ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) - #if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER) #define PB1550_BOTH_BANKS #elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER) -- cgit v1.2.2 From 93e9cd8485b31e5a33f1040bff4d15e65c0b2d19 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Wed, 7 Oct 2009 20:15:14 +0200 Subject: MIPS: Alchemy: Simple cpu subtype detector Extract the alchemy chip variant from c0_prid register. Signed-off-by: Manuel Lauss Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/14/ Patchwork: http://patchwork.linux-mips.org/patch/707/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-au1x00/au1000.h | 31 ++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index fceeca883359..2dc87d3b0428 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -130,6 +130,37 @@ static inline int au1xxx_cpu_needs_config_od(void) return 0; } +#define ALCHEMY_CPU_UNKNOWN -1 +#define ALCHEMY_CPU_AU1000 0 +#define ALCHEMY_CPU_AU1500 1 +#define ALCHEMY_CPU_AU1100 2 +#define ALCHEMY_CPU_AU1550 3 +#define ALCHEMY_CPU_AU1200 4 + +static inline int alchemy_get_cputype(void) +{ + switch (read_c0_prid() & 0xffff0000) { + case 0x00030000: + return ALCHEMY_CPU_AU1000; + break; + case 0x01030000: + return ALCHEMY_CPU_AU1500; + break; + case 0x02030000: + return ALCHEMY_CPU_AU1100; + break; + case 0x03030000: + return ALCHEMY_CPU_AU1550; + break; + case 0x04030000: + case 0x05030000: + return ALCHEMY_CPU_AU1200; + break; + } + + return ALCHEMY_CPU_UNKNOWN; +} + /* arch/mips/au1000/common/clocks.c */ extern void set_au1x00_speed(unsigned int new_freq); extern unsigned int get_au1x00_speed(void); -- cgit v1.2.2 From 788144656b8a862e724a1296e64ab6375eb541ed Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Wed, 7 Oct 2009 20:15:15 +0200 Subject: MIPS: Alchemy: Stop IRQ name sharing Eliminate the sharing of IRQ names among the differenct Alchemy variants. IRQ numbers need no longer be hidden behind a CONFIG_SOC_AU1XXX symbol: step 1 in my quest to make the Alchemy code less reliant on a hardcoded subtype. This patch also renames the GPIO irq number constants. It's really an interrupt line, NOT a GPIO number! Code which relied on certain irq numbers to have the same name across all supported cpu subtypes is changed to determine current cpu subtype at runtime; in some places this isn't possible so a "compat" symbol is used. Run-tested on DB1200. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-au1x00/au1000.h | 674 ++++++++++++------------ arch/mips/include/asm/mach-au1x00/gpio-au1000.h | 74 ++- 2 files changed, 367 insertions(+), 381 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 2dc87d3b0428..c2e233997b6c 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -174,6 +174,333 @@ void au_sleep(void); void save_au1xxx_intctl(void); void restore_au1xxx_intctl(void); + +/* SOC Interrupt numbers */ + +#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) +#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) +#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1) +#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) +#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST + +enum soc_au1000_ints { + AU1000_FIRST_INT = AU1000_INTC0_INT_BASE, + AU1000_UART0_INT = AU1000_FIRST_INT, + AU1000_UART1_INT, + AU1000_UART2_INT, + AU1000_UART3_INT, + AU1000_SSI0_INT, + AU1000_SSI1_INT, + AU1000_DMA_INT_BASE, + + AU1000_TOY_INT = AU1000_FIRST_INT + 14, + AU1000_TOY_MATCH0_INT, + AU1000_TOY_MATCH1_INT, + AU1000_TOY_MATCH2_INT, + AU1000_RTC_INT, + AU1000_RTC_MATCH0_INT, + AU1000_RTC_MATCH1_INT, + AU1000_RTC_MATCH2_INT, + AU1000_IRDA_TX_INT, + AU1000_IRDA_RX_INT, + AU1000_USB_DEV_REQ_INT, + AU1000_USB_DEV_SUS_INT, + AU1000_USB_HOST_INT, + AU1000_ACSYNC_INT, + AU1000_MAC0_DMA_INT, + AU1000_MAC1_DMA_INT, + AU1000_I2S_UO_INT, + AU1000_AC97C_INT, + AU1000_GPIO0_INT, + AU1000_GPIO1_INT, + AU1000_GPIO2_INT, + AU1000_GPIO3_INT, + AU1000_GPIO4_INT, + AU1000_GPIO5_INT, + AU1000_GPIO6_INT, + AU1000_GPIO7_INT, + AU1000_GPIO8_INT, + AU1000_GPIO9_INT, + AU1000_GPIO10_INT, + AU1000_GPIO11_INT, + AU1000_GPIO12_INT, + AU1000_GPIO13_INT, + AU1000_GPIO14_INT, + AU1000_GPIO15_INT, + AU1000_GPIO16_INT, + AU1000_GPIO17_INT, + AU1000_GPIO18_INT, + AU1000_GPIO19_INT, + AU1000_GPIO20_INT, + AU1000_GPIO21_INT, + AU1000_GPIO22_INT, + AU1000_GPIO23_INT, + AU1000_GPIO24_INT, + AU1000_GPIO25_INT, + AU1000_GPIO26_INT, + AU1000_GPIO27_INT, + AU1000_GPIO28_INT, + AU1000_GPIO29_INT, + AU1000_GPIO30_INT, + AU1000_GPIO31_INT, +}; + +enum soc_au1100_ints { + AU1100_FIRST_INT = AU1000_INTC0_INT_BASE, + AU1100_UART0_INT = AU1100_FIRST_INT, + AU1100_UART1_INT, + AU1100_SD_INT, + AU1100_UART3_INT, + AU1100_SSI0_INT, + AU1100_SSI1_INT, + AU1100_DMA_INT_BASE, + + AU1100_TOY_INT = AU1100_FIRST_INT + 14, + AU1100_TOY_MATCH0_INT, + AU1100_TOY_MATCH1_INT, + AU1100_TOY_MATCH2_INT, + AU1100_RTC_INT, + AU1100_RTC_MATCH0_INT, + AU1100_RTC_MATCH1_INT, + AU1100_RTC_MATCH2_INT, + AU1100_IRDA_TX_INT, + AU1100_IRDA_RX_INT, + AU1100_USB_DEV_REQ_INT, + AU1100_USB_DEV_SUS_INT, + AU1100_USB_HOST_INT, + AU1100_ACSYNC_INT, + AU1100_MAC0_DMA_INT, + AU1100_GPIO208_215_INT, + AU1100_LCD_INT, + AU1100_AC97C_INT, + AU1100_GPIO0_INT, + AU1100_GPIO1_INT, + AU1100_GPIO2_INT, + AU1100_GPIO3_INT, + AU1100_GPIO4_INT, + AU1100_GPIO5_INT, + AU1100_GPIO6_INT, + AU1100_GPIO7_INT, + AU1100_GPIO8_INT, + AU1100_GPIO9_INT, + AU1100_GPIO10_INT, + AU1100_GPIO11_INT, + AU1100_GPIO12_INT, + AU1100_GPIO13_INT, + AU1100_GPIO14_INT, + AU1100_GPIO15_INT, + AU1100_GPIO16_INT, + AU1100_GPIO17_INT, + AU1100_GPIO18_INT, + AU1100_GPIO19_INT, + AU1100_GPIO20_INT, + AU1100_GPIO21_INT, + AU1100_GPIO22_INT, + AU1100_GPIO23_INT, + AU1100_GPIO24_INT, + AU1100_GPIO25_INT, + AU1100_GPIO26_INT, + AU1100_GPIO27_INT, + AU1100_GPIO28_INT, + AU1100_GPIO29_INT, + AU1100_GPIO30_INT, + AU1100_GPIO31_INT, +}; + +enum soc_au1500_ints { + AU1500_FIRST_INT = AU1000_INTC0_INT_BASE, + AU1500_UART0_INT = AU1500_FIRST_INT, + AU1500_PCI_INTA, + AU1500_PCI_INTB, + AU1500_UART3_INT, + AU1500_PCI_INTC, + AU1500_PCI_INTD, + AU1500_DMA_INT_BASE, + + AU1500_TOY_INT = AU1500_FIRST_INT + 14, + AU1500_TOY_MATCH0_INT, + AU1500_TOY_MATCH1_INT, + AU1500_TOY_MATCH2_INT, + AU1500_RTC_INT, + AU1500_RTC_MATCH0_INT, + AU1500_RTC_MATCH1_INT, + AU1500_RTC_MATCH2_INT, + AU1500_PCI_ERR_INT, + AU1500_RESERVED_INT, + AU1500_USB_DEV_REQ_INT, + AU1500_USB_DEV_SUS_INT, + AU1500_USB_HOST_INT, + AU1500_ACSYNC_INT, + AU1500_MAC0_DMA_INT, + AU1500_MAC1_DMA_INT, + AU1500_AC97C_INT = AU1500_FIRST_INT + 31, + AU1500_GPIO0_INT, + AU1500_GPIO1_INT, + AU1500_GPIO2_INT, + AU1500_GPIO3_INT, + AU1500_GPIO4_INT, + AU1500_GPIO5_INT, + AU1500_GPIO6_INT, + AU1500_GPIO7_INT, + AU1500_GPIO8_INT, + AU1500_GPIO9_INT, + AU1500_GPIO10_INT, + AU1500_GPIO11_INT, + AU1500_GPIO12_INT, + AU1500_GPIO13_INT, + AU1500_GPIO14_INT, + AU1500_GPIO15_INT, + AU1500_GPIO200_INT, + AU1500_GPIO201_INT, + AU1500_GPIO202_INT, + AU1500_GPIO203_INT, + AU1500_GPIO20_INT, + AU1500_GPIO204_INT, + AU1500_GPIO205_INT, + AU1500_GPIO23_INT, + AU1500_GPIO24_INT, + AU1500_GPIO25_INT, + AU1500_GPIO26_INT, + AU1500_GPIO27_INT, + AU1500_GPIO28_INT, + AU1500_GPIO206_INT, + AU1500_GPIO207_INT, + AU1500_GPIO208_215_INT, +}; + +enum soc_au1550_ints { + AU1550_FIRST_INT = AU1000_INTC0_INT_BASE, + AU1550_UART0_INT = AU1550_FIRST_INT, + AU1550_PCI_INTA, + AU1550_PCI_INTB, + AU1550_DDMA_INT, + AU1550_CRYPTO_INT, + AU1550_PCI_INTC, + AU1550_PCI_INTD, + AU1550_PCI_RST_INT, + AU1550_UART1_INT, + AU1550_UART3_INT, + AU1550_PSC0_INT, + AU1550_PSC1_INT, + AU1550_PSC2_INT, + AU1550_PSC3_INT, + AU1550_TOY_INT, + AU1550_TOY_MATCH0_INT, + AU1550_TOY_MATCH1_INT, + AU1550_TOY_MATCH2_INT, + AU1550_RTC_INT, + AU1550_RTC_MATCH0_INT, + AU1550_RTC_MATCH1_INT, + AU1550_RTC_MATCH2_INT, + + AU1550_NAND_INT = AU1550_FIRST_INT + 23, + AU1550_USB_DEV_REQ_INT, + AU1550_USB_DEV_SUS_INT, + AU1550_USB_HOST_INT, + AU1550_MAC0_DMA_INT, + AU1550_MAC1_DMA_INT, + AU1550_GPIO0_INT = AU1550_FIRST_INT + 32, + AU1550_GPIO1_INT, + AU1550_GPIO2_INT, + AU1550_GPIO3_INT, + AU1550_GPIO4_INT, + AU1550_GPIO5_INT, + AU1550_GPIO6_INT, + AU1550_GPIO7_INT, + AU1550_GPIO8_INT, + AU1550_GPIO9_INT, + AU1550_GPIO10_INT, + AU1550_GPIO11_INT, + AU1550_GPIO12_INT, + AU1550_GPIO13_INT, + AU1550_GPIO14_INT, + AU1550_GPIO15_INT, + AU1550_GPIO200_INT, + AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */ + AU1550_GPIO16_INT, + AU1550_GPIO17_INT, + AU1550_GPIO20_INT, + AU1550_GPIO21_INT, + AU1550_GPIO22_INT, + AU1550_GPIO23_INT, + AU1550_GPIO24_INT, + AU1550_GPIO25_INT, + AU1550_GPIO26_INT, + AU1550_GPIO27_INT, + AU1550_GPIO28_INT, + AU1550_GPIO206_INT, + AU1550_GPIO207_INT, + AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */ +}; + +enum soc_au1200_ints { + AU1200_FIRST_INT = AU1000_INTC0_INT_BASE, + AU1200_UART0_INT = AU1200_FIRST_INT, + AU1200_SWT_INT, + AU1200_SD_INT, + AU1200_DDMA_INT, + AU1200_MAE_BE_INT, + AU1200_GPIO200_INT, + AU1200_GPIO201_INT, + AU1200_GPIO202_INT, + AU1200_UART1_INT, + AU1200_MAE_FE_INT, + AU1200_PSC0_INT, + AU1200_PSC1_INT, + AU1200_AES_INT, + AU1200_CAMERA_INT, + AU1200_TOY_INT, + AU1200_TOY_MATCH0_INT, + AU1200_TOY_MATCH1_INT, + AU1200_TOY_MATCH2_INT, + AU1200_RTC_INT, + AU1200_RTC_MATCH0_INT, + AU1200_RTC_MATCH1_INT, + AU1200_RTC_MATCH2_INT, + AU1200_GPIO203_INT, + AU1200_NAND_INT, + AU1200_GPIO204_INT, + AU1200_GPIO205_INT, + AU1200_GPIO206_INT, + AU1200_GPIO207_INT, + AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */ + AU1200_USB_INT, + AU1200_LCD_INT, + AU1200_MAE_BOTH_INT, + AU1200_GPIO0_INT, + AU1200_GPIO1_INT, + AU1200_GPIO2_INT, + AU1200_GPIO3_INT, + AU1200_GPIO4_INT, + AU1200_GPIO5_INT, + AU1200_GPIO6_INT, + AU1200_GPIO7_INT, + AU1200_GPIO8_INT, + AU1200_GPIO9_INT, + AU1200_GPIO10_INT, + AU1200_GPIO11_INT, + AU1200_GPIO12_INT, + AU1200_GPIO13_INT, + AU1200_GPIO14_INT, + AU1200_GPIO15_INT, + AU1200_GPIO16_INT, + AU1200_GPIO17_INT, + AU1200_GPIO18_INT, + AU1200_GPIO19_INT, + AU1200_GPIO20_INT, + AU1200_GPIO21_INT, + AU1200_GPIO22_INT, + AU1200_GPIO23_INT, + AU1200_GPIO24_INT, + AU1200_GPIO25_INT, + AU1200_GPIO26_INT, + AU1200_GPIO27_INT, + AU1200_GPIO28_INT, + AU1200_GPIO29_INT, + AU1200_GPIO30_INT, + AU1200_GPIO31_INT, +}; + #endif /* !defined (_LANGUAGE_ASSEMBLY) */ /* @@ -565,70 +892,9 @@ void restore_au1xxx_intctl(void); #define IC1_TESTBIT 0xB1800080 -/* Interrupt Numbers */ + /* Au1000 */ #ifdef CONFIG_SOC_AU1000 -enum soc_au1000_ints { - AU1000_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, - AU1000_UART0_INT = AU1000_FIRST_INT, - AU1000_UART1_INT, /* au1000 */ - AU1000_UART2_INT, /* au1000 */ - AU1000_UART3_INT, - AU1000_SSI0_INT, /* au1000 */ - AU1000_SSI1_INT, /* au1000 */ - AU1000_DMA_INT_BASE, - - AU1000_TOY_INT = AU1000_FIRST_INT + 14, - AU1000_TOY_MATCH0_INT, - AU1000_TOY_MATCH1_INT, - AU1000_TOY_MATCH2_INT, - AU1000_RTC_INT, - AU1000_RTC_MATCH0_INT, - AU1000_RTC_MATCH1_INT, - AU1000_RTC_MATCH2_INT, - AU1000_IRDA_TX_INT, /* au1000 */ - AU1000_IRDA_RX_INT, /* au1000 */ - AU1000_USB_DEV_REQ_INT, - AU1000_USB_DEV_SUS_INT, - AU1000_USB_HOST_INT, - AU1000_ACSYNC_INT, - AU1000_MAC0_DMA_INT, - AU1000_MAC1_DMA_INT, - AU1000_I2S_UO_INT, /* au1000 */ - AU1000_AC97C_INT, - AU1000_GPIO_0, - AU1000_GPIO_1, - AU1000_GPIO_2, - AU1000_GPIO_3, - AU1000_GPIO_4, - AU1000_GPIO_5, - AU1000_GPIO_6, - AU1000_GPIO_7, - AU1000_GPIO_8, - AU1000_GPIO_9, - AU1000_GPIO_10, - AU1000_GPIO_11, - AU1000_GPIO_12, - AU1000_GPIO_13, - AU1000_GPIO_14, - AU1000_GPIO_15, - AU1000_GPIO_16, - AU1000_GPIO_17, - AU1000_GPIO_18, - AU1000_GPIO_19, - AU1000_GPIO_20, - AU1000_GPIO_21, - AU1000_GPIO_22, - AU1000_GPIO_23, - AU1000_GPIO_24, - AU1000_GPIO_25, - AU1000_GPIO_26, - AU1000_GPIO_27, - AU1000_GPIO_28, - AU1000_GPIO_29, - AU1000_GPIO_30, - AU1000_GPIO_31, -}; #define UART0_ADDR 0xB1100000 #define UART1_ADDR 0xB1200000 @@ -637,6 +903,7 @@ enum soc_au1000_ints { #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ #define USB_HOST_CONFIG 0xB017FFFC +#define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT #define AU1000_ETH0_BASE 0xB0500000 #define AU1000_ETH1_BASE 0xB0510000 @@ -647,78 +914,13 @@ enum soc_au1000_ints { /* Au1500 */ #ifdef CONFIG_SOC_AU1500 -enum soc_au1500_ints { - AU1500_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, - AU1500_UART0_INT = AU1500_FIRST_INT, - AU1000_PCI_INTA, /* au1500 */ - AU1000_PCI_INTB, /* au1500 */ - AU1500_UART3_INT, - AU1000_PCI_INTC, /* au1500 */ - AU1000_PCI_INTD, /* au1500 */ - AU1000_DMA_INT_BASE, - - AU1000_TOY_INT = AU1500_FIRST_INT + 14, - AU1000_TOY_MATCH0_INT, - AU1000_TOY_MATCH1_INT, - AU1000_TOY_MATCH2_INT, - AU1000_RTC_INT, - AU1000_RTC_MATCH0_INT, - AU1000_RTC_MATCH1_INT, - AU1000_RTC_MATCH2_INT, - AU1500_PCI_ERR_INT, - AU1500_RESERVED_INT, - AU1000_USB_DEV_REQ_INT, - AU1000_USB_DEV_SUS_INT, - AU1000_USB_HOST_INT, - AU1000_ACSYNC_INT, - AU1500_MAC0_DMA_INT, - AU1500_MAC1_DMA_INT, - AU1000_AC97C_INT = AU1500_FIRST_INT + 31, - AU1000_GPIO_0, - AU1000_GPIO_1, - AU1000_GPIO_2, - AU1000_GPIO_3, - AU1000_GPIO_4, - AU1000_GPIO_5, - AU1000_GPIO_6, - AU1000_GPIO_7, - AU1000_GPIO_8, - AU1000_GPIO_9, - AU1000_GPIO_10, - AU1000_GPIO_11, - AU1000_GPIO_12, - AU1000_GPIO_13, - AU1000_GPIO_14, - AU1000_GPIO_15, - AU1500_GPIO_200, - AU1500_GPIO_201, - AU1500_GPIO_202, - AU1500_GPIO_203, - AU1500_GPIO_20, - AU1500_GPIO_204, - AU1500_GPIO_205, - AU1500_GPIO_23, - AU1500_GPIO_24, - AU1500_GPIO_25, - AU1500_GPIO_26, - AU1500_GPIO_27, - AU1500_GPIO_28, - AU1500_GPIO_206, - AU1500_GPIO_207, - AU1500_GPIO_208_215, -}; - -/* shortcuts */ -#define INTA AU1000_PCI_INTA -#define INTB AU1000_PCI_INTB -#define INTC AU1000_PCI_INTC -#define INTD AU1000_PCI_INTD #define UART0_ADDR 0xB1100000 #define UART3_ADDR 0xB1400000 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ #define USB_HOST_CONFIG 0xB017fffc +#define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT #define AU1500_ETH0_BASE 0xB1500000 #define AU1500_ETH1_BASE 0xB1510000 @@ -729,67 +931,6 @@ enum soc_au1500_ints { /* Au1100 */ #ifdef CONFIG_SOC_AU1100 -enum soc_au1100_ints { - AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, - AU1100_UART0_INT = AU1100_FIRST_INT, - AU1100_UART1_INT, - AU1100_SD_INT, - AU1100_UART3_INT, - AU1000_SSI0_INT, - AU1000_SSI1_INT, - AU1000_DMA_INT_BASE, - - AU1000_TOY_INT = AU1100_FIRST_INT + 14, - AU1000_TOY_MATCH0_INT, - AU1000_TOY_MATCH1_INT, - AU1000_TOY_MATCH2_INT, - AU1000_RTC_INT, - AU1000_RTC_MATCH0_INT, - AU1000_RTC_MATCH1_INT, - AU1000_RTC_MATCH2_INT, - AU1000_IRDA_TX_INT, - AU1000_IRDA_RX_INT, - AU1000_USB_DEV_REQ_INT, - AU1000_USB_DEV_SUS_INT, - AU1000_USB_HOST_INT, - AU1000_ACSYNC_INT, - AU1100_MAC0_DMA_INT, - AU1100_GPIO_208_215, - AU1100_LCD_INT, - AU1000_AC97C_INT, - AU1000_GPIO_0, - AU1000_GPIO_1, - AU1000_GPIO_2, - AU1000_GPIO_3, - AU1000_GPIO_4, - AU1000_GPIO_5, - AU1000_GPIO_6, - AU1000_GPIO_7, - AU1000_GPIO_8, - AU1000_GPIO_9, - AU1000_GPIO_10, - AU1000_GPIO_11, - AU1000_GPIO_12, - AU1000_GPIO_13, - AU1000_GPIO_14, - AU1000_GPIO_15, - AU1000_GPIO_16, - AU1000_GPIO_17, - AU1000_GPIO_18, - AU1000_GPIO_19, - AU1000_GPIO_20, - AU1000_GPIO_21, - AU1000_GPIO_22, - AU1000_GPIO_23, - AU1000_GPIO_24, - AU1000_GPIO_25, - AU1000_GPIO_26, - AU1000_GPIO_27, - AU1000_GPIO_28, - AU1000_GPIO_29, - AU1000_GPIO_30, - AU1000_GPIO_31, -}; #define UART0_ADDR 0xB1100000 #define UART1_ADDR 0xB1200000 @@ -797,6 +938,7 @@ enum soc_au1100_ints { #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ #define USB_HOST_CONFIG 0xB017FFFC +#define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT #define AU1100_ETH0_BASE 0xB0500000 #define AU1100_MAC0_ENABLE 0xB0520000 @@ -804,80 +946,6 @@ enum soc_au1100_ints { #endif /* CONFIG_SOC_AU1100 */ #ifdef CONFIG_SOC_AU1550 -enum soc_au1550_ints { - AU1550_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, - AU1550_UART0_INT = AU1550_FIRST_INT, - AU1550_PCI_INTA, - AU1550_PCI_INTB, - AU1550_DDMA_INT, - AU1550_CRYPTO_INT, - AU1550_PCI_INTC, - AU1550_PCI_INTD, - AU1550_PCI_RST_INT, - AU1550_UART1_INT, - AU1550_UART3_INT, - AU1550_PSC0_INT, - AU1550_PSC1_INT, - AU1550_PSC2_INT, - AU1550_PSC3_INT, - AU1000_TOY_INT, - AU1000_TOY_MATCH0_INT, - AU1000_TOY_MATCH1_INT, - AU1000_TOY_MATCH2_INT, - AU1000_RTC_INT, - AU1000_RTC_MATCH0_INT, - AU1000_RTC_MATCH1_INT, - AU1000_RTC_MATCH2_INT, - - AU1550_NAND_INT = AU1550_FIRST_INT + 23, - AU1550_USB_DEV_REQ_INT, - AU1000_USB_DEV_REQ_INT = AU1550_USB_DEV_REQ_INT, - AU1550_USB_DEV_SUS_INT, - AU1000_USB_DEV_SUS_INT = AU1550_USB_DEV_SUS_INT, - AU1550_USB_HOST_INT, - AU1000_USB_HOST_INT = AU1550_USB_HOST_INT, - AU1550_MAC0_DMA_INT, - AU1550_MAC1_DMA_INT, - AU1000_GPIO_0 = AU1550_FIRST_INT + 32, - AU1000_GPIO_1, - AU1000_GPIO_2, - AU1000_GPIO_3, - AU1000_GPIO_4, - AU1000_GPIO_5, - AU1000_GPIO_6, - AU1000_GPIO_7, - AU1000_GPIO_8, - AU1000_GPIO_9, - AU1000_GPIO_10, - AU1000_GPIO_11, - AU1000_GPIO_12, - AU1000_GPIO_13, - AU1000_GPIO_14, - AU1000_GPIO_15, - AU1550_GPIO_200, - AU1500_GPIO_201_205, /* Logical or of GPIO201:205 */ - AU1500_GPIO_16, - AU1500_GPIO_17, - AU1500_GPIO_20, - AU1500_GPIO_21, - AU1500_GPIO_22, - AU1500_GPIO_23, - AU1500_GPIO_24, - AU1500_GPIO_25, - AU1500_GPIO_26, - AU1500_GPIO_27, - AU1500_GPIO_28, - AU1500_GPIO_206, - AU1500_GPIO_207, - AU1500_GPIO_208_218, /* Logical or of GPIO208:218 */ -}; - -/* shortcuts */ -#define INTA AU1550_PCI_INTA -#define INTB AU1550_PCI_INTB -#define INTC AU1550_PCI_INTC -#define INTD AU1550_PCI_INTD - #define UART0_ADDR 0xB1100000 #define UART1_ADDR 0xB1200000 #define UART3_ADDR 0xB1400000 @@ -885,6 +953,7 @@ enum soc_au1550_ints { #define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */ #define USB_OHCI_LEN 0x00060000 #define USB_HOST_CONFIG 0xB4027ffc +#define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT #define AU1550_ETH0_BASE 0xB0500000 #define AU1550_ETH1_BASE 0xB0510000 @@ -893,75 +962,8 @@ enum soc_au1550_ints { #define NUM_ETH_INTERFACES 2 #endif /* CONFIG_SOC_AU1550 */ + #ifdef CONFIG_SOC_AU1200 -enum soc_au1200_ints { - AU1200_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, - AU1200_UART0_INT = AU1200_FIRST_INT, - AU1200_SWT_INT, - AU1200_SD_INT, - AU1200_DDMA_INT, - AU1200_MAE_BE_INT, - AU1200_GPIO_200, - AU1200_GPIO_201, - AU1200_GPIO_202, - AU1200_UART1_INT, - AU1200_MAE_FE_INT, - AU1200_PSC0_INT, - AU1200_PSC1_INT, - AU1200_AES_INT, - AU1200_CAMERA_INT, - AU1000_TOY_INT, - AU1000_TOY_MATCH0_INT, - AU1000_TOY_MATCH1_INT, - AU1000_TOY_MATCH2_INT, - AU1000_RTC_INT, - AU1000_RTC_MATCH0_INT, - AU1000_RTC_MATCH1_INT, - AU1000_RTC_MATCH2_INT, - AU1200_GPIO_203, - AU1200_NAND_INT, - AU1200_GPIO_204, - AU1200_GPIO_205, - AU1200_GPIO_206, - AU1200_GPIO_207, - AU1200_GPIO_208_215, /* Logical OR of 208:215 */ - AU1200_USB_INT, - AU1000_USB_HOST_INT = AU1200_USB_INT, - AU1200_LCD_INT, - AU1200_MAE_BOTH_INT, - AU1000_GPIO_0, - AU1000_GPIO_1, - AU1000_GPIO_2, - AU1000_GPIO_3, - AU1000_GPIO_4, - AU1000_GPIO_5, - AU1000_GPIO_6, - AU1000_GPIO_7, - AU1000_GPIO_8, - AU1000_GPIO_9, - AU1000_GPIO_10, - AU1000_GPIO_11, - AU1000_GPIO_12, - AU1000_GPIO_13, - AU1000_GPIO_14, - AU1000_GPIO_15, - AU1000_GPIO_16, - AU1000_GPIO_17, - AU1000_GPIO_18, - AU1000_GPIO_19, - AU1000_GPIO_20, - AU1000_GPIO_21, - AU1000_GPIO_22, - AU1000_GPIO_23, - AU1000_GPIO_24, - AU1000_GPIO_25, - AU1000_GPIO_26, - AU1000_GPIO_27, - AU1000_GPIO_28, - AU1000_GPIO_29, - AU1000_GPIO_30, - AU1000_GPIO_31, -}; #define UART0_ADDR 0xB1100000 #define UART1_ADDR 0xB1200000 @@ -990,15 +992,9 @@ enum soc_au1200_ints { #define USBMSRMCFG_RDCOMB 30 #define USBMSRMCFG_PFEN 31 -#endif /* CONFIG_SOC_AU1200 */ +#define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT -#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) -#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) -#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_BASE + 32) -#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) - -#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST -#define INTX 0xFF /* not valid */ +#endif /* CONFIG_SOC_AU1200 */ /* Programmable Counters 0 and 1 */ #define SYS_BASE 0xB1900000 diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h index 91595fa89034..9cf32d9dbb21 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h @@ -35,15 +35,13 @@ static inline int au1000_gpio2_to_irq(int gpio) return -ENXIO; } -#ifdef CONFIG_SOC_AU1000 static inline int au1000_irq_to_gpio(int irq) { - if ((irq >= AU1000_GPIO_0) && (irq <= AU1000_GPIO_31)) - return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; + if ((irq >= AU1000_GPIO0_INT) && (irq <= AU1000_GPIO31_INT)) + return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO0_INT) + 0; return -ENXIO; } -#endif static inline int au1500_gpio1_to_irq(int gpio) { @@ -71,27 +69,25 @@ static inline int au1500_gpio2_to_irq(int gpio) return -ENXIO; } -#ifdef CONFIG_SOC_AU1500 static inline int au1500_irq_to_gpio(int irq) { switch (irq) { - case AU1000_GPIO_0 ... AU1000_GPIO_15: - case AU1500_GPIO_20: - case AU1500_GPIO_23 ... AU1500_GPIO_28: - return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; - case AU1500_GPIO_200 ... AU1500_GPIO_203: - return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_200) + 0; - case AU1500_GPIO_204 ... AU1500_GPIO_205: - return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_204) + 4; - case AU1500_GPIO_206 ... AU1500_GPIO_207: - return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6; - case AU1500_GPIO_208_215: + case AU1500_GPIO0_INT ... AU1500_GPIO15_INT: + case AU1500_GPIO20_INT: + case AU1500_GPIO23_INT ... AU1500_GPIO28_INT: + return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO0_INT) + 0; + case AU1500_GPIO200_INT ... AU1500_GPIO203_INT: + return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO200_INT) + 0; + case AU1500_GPIO204_INT ... AU1500_GPIO205_INT: + return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO204_INT) + 4; + case AU1500_GPIO206_INT ... AU1500_GPIO207_INT: + return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO206_INT) + 6; + case AU1500_GPIO208_215_INT: return ALCHEMY_GPIO2_BASE + 8; } return -ENXIO; } -#endif static inline int au1100_gpio1_to_irq(int gpio) { @@ -108,19 +104,17 @@ static inline int au1100_gpio2_to_irq(int gpio) return -ENXIO; } -#ifdef CONFIG_SOC_AU1100 static inline int au1100_irq_to_gpio(int irq) { switch (irq) { - case AU1000_GPIO_0 ... AU1000_GPIO_31: - return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; - case AU1100_GPIO_208_215: + case AU1100_GPIO0_INT ... AU1100_GPIO31_INT: + return ALCHEMY_GPIO1_BASE + (irq - AU1100_GPIO0_INT) + 0; + case AU1100_GPIO208_215_INT: return ALCHEMY_GPIO2_BASE + 8; } return -ENXIO; } -#endif static inline int au1550_gpio1_to_irq(int gpio) { @@ -149,24 +143,22 @@ static inline int au1550_gpio2_to_irq(int gpio) return -ENXIO; } -#ifdef CONFIG_SOC_AU1550 static inline int au1550_irq_to_gpio(int irq) { switch (irq) { - case AU1000_GPIO_0 ... AU1000_GPIO_15: - return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; - case AU1550_GPIO_200: - case AU1500_GPIO_201_205: - return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO_200) + 0; - case AU1500_GPIO_16 ... AU1500_GPIO_28: - return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO_16) + 16; - case AU1500_GPIO_206 ... AU1500_GPIO_208_218: - return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6; + case AU1550_GPIO0_INT ... AU1550_GPIO15_INT: + return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO0_INT) + 0; + case AU1550_GPIO200_INT: + case AU1550_GPIO201_205_INT: + return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO200_INT) + 0; + case AU1550_GPIO16_INT ... AU1550_GPIO28_INT: + return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO16_INT) + 16; + case AU1550_GPIO206_INT ... AU1550_GPIO208_215_INT: + return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO206_INT) + 6; } return -ENXIO; } -#endif static inline int au1200_gpio1_to_irq(int gpio) { @@ -187,23 +179,21 @@ static inline int au1200_gpio2_to_irq(int gpio) return -ENXIO; } -#ifdef CONFIG_SOC_AU1200 static inline int au1200_irq_to_gpio(int irq) { switch (irq) { - case AU1000_GPIO_0 ... AU1000_GPIO_31: - return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; - case AU1200_GPIO_200 ... AU1200_GPIO_202: - return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_200) + 0; - case AU1200_GPIO_203: + case AU1200_GPIO0_INT ... AU1200_GPIO31_INT: + return ALCHEMY_GPIO1_BASE + (irq - AU1200_GPIO0_INT) + 0; + case AU1200_GPIO200_INT ... AU1200_GPIO202_INT: + return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO200_INT) + 0; + case AU1200_GPIO203_INT: return ALCHEMY_GPIO2_BASE + 3; - case AU1200_GPIO_204 ... AU1200_GPIO_208_215: - return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_204) + 4; + case AU1200_GPIO204_INT ... AU1200_GPIO208_215_INT: + return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO204_INT) + 4; } return -ENXIO; } -#endif /* * GPIO1 block macros for common linux gpio functions. -- cgit v1.2.2 From ea071cc705e8bfba0c8bf84be8d4f9f4e9da6962 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Tue, 13 Oct 2009 20:22:34 +0200 Subject: MIPS: Alchemy: remove dbdma compat macros Remove dbdma compat macros, move remaining users over to default queueing functions and -flags. (Queueing function signature has changed in order to give a build failure instead of silent functional changes due to the no longer implicitly specified DDMA_FLAGS_IE flag) Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | 23 ++--------------------- 1 file changed, 2 insertions(+), 21 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h index d206000fbfe2..b417c3bcdcb9 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h @@ -339,8 +339,8 @@ u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits); u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries); /* Put buffers on source/destination descriptors. */ -u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags); -u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags); +u32 au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags); +u32 au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags); /* Get a buffer from the destination descriptor. */ u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes); @@ -363,25 +363,6 @@ void au1xxx_dbdma_suspend(void); void au1xxx_dbdma_resume(void); #endif - -/* - * Some compatibilty macros -- needed to make changes to API - * without breaking existing drivers. - */ -#define au1xxx_dbdma_put_source(chanid, buf, nbytes) \ - _au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE) -#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) \ - _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags) -#define put_source_flags(chanid, buf, nbytes, flags) \ - au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) - -#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) \ - _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE) -#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) \ - _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags) -#define put_dest_flags(chanid, buf, nbytes, flags) \ - au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) - /* * Flags for the put_source/put_dest functions. */ -- cgit v1.2.2 From 963accbc82a0912b39de39d59e2fd6741db3aa4b Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Tue, 13 Oct 2009 20:22:35 +0200 Subject: MIPS: Alchemy: change dbdma to accept physical memory addresses DMA can only be done from physical addresses; move the "virt_to_phys" source/destination buffer address translation from the dbdma queueing functions (since the hardware can only DMA to/from physical addresses) to their respective users. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h index b417c3bcdcb9..8c6b1105ce0b 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h @@ -339,8 +339,8 @@ u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits); u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries); /* Put buffers on source/destination descriptors. */ -u32 au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags); -u32 au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags); +u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags); +u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags); /* Get a buffer from the destination descriptor. */ u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes); -- cgit v1.2.2 From 8402a1588a4f63465079e98481dd83d1d9cc9a98 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Thu, 15 Oct 2009 18:49:27 +0200 Subject: MIPS: Alchemy: prom_putchar is board dependent This patch replaces the general alchemy prom_putchar() implementation in favor of board-specific versions: The UART where the output of prom_putchar is directed to really depends on the board, the current implementation hardcodes this on a per-SoC basis which is just wrong. So a generic uart tx function is provided in the alchemy headers, and the boards can provide their own prom_putchar with custom destination uart, and all in-kernel alchemy boards support early printk. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-au1x00/au1000.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index c2e233997b6c..e11756d9aaa2 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -161,6 +161,25 @@ static inline int alchemy_get_cputype(void) return ALCHEMY_CPU_UNKNOWN; } +static inline void alchemy_uart_putchar(u32 uart_phys, u8 c) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys); + int timeout, i; + + /* check LSR TX_EMPTY bit */ + timeout = 0xffffff; + do { + if (__raw_readl(base + 0x1c) & 0x20) + break; + /* slow down */ + for (i = 10000; i; i--) + asm volatile ("nop"); + } while (--timeout); + + __raw_writel(c, base + 0x04); /* tx */ + wmb(); +} + /* arch/mips/au1000/common/clocks.c */ extern void set_au1x00_speed(unsigned int new_freq); extern unsigned int get_au1x00_speed(void); -- cgit v1.2.2 From b6e6d120c8dd9c9cd888645b01299e2a55d873a4 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Thu, 15 Oct 2009 19:07:34 +0200 Subject: MIPS: Alchemy: get rid of superfluous UART definitions Remove unused uart bit definitions and base macros. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-au1x00/au1000.h | 92 ------------------------------ 1 file changed, 92 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index e11756d9aaa2..2c524a87ecb6 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -916,8 +916,6 @@ enum soc_au1200_ints { #ifdef CONFIG_SOC_AU1000 #define UART0_ADDR 0xB1100000 -#define UART1_ADDR 0xB1200000 -#define UART2_ADDR 0xB1300000 #define UART3_ADDR 0xB1400000 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ @@ -952,7 +950,6 @@ enum soc_au1200_ints { #ifdef CONFIG_SOC_AU1100 #define UART0_ADDR 0xB1100000 -#define UART1_ADDR 0xB1200000 #define UART3_ADDR 0xB1400000 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ @@ -966,8 +963,6 @@ enum soc_au1200_ints { #ifdef CONFIG_SOC_AU1550 #define UART0_ADDR 0xB1100000 -#define UART1_ADDR 0xB1200000 -#define UART3_ADDR 0xB1400000 #define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */ #define USB_OHCI_LEN 0x00060000 @@ -985,7 +980,6 @@ enum soc_au1200_ints { #ifdef CONFIG_SOC_AU1200 #define UART0_ADDR 0xB1100000 -#define UART1_ADDR 0xB1200000 #define USB_UOC_BASE 0x14020020 #define USB_UOC_LEN 0x20 @@ -1262,14 +1256,6 @@ enum soc_au1200_ints { #define MAC_RX_BUFF3_STATUS 0x30 #define MAC_RX_BUFF3_ADDR 0x34 -/* UARTS 0-3 */ -#define UART_BASE UART0_ADDR -#ifdef CONFIG_SOC_AU1200 -#define UART_DEBUG_BASE UART1_ADDR -#else -#define UART_DEBUG_BASE UART3_ADDR -#endif - #define UART_RX 0 /* Receive buffer */ #define UART_TX 4 /* Transmit buffer */ #define UART_IER 8 /* Interrupt Enable Register */ @@ -1282,84 +1268,6 @@ enum soc_au1200_ints { #define UART_CLK 0x28 /* Baud Rate Clock Divider */ #define UART_MOD_CNTRL 0x100 /* Module Control */ -#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ -#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ -#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ -#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ -#define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */ -#define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */ -#define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */ -#define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */ -#define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */ -#define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */ -#define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */ -#define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */ -#define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */ - -/* - * These are the definitions for the Line Control Register - */ -#define UART_LCR_SBC 0x40 /* Set break control */ -#define UART_LCR_SPAR 0x20 /* Stick parity (?) */ -#define UART_LCR_EPAR 0x10 /* Even parity select */ -#define UART_LCR_PARITY 0x08 /* Parity Enable */ -#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ -#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ -#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ -#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ -#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ - -/* - * These are the definitions for the Line Status Register - */ -#define UART_LSR_TEMT 0x40 /* Transmitter empty */ -#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ -#define UART_LSR_BI 0x10 /* Break interrupt indicator */ -#define UART_LSR_FE 0x08 /* Frame error indicator */ -#define UART_LSR_PE 0x04 /* Parity error indicator */ -#define UART_LSR_OE 0x02 /* Overrun error indicator */ -#define UART_LSR_DR 0x01 /* Receiver data ready */ - -/* - * These are the definitions for the Interrupt Identification Register - */ -#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ -#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ -#define UART_IIR_MSI 0x00 /* Modem status interrupt */ -#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ -#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ -#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ - -/* - * These are the definitions for the Interrupt Enable Register - */ -#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ -#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ -#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ -#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ - -/* - * These are the definitions for the Modem Control Register - */ -#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ -#define UART_MCR_OUT2 0x08 /* Out2 complement */ -#define UART_MCR_OUT1 0x04 /* Out1 complement */ -#define UART_MCR_RTS 0x02 /* RTS complement */ -#define UART_MCR_DTR 0x01 /* DTR complement */ - -/* - * These are the definitions for the Modem Status Register - */ -#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ -#define UART_MSR_RI 0x40 /* Ring Indicator */ -#define UART_MSR_DSR 0x20 /* Data Set Ready */ -#define UART_MSR_CTS 0x10 /* Clear to Send */ -#define UART_MSR_DDCD 0x08 /* Delta DCD */ -#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ -#define UART_MSR_DDSR 0x02 /* Delta DSR */ -#define UART_MSR_DCTS 0x01 /* Delta CTS */ -#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ - /* SSIO */ #define SSI0_STATUS 0xB1600000 # define SSI_STATUS_BF (1 << 4) -- cgit v1.2.2 From 66a1d9baf4962defb3fc41439e3a22e752182f9f Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Thu, 15 Oct 2009 19:32:01 +0200 Subject: MIPS: Alchemy: remove unused SYS area structure Nothing in-tree uses it, so get rid of it. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-au1x00/au1000.h | 49 ------------------------------ 1 file changed, 49 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 2c524a87ecb6..088c8e0f43bb 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -1692,53 +1692,4 @@ enum soc_au1200_ints { #define PCMCIA_MEM_PSEUDO_PHYS (PCMCIA_MEM_PHYS_ADDR >> 4) #define PCMCIA_PSEUDO_END (0xffffffff) -#ifndef _LANGUAGE_ASSEMBLY -typedef volatile struct { - /* 0x0000 */ u32 toytrim; - /* 0x0004 */ u32 toywrite; - /* 0x0008 */ u32 toymatch0; - /* 0x000C */ u32 toymatch1; - /* 0x0010 */ u32 toymatch2; - /* 0x0014 */ u32 cntrctrl; - /* 0x0018 */ u32 scratch0; - /* 0x001C */ u32 scratch1; - /* 0x0020 */ u32 freqctrl0; - /* 0x0024 */ u32 freqctrl1; - /* 0x0028 */ u32 clksrc; - /* 0x002C */ u32 pinfunc; - /* 0x0030 */ u32 reserved0; - /* 0x0034 */ u32 wakemsk; - /* 0x0038 */ u32 endian; - /* 0x003C */ u32 powerctrl; - /* 0x0040 */ u32 toyread; - /* 0x0044 */ u32 rtctrim; - /* 0x0048 */ u32 rtcwrite; - /* 0x004C */ u32 rtcmatch0; - /* 0x0050 */ u32 rtcmatch1; - /* 0x0054 */ u32 rtcmatch2; - /* 0x0058 */ u32 rtcread; - /* 0x005C */ u32 wakesrc; - /* 0x0060 */ u32 cpupll; - /* 0x0064 */ u32 auxpll; - /* 0x0068 */ u32 reserved1; - /* 0x006C */ u32 reserved2; - /* 0x0070 */ u32 reserved3; - /* 0x0074 */ u32 reserved4; - /* 0x0078 */ u32 slppwr; - /* 0x007C */ u32 sleep; - /* 0x0080 */ u32 reserved5[32]; - /* 0x0100 */ u32 trioutrd; -#define trioutclr trioutrd - /* 0x0104 */ u32 reserved6; - /* 0x0108 */ u32 outputrd; -#define outputset outputrd - /* 0x010C */ u32 outputclr; - /* 0x0110 */ u32 pinstaterd; -#define pininputen pinstaterd -} AU1X00_SYS; - -static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE; - -#endif - #endif -- cgit v1.2.2 From 63323ec54a7e922a232c82070727e44eb1a5b43c Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Mon, 2 Nov 2009 21:21:43 +0100 Subject: MIPS: Alchemy: Extended DB1200 board support. Create own directory for DB1200 code and update it with new features. - SPI support: - tmp121 temperature sensor - SPI flash on DB1200 - I2C support - NE1619 sensor - AT24 eeprom - I2C/SPI can be selected at boot time via switch S6.8 - Carddetect IRQs for SD cards. - gen_nand based NAND support. - hexleds count sleep/wake transitions. Signed-off-by: Manuel Lauss Cc: Linux-MIPS Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-db1x00/db1200.h | 33 +++++------------------------- 1 file changed, 5 insertions(+), 28 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h index 52b1d84a92c7..3404248f5094 100644 --- a/arch/mips/include/asm/mach-db1x00/db1200.h +++ b/arch/mips/include/asm/mach-db1x00/db1200.h @@ -28,24 +28,6 @@ #include #include -#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX -#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX - -/* - * SPI and SMB are muxed on the DBAu1200 board. - * Refer to board documentation. - */ -#define SPI_PSC_BASE PSC0_BASE_ADDR -#define SMBUS_PSC_BASE PSC0_BASE_ADDR -/* - * AC'97 and I2S are muxed on the DBAu1200 board. - * Refer to board documentation. - */ -#define AC97_PSC_BASE PSC1_BASE_ADDR -#define I2S_PSC_BASE PSC1_BASE_ADDR - /* Bit positions for the different interrupt sources */ #define BCSR_INT_IDE 0x0001 #define BCSR_INT_ETH 0x0002 @@ -62,17 +44,15 @@ #define BCSR_INT_SD0INSERT 0x1000 #define BCSR_INT_SD0EJECT 0x2000 -#define SMC91C111_PHYS_ADDR 0x19000300 -#define SMC91C111_INT DB1200_ETH_INT - #define IDE_PHYS_ADDR 0x18800000 #define IDE_REG_SHIFT 5 -#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT) -#define IDE_INT DB1200_IDE_INT #define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 #define IDE_RQSIZE 128 -#define NAND_PHYS_ADDR 0x20000000 +#define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR +#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT) +#define DB1200_ETH_PHYS_ADDR 0x19000300 +#define DB1200_NAND_PHYS_ADDR 0x20000000 /* * External Interrupts for DBAu1200 as of 8/6/2004. @@ -82,7 +62,7 @@ * Example: IDE bis pos is = 64 - 64 * ETH bit pos is = 65 - 64 */ -enum external_pb1200_ints { +enum external_db1200_ints { DB1200_INT_BEGIN = AU1000_MAX_INTR + 1, DB1200_IDE_INT = DB1200_INT_BEGIN, @@ -103,7 +83,4 @@ enum external_pb1200_ints { DB1200_INT_END = DB1200_INT_BEGIN + 15, }; -/* NAND chip select */ -#define NAND_CS 1 - #endif /* __ASM_DB1200_H */ -- cgit v1.2.2 From 66f75ccb856304c190fde9c26e651c2b754e3e72 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 10 Nov 2009 01:13:30 +0100 Subject: MIPS: Alchemy: Add au1000-eth platform device This patch makes the board code register the au1000-eth platform device. The au1000-eth platform data can be overriden with the au1xxx_override_eth_cfg function like it has to be done for the Bosporus board which uses a different MAC/PHY setup. Signed-off-by: Florian Fainelli Cc: David Miller Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Patchwork: http://patchwork.linux-mips.org/patch/618/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-au1x00/au1xxx_eth.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 arch/mips/include/asm/mach-au1x00/au1xxx_eth.h (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h new file mode 100644 index 000000000000..bae9b758fcde --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h @@ -0,0 +1,17 @@ +#ifndef __AU1X00_ETH_DATA_H +#define __AU1X00_ETH_DATA_H + +/* Platform specific PHY configuration passed to the MAC driver */ +struct au1000_eth_platform_data { + int phy_static_config; + int phy_search_highest_addr; + int phy1_search_mac0; + int phy_addr; + int phy_busid; + int phy_irq; +}; + +void __init au1xxx_override_eth_cfg(unsigned port, + struct au1000_eth_platform_data *eth_data); + +#endif /* __AU1X00_ETH_DATA_H */ -- cgit v1.2.2 From 70f82f2c59be86fad915a2ee62673fe1aad6c2bd Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Mon, 23 Nov 2009 20:40:00 +0100 Subject: MIPS: Alchemy: use runtime cpu detection in GPIO code. Remove the cpu subtype cpp macros in favor of runtime detection, to improve compile coverage of the alchemy common code. (Increases kernel size by 700 bytes). Signed-off-by: Manuel Lauss Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/699/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-au1x00/gpio-au1000.h | 90 +++++++++++++------------ 1 file changed, 48 insertions(+), 42 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h index 9cf32d9dbb21..62d2f136d941 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h @@ -236,19 +236,19 @@ static inline int alchemy_gpio1_is_valid(int gpio) static inline int alchemy_gpio1_to_irq(int gpio) { -#if defined(CONFIG_SOC_AU1000) - return au1000_gpio1_to_irq(gpio); -#elif defined(CONFIG_SOC_AU1100) - return au1100_gpio1_to_irq(gpio); -#elif defined(CONFIG_SOC_AU1500) - return au1500_gpio1_to_irq(gpio); -#elif defined(CONFIG_SOC_AU1550) - return au1550_gpio1_to_irq(gpio); -#elif defined(CONFIG_SOC_AU1200) - return au1200_gpio1_to_irq(gpio); -#else + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000: + return au1000_gpio1_to_irq(gpio); + case ALCHEMY_CPU_AU1100: + return au1100_gpio1_to_irq(gpio); + case ALCHEMY_CPU_AU1500: + return au1500_gpio1_to_irq(gpio); + case ALCHEMY_CPU_AU1550: + return au1550_gpio1_to_irq(gpio); + case ALCHEMY_CPU_AU1200: + return au1200_gpio1_to_irq(gpio); + } return -ENXIO; -#endif } /* @@ -306,19 +306,19 @@ static inline int alchemy_gpio2_is_valid(int gpio) static inline int alchemy_gpio2_to_irq(int gpio) { -#if defined(CONFIG_SOC_AU1000) - return au1000_gpio2_to_irq(gpio); -#elif defined(CONFIG_SOC_AU1100) - return au1100_gpio2_to_irq(gpio); -#elif defined(CONFIG_SOC_AU1500) - return au1500_gpio2_to_irq(gpio); -#elif defined(CONFIG_SOC_AU1550) - return au1550_gpio2_to_irq(gpio); -#elif defined(CONFIG_SOC_AU1200) - return au1200_gpio2_to_irq(gpio); -#else + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000: + return au1000_gpio2_to_irq(gpio); + case ALCHEMY_CPU_AU1100: + return au1100_gpio2_to_irq(gpio); + case ALCHEMY_CPU_AU1500: + return au1500_gpio2_to_irq(gpio); + case ALCHEMY_CPU_AU1550: + return au1550_gpio2_to_irq(gpio); + case ALCHEMY_CPU_AU1200: + return au1200_gpio2_to_irq(gpio); + } return -ENXIO; -#endif } /**********************************************************************/ @@ -374,10 +374,13 @@ static inline void alchemy_gpio2_enable_int(int gpio2) gpio2 -= ALCHEMY_GPIO2_BASE; -#if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500) /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */ - gpio2 -= 8; -#endif + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1100: + case ALCHEMY_CPU_AU1500: + gpio2 -= 8; + } + local_irq_save(flags); __alchemy_gpio2_mod_int(gpio2, 1); local_irq_restore(flags); @@ -395,10 +398,13 @@ static inline void alchemy_gpio2_disable_int(int gpio2) gpio2 -= ALCHEMY_GPIO2_BASE; -#if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500) /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */ - gpio2 -= 8; -#endif + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1100: + case ALCHEMY_CPU_AU1500: + gpio2 -= 8; + } + local_irq_save(flags); __alchemy_gpio2_mod_int(gpio2, 0); local_irq_restore(flags); @@ -484,19 +490,19 @@ static inline int alchemy_gpio_to_irq(int gpio) static inline int alchemy_irq_to_gpio(int irq) { -#if defined(CONFIG_SOC_AU1000) - return au1000_irq_to_gpio(irq); -#elif defined(CONFIG_SOC_AU1100) - return au1100_irq_to_gpio(irq); -#elif defined(CONFIG_SOC_AU1500) - return au1500_irq_to_gpio(irq); -#elif defined(CONFIG_SOC_AU1550) - return au1550_irq_to_gpio(irq); -#elif defined(CONFIG_SOC_AU1200) - return au1200_irq_to_gpio(irq); -#else + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000: + return au1000_irq_to_gpio(irq); + case ALCHEMY_CPU_AU1100: + return au1100_irq_to_gpio(irq); + case ALCHEMY_CPU_AU1500: + return au1500_irq_to_gpio(irq); + case ALCHEMY_CPU_AU1550: + return au1550_irq_to_gpio(irq); + case ALCHEMY_CPU_AU1200: + return au1200_irq_to_gpio(irq); + } return -ENXIO; -#endif } /**********************************************************************/ -- cgit v1.2.2 From 5d400f5c59df3ed2c3682a7409c8e81a7c4e650c Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Mon, 23 Nov 2009 20:40:01 +0100 Subject: MIPS: Alchemy: Only build AU1000 INTC code for compatible cpus Use the GPIO config symbol to only build Au1000 interrupt code on chips with compatible hw. Signed-off-by: Manuel Lauss Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/670/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-au1x00/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h index f9b7d41c659a..c3f60cdc3203 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio.h +++ b/arch/mips/include/asm/mach-au1x00/gpio.h @@ -1,7 +1,7 @@ #ifndef _ALCHEMY_GPIO_H_ #define _ALCHEMY_GPIO_H_ -#if defined(CONFIG_ALCHEMY_GPIO_AU1000) +#if defined(CONFIG_ALCHEMY_GPIOINT_AU1000) #include -- cgit v1.2.2 From 325f8a0a31df567dbafafc48f8e60f3c1f101a46 Mon Sep 17 00:00:00 2001 From: David Daney Date: Fri, 4 Dec 2009 13:52:36 -0800 Subject: MIPS: Two-level pagetables for 64-bit kernels with 64KB pages. For 64-bit kernels with 64KB pages and two level page tables, there are 42 bits worth of virtual address space This is larger than the 40 bits of virtual address space obtained with the default 4KB Page size and three levels, so there are no draw backs for using two level tables with this configuration. Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/761/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/page.h | 12 ------------ arch/mips/include/asm/pgalloc.h | 4 ++-- arch/mips/include/asm/pgtable-64.h | 36 ++++++++++++++++++++++++++++++++++-- arch/mips/include/asm/pgtable.h | 2 +- 4 files changed, 37 insertions(+), 17 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h index f266295cce51..ac32572430f4 100644 --- a/arch/mips/include/asm/page.h +++ b/arch/mips/include/asm/page.h @@ -106,18 +106,6 @@ typedef struct { unsigned long pte; } pte_t; #endif typedef struct page *pgtable_t; -/* - * For 3-level pagetables we defines these ourselves, for 2-level the - * definitions are supplied by . - */ -#ifdef CONFIG_64BIT - -typedef struct { unsigned long pmd; } pmd_t; -#define pmd_val(x) ((x).pmd) -#define __pmd(x) ((pmd_t) { (x) } ) - -#endif - /* * Right now we don't support 4-level pagetables, so all pud-related * definitions come from . diff --git a/arch/mips/include/asm/pgalloc.h b/arch/mips/include/asm/pgalloc.h index 3738f4b48cbd..881d18b4e298 100644 --- a/arch/mips/include/asm/pgalloc.h +++ b/arch/mips/include/asm/pgalloc.h @@ -31,7 +31,7 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, */ extern void pmd_init(unsigned long page, unsigned long pagetable); -#ifdef CONFIG_64BIT +#ifndef __PAGETABLE_PMD_FOLDED static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd) { @@ -104,7 +104,7 @@ do { \ tlb_remove_page((tlb), pte); \ } while (0) -#ifdef CONFIG_64BIT +#ifndef __PAGETABLE_PMD_FOLDED static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address) { diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h index 8eda30b467da..24314d21a708 100644 --- a/arch/mips/include/asm/pgtable-64.h +++ b/arch/mips/include/asm/pgtable-64.h @@ -16,7 +16,11 @@ #include #include +#ifdef CONFIG_PAGE_SIZE_64KB +#include +#else #include +#endif /* * Each address space has 2 4K pages as its page directory, giving 1024 @@ -37,13 +41,20 @@ * fault address - VMALLOC_START. */ + +/* PGDIR_SHIFT determines what a third-level page table entry can map */ +#ifdef __PAGETABLE_PMD_FOLDED +#define PGDIR_SHIFT (PAGE_SHIFT + PAGE_SHIFT + PTE_ORDER - 3) +#else + /* PMD_SHIFT determines the size of the area a second-level page table can map */ #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3)) #define PMD_SIZE (1UL << PMD_SHIFT) #define PMD_MASK (~(PMD_SIZE-1)) -/* PGDIR_SHIFT determines what a third-level page table entry can map */ + #define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3)) +#endif #define PGDIR_SIZE (1UL << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE-1)) @@ -92,12 +103,14 @@ #ifdef CONFIG_PAGE_SIZE_64KB #define PGD_ORDER 0 #define PUD_ORDER aieeee_attempt_to_allocate_pud -#define PMD_ORDER 0 +#define PMD_ORDER aieeee_attempt_to_allocate_pmd #define PTE_ORDER 0 #endif #define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t)) +#ifndef __PAGETABLE_PMD_FOLDED #define PTRS_PER_PMD ((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t)) +#endif #define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) #if PGDIR_SIZE >= TASK_SIZE @@ -122,15 +135,30 @@ #define pte_ERROR(e) \ printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) +#ifndef __PAGETABLE_PMD_FOLDED #define pmd_ERROR(e) \ printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) +#endif #define pgd_ERROR(e) \ printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) extern pte_t invalid_pte_table[PTRS_PER_PTE]; extern pte_t empty_bad_page_table[PTRS_PER_PTE]; + + +#ifndef __PAGETABLE_PMD_FOLDED +/* + * For 3-level pagetables we defines these ourselves, for 2-level the + * definitions are supplied by . + */ +typedef struct { unsigned long pmd; } pmd_t; +#define pmd_val(x) ((x).pmd) +#define __pmd(x) ((pmd_t) { (x) } ) + + extern pmd_t invalid_pmd_table[PTRS_PER_PMD]; extern pmd_t empty_bad_pmd_table[PTRS_PER_PMD]; +#endif /* * Empty pgd/pmd entries point to the invalid_pte_table. @@ -151,6 +179,7 @@ static inline void pmd_clear(pmd_t *pmdp) { pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); } +#ifndef __PAGETABLE_PMD_FOLDED /* * Empty pud entries point to the invalid_pmd_table. @@ -174,6 +203,7 @@ static inline void pud_clear(pud_t *pudp) { pud_val(*pudp) = ((unsigned long) invalid_pmd_table); } +#endif #define pte_page(x) pfn_to_page(pte_pfn(x)) @@ -198,6 +228,7 @@ static inline void pud_clear(pud_t *pudp) /* to find an entry in a page-table-directory */ #define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr)) +#ifndef __PAGETABLE_PMD_FOLDED static inline unsigned long pud_page_vaddr(pud_t pud) { return pud_val(pud); @@ -210,6 +241,7 @@ static inline pmd_t *pmd_offset(pud_t * pud, unsigned long address) { return (pmd_t *) pud_page_vaddr(*pud) + pmd_index(address); } +#endif /* Find an entry in the third-level page table.. */ #define __pte_offset(address) \ diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index 1854336e56a2..02335fda9e77 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h @@ -177,7 +177,7 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt */ #define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0) -#ifdef CONFIG_64BIT +#ifndef __PAGETABLE_PMD_FOLDED /* * (puds are folded into pgds so this doesn't get actually called, * but the define is needed for a generic inline function.) -- cgit v1.2.2 From d38760ccdf879a8648be53488227bf7fe597792d Mon Sep 17 00:00:00 2001 From: "Robert P. J. Day" Date: Thu, 31 Dec 2009 15:39:00 -0500 Subject: MIPS: Simplify param.h by using Signed-off-by: Robert P. J. Day To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/810/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/param.h | 17 +---------------- 1 file changed, 1 insertion(+), 16 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/param.h b/arch/mips/include/asm/param.h index 1d9bb8c5ab24..da3920fce9ad 100644 --- a/arch/mips/include/asm/param.h +++ b/arch/mips/include/asm/param.h @@ -9,23 +9,8 @@ #ifndef _ASM_PARAM_H #define _ASM_PARAM_H -#ifdef __KERNEL__ - -# define HZ CONFIG_HZ /* Internal kernel timer frequency */ -# define USER_HZ 100 /* .. some user interfaces are in "ticks" */ -# define CLOCKS_PER_SEC (USER_HZ) /* like times() */ -#endif - -#ifndef HZ -#define HZ 100 -#endif - #define EXEC_PAGESIZE 65536 -#ifndef NOGROUP -#define NOGROUP (-1) -#endif - -#define MAXHOSTNAMELEN 64 /* max length of hostname */ +#include #endif /* _ASM_PARAM_H */ -- cgit v1.2.2 From f41c3c1b3ed53440b37445712f8e1048a39d7001 Mon Sep 17 00:00:00 2001 From: David Daney Date: Thu, 7 Jan 2010 13:23:41 -0800 Subject: MIPS: Octeon: Add I2C platform device. Signed-off-by: David Daney To: linux-mips@linux-mips.org To: linux-i2c@vger.kernel.org To: ben-linux@fluff.org To: khali@linux-fr.org Cc: Rade Bozic Patchwork: http://patchwork.linux-mips.org/patch/847/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/octeon/octeon.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h index 4d0a8c61fc3e..ca6214b5ccb9 100644 --- a/arch/mips/include/asm/octeon/octeon.h +++ b/arch/mips/include/asm/octeon/octeon.h @@ -213,6 +213,11 @@ struct octeon_cf_data { int dma_engine; /* -1 for no DMA */ }; +struct octeon_i2c_data { + unsigned int sys_freq; + unsigned int i2c_freq; +}; + extern void octeon_write_lcd(const char *s); extern void octeon_check_cpu_bist(void); extern int octeon_get_boot_debug_flag(void); -- cgit v1.2.2 From ec5380c768864c7afd92aa886dd4bb6d38497a01 Mon Sep 17 00:00:00 2001 From: David Daney Date: Thu, 7 Jan 2010 14:33:30 -0800 Subject: MIPS: Remove unused macros from barrier.h The smp_llsc_rmb() and smp_llsc_wmb() macros are not used in the tree, remove them. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/848/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/barrier.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h index 8e9ac313ca3b..91785dc8e94e 100644 --- a/arch/mips/include/asm/barrier.h +++ b/arch/mips/include/asm/barrier.h @@ -149,7 +149,5 @@ do { var = value; smp_mb(); } while (0) #define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") -#define smp_llsc_rmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") -#define smp_llsc_wmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") #endif /* __ASM_BARRIER_H */ -- cgit v1.2.2 From f252ffd50c97dae87b45f1dbad24f71358ccfbd6 Mon Sep 17 00:00:00 2001 From: David Daney Date: Fri, 8 Jan 2010 17:17:43 -0800 Subject: MIPS: New macro smp_mb__before_llsc. Replace some instances of smp_llsc_mb() with a new macro smp_mb__before_llsc(). It is used before ll/sc sequences that are documented as needing write barrier semantics. The default implementation of smp_mb__before_llsc() is just smp_llsc_mb(), so there are no changes in semantics. Also simplify definition of smp_mb(), smp_rmb(), and smp_wmb() to be just barrier() in the non-SMP case. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/851/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/atomic.h | 16 ++++++++-------- arch/mips/include/asm/barrier.h | 15 +++++++++------ arch/mips/include/asm/bitops.h | 8 ++++---- arch/mips/include/asm/cmpxchg.h | 10 +++++----- arch/mips/include/asm/spinlock.h | 4 ++-- arch/mips/include/asm/system.h | 4 ++++ 6 files changed, 32 insertions(+), 25 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h index dd75d673447e..519197ede089 100644 --- a/arch/mips/include/asm/atomic.h +++ b/arch/mips/include/asm/atomic.h @@ -137,7 +137,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v) { int result; - smp_llsc_mb(); + smp_mb__before_llsc(); if (kernel_uses_llsc && R10000_LLSC_WAR) { int temp; @@ -189,7 +189,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) { int result; - smp_llsc_mb(); + smp_mb__before_llsc(); if (kernel_uses_llsc && R10000_LLSC_WAR) { int temp; @@ -249,7 +249,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) { int result; - smp_llsc_mb(); + smp_mb__before_llsc(); if (kernel_uses_llsc && R10000_LLSC_WAR) { int temp; @@ -516,7 +516,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v) { long result; - smp_llsc_mb(); + smp_mb__before_llsc(); if (kernel_uses_llsc && R10000_LLSC_WAR) { long temp; @@ -568,7 +568,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) { long result; - smp_llsc_mb(); + smp_mb__before_llsc(); if (kernel_uses_llsc && R10000_LLSC_WAR) { long temp; @@ -628,7 +628,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) { long result; - smp_llsc_mb(); + smp_mb__before_llsc(); if (kernel_uses_llsc && R10000_LLSC_WAR) { long temp; @@ -788,9 +788,9 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) * atomic*_return operations are serializing but not the non-*_return * versions. */ -#define smp_mb__before_atomic_dec() smp_llsc_mb() +#define smp_mb__before_atomic_dec() smp_mb__before_llsc() #define smp_mb__after_atomic_dec() smp_llsc_mb() -#define smp_mb__before_atomic_inc() smp_llsc_mb() +#define smp_mb__before_atomic_inc() smp_mb__before_llsc() #define smp_mb__after_atomic_inc() smp_llsc_mb() #include diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h index 91785dc8e94e..1a5a51c3e96f 100644 --- a/arch/mips/include/asm/barrier.h +++ b/arch/mips/include/asm/barrier.h @@ -131,23 +131,26 @@ #endif /* !CONFIG_CPU_HAS_WB */ #if defined(CONFIG_WEAK_ORDERING) && defined(CONFIG_SMP) -#define __WEAK_ORDERING_MB " sync \n" +#define smp_mb() __asm__ __volatile__("sync" : : :"memory") +#define smp_rmb() __asm__ __volatile__("sync" : : :"memory") +#define smp_wmb() __asm__ __volatile__("sync" : : :"memory") #else -#define __WEAK_ORDERING_MB " \n" +#define smp_mb() barrier() +#define smp_rmb() barrier() +#define smp_wmb() barrier() #endif + #if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP) #define __WEAK_LLSC_MB " sync \n" #else #define __WEAK_LLSC_MB " \n" #endif -#define smp_mb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory") -#define smp_rmb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory") -#define smp_wmb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory") - #define set_mb(var, value) \ do { var = value; smp_mb(); } while (0) #define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") +#define smp_mb__before_llsc() smp_llsc_mb() + #endif /* __ASM_BARRIER_H */ diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index 84a383806b2c..9255cfbee459 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -42,7 +42,7 @@ /* * clear_bit() doesn't provide any barrier for the compiler. */ -#define smp_mb__before_clear_bit() smp_llsc_mb() +#define smp_mb__before_clear_bit() smp_mb__before_llsc() #define smp_mb__after_clear_bit() smp_llsc_mb() /* @@ -258,7 +258,7 @@ static inline int test_and_set_bit(unsigned long nr, unsigned short bit = nr & SZLONG_MASK; unsigned long res; - smp_llsc_mb(); + smp_mb__before_llsc(); if (kernel_uses_llsc && R10000_LLSC_WAR) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); @@ -395,7 +395,7 @@ static inline int test_and_clear_bit(unsigned long nr, unsigned short bit = nr & SZLONG_MASK; unsigned long res; - smp_llsc_mb(); + smp_mb__before_llsc(); if (kernel_uses_llsc && R10000_LLSC_WAR) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); @@ -485,7 +485,7 @@ static inline int test_and_change_bit(unsigned long nr, unsigned short bit = nr & SZLONG_MASK; unsigned long res; - smp_llsc_mb(); + smp_mb__before_llsc(); if (kernel_uses_llsc && R10000_LLSC_WAR) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h index 815a438a268d..ed9aaaaf0749 100644 --- a/arch/mips/include/asm/cmpxchg.h +++ b/arch/mips/include/asm/cmpxchg.h @@ -72,14 +72,14 @@ */ extern void __cmpxchg_called_with_bad_pointer(void); -#define __cmpxchg(ptr, old, new, barrier) \ +#define __cmpxchg(ptr, old, new, pre_barrier, post_barrier) \ ({ \ __typeof__(ptr) __ptr = (ptr); \ __typeof__(*(ptr)) __old = (old); \ __typeof__(*(ptr)) __new = (new); \ __typeof__(*(ptr)) __res = 0; \ \ - barrier; \ + pre_barrier; \ \ switch (sizeof(*(__ptr))) { \ case 4: \ @@ -96,13 +96,13 @@ extern void __cmpxchg_called_with_bad_pointer(void); break; \ } \ \ - barrier; \ + post_barrier; \ \ __res; \ }) -#define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_llsc_mb()) -#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new, ) +#define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_mb__before_llsc(), smp_llsc_mb()) +#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new, , ) #define cmpxchg64(ptr, o, n) \ ({ \ diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h index 21ef9efbde43..5f16696eaa00 100644 --- a/arch/mips/include/asm/spinlock.h +++ b/arch/mips/include/asm/spinlock.h @@ -138,7 +138,7 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock) { int tmp; - smp_llsc_mb(); + smp_mb__before_llsc(); if (R10000_LLSC_WAR) { __asm__ __volatile__ ( @@ -305,7 +305,7 @@ static inline void arch_read_unlock(arch_rwlock_t *rw) { unsigned int tmp; - smp_llsc_mb(); + smp_mb__before_llsc(); if (R10000_LLSC_WAR) { __asm__ __volatile__( diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h index 83b5509e09e8..bb937ccfba1e 100644 --- a/arch/mips/include/asm/system.h +++ b/arch/mips/include/asm/system.h @@ -95,6 +95,8 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) { __u32 retval; + smp_mb__before_llsc(); + if (kernel_uses_llsc && R10000_LLSC_WAR) { unsigned long dummy; @@ -147,6 +149,8 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val) { __u64 retval; + smp_mb__before_llsc(); + if (kernel_uses_llsc && R10000_LLSC_WAR) { unsigned long dummy; -- cgit v1.2.2 From 6b07d38aaa520cee922fadfeaf90c97faf217045 Mon Sep 17 00:00:00 2001 From: David Daney Date: Fri, 8 Jan 2010 17:17:44 -0800 Subject: MIPS: Octeon: Use optimized memory barrier primitives. In order to achieve correct synchronization semantics, the Octeon port had defined CONFIG_WEAK_REORDERING_BEYOND_LLSC. This resulted in code that looks like: sync ll ... . . . sc ... . . sync The second SYNC was redundant, but harmless. Octeon has a SYNCW instruction that acts as a write-memory-barrier (due to an erratum in some parts two SYNCW are used). It is much faster than SYNC because it imposes ordering on the writes, but doesn't otherwise stall the execution pipeline. On Octeon, SYNC stalls execution until all preceeding writes are committed to the coherent memory system. Using: syncw;syncw ll . . . sc . . Has identical semantics to the first sequence, but is much faster. The SYNCW orders the writes, and the SC will not complete successfully until the write is committed to the coherent memory system. So at the end all preceeding writes have been committed. Since Octeon does not do speculative reads, this functions as a full barrier. The patch removes CONFIG_WEAK_REORDERING_BEYOND_LLSC, and substitutes SYNCW for SYNC in write-memory-barriers. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/850/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/barrier.h | 43 +++++++++++++++++++++++++++++------------ 1 file changed, 31 insertions(+), 12 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h index 1a5a51c3e96f..a2670a239e0c 100644 --- a/arch/mips/include/asm/barrier.h +++ b/arch/mips/include/asm/barrier.h @@ -88,12 +88,20 @@ : /* no output */ \ : "m" (*(int *)CKSEG1) \ : "memory") - -#define fast_wmb() __sync() -#define fast_rmb() __sync() -#define fast_mb() __sync() -#ifdef CONFIG_SGI_IP28 -#define fast_iob() \ +#ifdef CONFIG_CPU_CAVIUM_OCTEON +# define OCTEON_SYNCW_STR ".set push\n.set arch=octeon\nsyncw\nsyncw\n.set pop\n" +# define __syncw() __asm__ __volatile__(OCTEON_SYNCW_STR : : : "memory") + +# define fast_wmb() __syncw() +# define fast_rmb() barrier() +# define fast_mb() __sync() +# define fast_iob() do { } while (0) +#else /* ! CONFIG_CPU_CAVIUM_OCTEON */ +# define fast_wmb() __sync() +# define fast_rmb() __sync() +# define fast_mb() __sync() +# ifdef CONFIG_SGI_IP28 +# define fast_iob() \ __asm__ __volatile__( \ ".set push\n\t" \ ".set noreorder\n\t" \ @@ -104,13 +112,14 @@ : /* no output */ \ : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \ : "memory") -#else -#define fast_iob() \ +# else +# define fast_iob() \ do { \ __sync(); \ __fast_iob(); \ } while (0) -#endif +# endif +#endif /* CONFIG_CPU_CAVIUM_OCTEON */ #ifdef CONFIG_CPU_HAS_WB @@ -131,9 +140,15 @@ #endif /* !CONFIG_CPU_HAS_WB */ #if defined(CONFIG_WEAK_ORDERING) && defined(CONFIG_SMP) -#define smp_mb() __asm__ __volatile__("sync" : : :"memory") -#define smp_rmb() __asm__ __volatile__("sync" : : :"memory") -#define smp_wmb() __asm__ __volatile__("sync" : : :"memory") +# ifdef CONFIG_CPU_CAVIUM_OCTEON +# define smp_mb() __sync() +# define smp_rmb() barrier() +# define smp_wmb() __syncw() +# else +# define smp_mb() __asm__ __volatile__("sync" : : :"memory") +# define smp_rmb() __asm__ __volatile__("sync" : : :"memory") +# define smp_wmb() __asm__ __volatile__("sync" : : :"memory") +# endif #else #define smp_mb() barrier() #define smp_rmb() barrier() @@ -151,6 +166,10 @@ #define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") +#ifdef CONFIG_CPU_CAVIUM_OCTEON +#define smp_mb__before_llsc() smp_wmb() +#else #define smp_mb__before_llsc() smp_llsc_mb() +#endif #endif /* __ASM_BARRIER_H */ -- cgit v1.2.2 From eb11df472d8491fcb28534b59017e1b5465997fa Mon Sep 17 00:00:00 2001 From: Wu Zhangjin Date: Mon, 4 Jan 2010 17:16:48 +0800 Subject: MIPS: Loongson: Cleanup of the environment variables Changes: o Move bus_clock into prom_init_env() o Initialize the cpu_clock_freq to the default values for the correspoding processor revisions if no such environment variable passed by BIOS/Bootloader. Signed-off-by: Wu Zhangjin Cc: linux-mips@linux-mips.org Cc: yanh@lemote.com Cc: huhb@lemote.com Cc: zhangfx@lemote.com Patchwork: http://patchwork.linux-mips.org/patch/826/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-loongson/loongson.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index ee8bc8376972..a6eac0f93799 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -23,7 +23,7 @@ extern void mach_prepare_reboot(void); extern void mach_prepare_shutdown(void); /* environment arguments from bootloader */ -extern unsigned long bus_clock, cpu_clock_freq; +extern unsigned long cpu_clock_freq; extern unsigned long memsize, highmemsize; /* loongson-specific command line, env and memory initialization */ -- cgit v1.2.2 From f7a904dffe30a02636053d8022498ced7e44d31c Mon Sep 17 00:00:00 2001 From: Wu Zhangjin Date: Mon, 4 Jan 2010 17:16:51 +0800 Subject: MIPS: Loongson: Change the Email address of Wu Zhangjin Currently wuzj@lemote.com is not usable; change it to wuzhangjin@gmail.com. Signed-off-by: Wu Zhangjin Cc: linux-mips@linux-mips.org Cc: yanh@lemote.com Cc: huhb@lemote.com Cc: zhangfx@lemote.com Patchwork: http://patchwork.linux-mips.org/patch/829/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/ftrace.h | 2 +- arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h | 2 +- arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h | 2 +- arch/mips/include/asm/mach-loongson/loongson.h | 3 +-- arch/mips/include/asm/mach-loongson/machine.h | 4 ++-- arch/mips/include/asm/mach-loongson/mem.h | 2 +- arch/mips/include/asm/mach-loongson/pci.h | 13 +------------ 7 files changed, 8 insertions(+), 20 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/ftrace.h b/arch/mips/include/asm/ftrace.h index 3986cd8704f3..ce35c9af0c28 100644 --- a/arch/mips/include/asm/ftrace.h +++ b/arch/mips/include/asm/ftrace.h @@ -4,7 +4,7 @@ * more details. * * Copyright (C) 2009 DSLab, Lanzhou University, China - * Author: Wu Zhangjin + * Author: Wu Zhangjin */ #ifndef _ASM_MIPS_FTRACE_H diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h index 9947e57c91de..16210cedd929 100644 --- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2009 Wu Zhangjin + * Copyright (C) 2009 Wu Zhangjin * Copyright (C) 2009 Philippe Vachon * Copyright (C) 2009 Zhang Le * diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h index 6305bea7e18e..21c4ecedebe7 100644 --- a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h +++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h @@ -2,7 +2,7 @@ * the read/write interfaces for Virtual Support Module(VSM) * * Copyright (C) 2009 Lemote, Inc. - * Author: Wu Zhangjin + * Author: Wu Zhangjin */ #ifndef _CS5536_VSM_H diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index a6eac0f93799..1cf7b1401ee4 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -1,12 +1,11 @@ /* * Copyright (C) 2009 Lemote, Inc. - * Author: Wu Zhangjin + * Author: Wu Zhangjin * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. - * */ #ifndef __ASM_MACH_LOONGSON_LOONGSON_H diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h index acf8359cb135..43213388c174 100644 --- a/arch/mips/include/asm/mach-loongson/machine.h +++ b/arch/mips/include/asm/mach-loongson/machine.h @@ -1,6 +1,6 @@ /* - * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology - * Author: Wu Zhangjin + * Copyright (C) 2009 Lemote, Inc. + * Author: Wu Zhangjin * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the diff --git a/arch/mips/include/asm/mach-loongson/mem.h b/arch/mips/include/asm/mach-loongson/mem.h index e9960f341b96..3b23ee8647d6 100644 --- a/arch/mips/include/asm/mach-loongson/mem.h +++ b/arch/mips/include/asm/mach-loongson/mem.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2009 Lemote, Inc. - * Author: Wu Zhangjin + * Author: Wu Zhangjin * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the diff --git a/arch/mips/include/asm/mach-loongson/pci.h b/arch/mips/include/asm/mach-loongson/pci.h index a199a4f6de4e..bc99dab4ef63 100644 --- a/arch/mips/include/asm/mach-loongson/pci.h +++ b/arch/mips/include/asm/mach-loongson/pci.h @@ -1,23 +1,12 @@ /* * Copyright (c) 2008 Zhang Le - * Copyright (c) 2009 Wu Zhangjin + * Copyright (c) 2009 Wu Zhangjin * * This program is free software; you can redistribute it * and/or modify it under the terms of the GNU General * Public License as published by the Free Software * Foundation; either version 2 of the License, or (at your * option) any later version. - * - * This program is distributed in the hope that it will be - * useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR - * PURPOSE. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public - * License along with this program; if not, write to the Free - * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA - * 02139, USA. */ #ifndef __ASM_MACH_LOONGSON_PCI_H_ -- cgit v1.2.2 From f868ba29723be46e0981226d7455090d515b08ef Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Wed, 16 Dec 2009 11:29:06 +0100 Subject: MIPS: add readl/write_be accessors MIPS currently lacks the readl_be and writel_be accessors which are required by BCM63xx for OHCI and EHCI support. Let's define them globally for MIPS. This also fixes the compilation of the bcm63xx defconfig against USB. Signed-off-by: Florian Fainelli Cc: Geert Uytterhoeven Cc: Thomas Bogendoerfer Cc: linux-mips@linux-mips.org Cc: Maxime Bizon Patchwork: http://patchwork.linux-mips.org/patch/793/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/io.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 436878e4e063..c98bf514ec7d 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -447,6 +447,24 @@ __BUILDIO(q, u64) #define readl_relaxed readl #define readq_relaxed readq +#define readb_be(addr) \ + __raw_readb((__force unsigned *)(addr)) +#define readw_be(addr) \ + be16_to_cpu(__raw_readw((__force unsigned *)(addr))) +#define readl_be(addr) \ + be32_to_cpu(__raw_readl((__force unsigned *)(addr))) +#define readq_be(addr) \ + be64_to_cpu(__raw_readq((__force unsigned *)(addr))) + +#define writeb_be(val, addr) \ + __raw_writeb((val), (__force unsigned *)(addr)) +#define writew_be(val, addr) \ + __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr)) +#define writel_be(val, addr) \ + __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr)) +#define writeq_be(val, addr) \ + __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr)) + /* * Some code tests for these symbols */ -- cgit v1.2.2 From 1b362e3e350f72c6cb4b3346f6ba92a529082a09 Mon Sep 17 00:00:00 2001 From: David Daney Date: Fri, 22 Jan 2010 14:41:15 -0800 Subject: MIPS: Decode c0_config4 for large TLBs. For processors that have more than 64 TLBs, we need to decode both config1 and config4 to determine the total number TLBs. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/866/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mipsregs.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index f4ab3139d737..edda1daf742f 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -576,6 +576,10 @@ #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) +#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) +#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) +#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) + #define MIPS_CONF7_WII (_ULCAST_(1) << 31) #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) -- cgit v1.2.2 From 2fe062608086f9b74a80f16272c5a59a3e05722f Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Wed, 20 Jan 2010 00:59:27 +0100 Subject: MIPS: Cleanup switches with cases that can be merged Signed-off-by: Roel Kluin To: linux-mips@linux-mips.org To: Andrew Morton To: LKML Patchwork: http://patchwork.linux-mips.org/patch/860/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/octeon/octeon-feature.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h index ef24a7b4ea57..cba6fbed9f43 100644 --- a/arch/mips/include/asm/octeon/octeon-feature.h +++ b/arch/mips/include/asm/octeon/octeon-feature.h @@ -99,6 +99,8 @@ static inline int octeon_has_feature(enum octeon_feature feature) return !cvmx_fuse_read(90); case OCTEON_FEATURE_PCIE: + case OCTEON_FEATURE_MGMT_PORT: + case OCTEON_FEATURE_RAID: return OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX); @@ -110,12 +112,6 @@ static inline int octeon_has_feature(enum octeon_feature feature) case OCTEON_FEATURE_TRA: return !(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)); - case OCTEON_FEATURE_MGMT_PORT: - return OCTEON_IS_MODEL(OCTEON_CN56XX) - || OCTEON_IS_MODEL(OCTEON_CN52XX); - case OCTEON_FEATURE_RAID: - return OCTEON_IS_MODEL(OCTEON_CN56XX) - || OCTEON_IS_MODEL(OCTEON_CN52XX); case OCTEON_FEATURE_USB: return !(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)); -- cgit v1.2.2 From e0e53dee69e07e9446eb16ceabd55a1116611696 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sat, 27 Feb 2010 12:53:14 +0100 Subject: MIPS: Nuke trailing blank lines Recent git versions now warn about those and they've always been a bit of an annoyance. Signed-off-by: Ralf Baechle --- arch/mips/include/asm/device.h | 1 - arch/mips/include/asm/mach-au1x00/au1100_mmc.h | 1 - arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 1 - arch/mips/include/asm/mach-pnx833x/irq-mapping.h | 1 - arch/mips/include/asm/mach-powertv/interrupts.h | 1 - arch/mips/include/asm/msc01_ic.h | 1 - arch/mips/include/asm/nile4.h | 1 - arch/mips/include/asm/sibyte/bigsur.h | 1 - arch/mips/include/asm/sibyte/sb1250_ldt.h | 1 - arch/mips/include/asm/sn/klkernvars.h | 1 - arch/mips/include/asm/sparsemem.h | 1 - 11 files changed, 11 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/device.h b/arch/mips/include/asm/device.h index d8f9872b0e2d..06746c5e8099 100644 --- a/arch/mips/include/asm/device.h +++ b/arch/mips/include/asm/device.h @@ -4,4 +4,3 @@ * This file is released under the GPLv2 */ #include - diff --git a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h index c35e20918490..58fbe173ecde 100644 --- a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h +++ b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h @@ -205,4 +205,3 @@ struct au1xmmc_platform_data { #endif /* __ASM_AU1100_MMC_H */ - diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index ed4ccec87dd4..85fd27509aac 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -770,4 +770,3 @@ #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT) #endif /* BCM63XX_REGS_H_ */ - diff --git a/arch/mips/include/asm/mach-pnx833x/irq-mapping.h b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h index 657f089b1724..6d70264557b2 100644 --- a/arch/mips/include/asm/mach-pnx833x/irq-mapping.h +++ b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h @@ -123,4 +123,3 @@ #define PNX833X_GPIO_15_INT (PNX833X_GPIO_IRQ_BASE + 15) #endif - diff --git a/arch/mips/include/asm/mach-powertv/interrupts.h b/arch/mips/include/asm/mach-powertv/interrupts.h index 629a57413657..4fd652ceb52a 100644 --- a/arch/mips/include/asm/mach-powertv/interrupts.h +++ b/arch/mips/include/asm/mach-powertv/interrupts.h @@ -251,4 +251,3 @@ * channel 3. */ #define irq_mpeg_d (ibase+0) /* MPEG Decoder Interrupt */ #endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */ - diff --git a/arch/mips/include/asm/msc01_ic.h b/arch/mips/include/asm/msc01_ic.h index 7989b9ffc1d2..d92406ae2841 100644 --- a/arch/mips/include/asm/msc01_ic.h +++ b/arch/mips/include/asm/msc01_ic.h @@ -145,4 +145,3 @@ extern void __init init_msc_irqs(unsigned long icubase, unsigned int base, msc_i extern void ll_msc_irq(void); #endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */ - diff --git a/arch/mips/include/asm/nile4.h b/arch/mips/include/asm/nile4.h index c3ca959aa4d9..af0e51a9f68a 100644 --- a/arch/mips/include/asm/nile4.h +++ b/arch/mips/include/asm/nile4.h @@ -307,4 +307,3 @@ extern u8 nile4_i8259_iack(void); extern void nile4_dump_irq_status(void); /* Debug */ #endif - diff --git a/arch/mips/include/asm/sibyte/bigsur.h b/arch/mips/include/asm/sibyte/bigsur.h index ebefe797fc1d..2d1a26d3436a 100644 --- a/arch/mips/include/asm/sibyte/bigsur.h +++ b/arch/mips/include/asm/sibyte/bigsur.h @@ -46,4 +46,3 @@ #endif #endif /* __ASM_SIBYTE_BIGSUR_H */ - diff --git a/arch/mips/include/asm/sibyte/sb1250_ldt.h b/arch/mips/include/asm/sibyte/sb1250_ldt.h index 081e8b1c4ad0..1e76cf137995 100644 --- a/arch/mips/include/asm/sibyte/sb1250_ldt.h +++ b/arch/mips/include/asm/sibyte/sb1250_ldt.h @@ -420,4 +420,3 @@ #endif /* 1250 PASS2 || 112x PASS1 */ #endif - diff --git a/arch/mips/include/asm/sn/klkernvars.h b/arch/mips/include/asm/sn/klkernvars.h index 5de4c5e8ab30..6af25ba41ade 100644 --- a/arch/mips/include/asm/sn/klkernvars.h +++ b/arch/mips/include/asm/sn/klkernvars.h @@ -26,4 +26,3 @@ typedef struct kern_vars_s { #endif /* !__ASSEMBLY__ */ #endif /* __ASM_SN_KLKERNVARS_H */ - diff --git a/arch/mips/include/asm/sparsemem.h b/arch/mips/include/asm/sparsemem.h index 795ac6c23203..7165333ad043 100644 --- a/arch/mips/include/asm/sparsemem.h +++ b/arch/mips/include/asm/sparsemem.h @@ -11,4 +11,3 @@ #endif /* CONFIG_SPARSEMEM */ #endif /* _MIPS_SPARSEMEM_H */ - -- cgit v1.2.2 From 69b427cd23b6f637763bf49e3e166c1236313f69 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Tue, 26 Jan 2010 18:02:58 +0900 Subject: MIPS: msp71xx: remove unused prom_getcmdline() Signed-off-by: Yoichi Yuasa Cc: linux-mips Patchwork: http://patchwork.linux-mips.org/patch/868/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h index 14ca7dc382a8..54ef1a96d7ce 100644 --- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h +++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h @@ -118,7 +118,6 @@ #define ZSP_DUET 'D' /* one DUET zsp engine */ #define ZSP_TRIAD 'T' /* two TRIAD zsp engines */ -extern char *prom_getcmdline(void); extern char *prom_getenv(char *name); extern void prom_init_cmdline(void); extern void prom_meminit(void); -- cgit v1.2.2 From 5f3c909881d5deebb9a3ddc836a15937e76daefc Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Sun, 3 Jan 2010 21:16:51 +0100 Subject: MIPS: AR7: Implement gpiolib This patch implements gpiolib for the AR7 SoC. Signed-off-by: Florian Fainelli To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/816/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-ar7/gpio.h | 86 ++++------------------------------- 1 file changed, 8 insertions(+), 78 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-ar7/gpio.h b/arch/mips/include/asm/mach-ar7/gpio.h index cbe9c4f126df..73f9b162c970 100644 --- a/arch/mips/include/asm/mach-ar7/gpio.h +++ b/arch/mips/include/asm/mach-ar7/gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007 Florian Fainelli + * Copyright (C) 2007-2009 Florian Fainelli * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,88 +22,18 @@ #include #define AR7_GPIO_MAX 32 +#define NR_BUILTIN_GPIO AR7_GPIO_MAX -extern int gpio_request(unsigned gpio, const char *label); -extern void gpio_free(unsigned gpio); +#define gpio_to_irq(gpio) NULL -/* Common GPIO layer */ -static inline int gpio_get_value(unsigned gpio) -{ - void __iomem *gpio_in = - (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_INPUT); +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value - return readl(gpio_in) & (1 << gpio); -} - -static inline void gpio_set_value(unsigned gpio, int value) -{ - void __iomem *gpio_out = - (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_OUTPUT); - unsigned tmp; - - tmp = readl(gpio_out) & ~(1 << gpio); - if (value) - tmp |= 1 << gpio; - writel(tmp, gpio_out); -} - -static inline int gpio_direction_input(unsigned gpio) -{ - void __iomem *gpio_dir = - (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR); - - if (gpio >= AR7_GPIO_MAX) - return -EINVAL; - - writel(readl(gpio_dir) | (1 << gpio), gpio_dir); - - return 0; -} - -static inline int gpio_direction_output(unsigned gpio, int value) -{ - void __iomem *gpio_dir = - (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR); - - if (gpio >= AR7_GPIO_MAX) - return -EINVAL; - - gpio_set_value(gpio, value); - writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir); - - return 0; -} - -static inline int gpio_to_irq(unsigned gpio) -{ - return -EINVAL; -} - -static inline int irq_to_gpio(unsigned irq) -{ - return -EINVAL; -} +#define gpio_cansleep __gpio_cansleep /* Board specific GPIO functions */ -static inline int ar7_gpio_enable(unsigned gpio) -{ - void __iomem *gpio_en = - (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE); - - writel(readl(gpio_en) | (1 << gpio), gpio_en); - - return 0; -} - -static inline int ar7_gpio_disable(unsigned gpio) -{ - void __iomem *gpio_en = - (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE); - - writel(readl(gpio_en) & ~(1 << gpio), gpio_en); - - return 0; -} +int ar7_gpio_enable(unsigned gpio); +int ar7_gpio_disable(unsigned gpio); #include -- cgit v1.2.2 From 780019ddf02f214ad61e641b57b8ac30c837e2a7 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Wed, 27 Jan 2010 09:10:06 +0100 Subject: MIPS: AR7: Implement clock API This patch makes the ar7 clock code implement the Linux clk API. Drivers using the various clocks available in the SoC are updated accordingly. Signed-off-by: Florian Fainelli Acked-by: Wim Van Sebroeck To: linux-mips@linux-mips.org Cc: Wim Van Sebroeck Cc: netdev@vger.kernel.org Cc: David Miller Patchwork: http://patchwork.linux-mips.org/patch/881/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-ar7/ar7.h | 23 +++-------------------- 1 file changed, 3 insertions(+), 20 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-ar7/ar7.h b/arch/mips/include/asm/mach-ar7/ar7.h index 21cbbc706448..f1cf38943497 100644 --- a/arch/mips/include/asm/mach-ar7/ar7.h +++ b/arch/mips/include/asm/mach-ar7/ar7.h @@ -105,26 +105,9 @@ static inline u8 ar7_chip_rev(void) return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff; } -static inline int ar7_cpu_freq(void) -{ - return ar7_cpu_clock; -} - -static inline int ar7_bus_freq(void) -{ - return ar7_bus_clock; -} - -static inline int ar7_vbus_freq(void) -{ - return ar7_bus_clock / 2; -} -#define ar7_cpmac_freq ar7_vbus_freq - -static inline int ar7_dsp_freq(void) -{ - return ar7_dsp_clock; -} +struct clk { + unsigned int rate; +}; static inline int ar7_has_high_cpmac(void) { -- cgit v1.2.2 From 60ec6571c5072cdea9e518d1dac8147b85ca93a2 Mon Sep 17 00:00:00 2001 From: "pascal@pabr.org" Date: Sun, 3 Jan 2010 13:39:12 +0100 Subject: MIPS: Support 36-bit iomem on 32-bit Au1x00 I believe these changes are needed on Alchemy SoCs in order to use iomem above 4G with the usual platform_device machinery: - Set CONFIG_ARCH_PHYS_ADDR_T_64BIT to make resource_size_t 64-bit. - Increase IOMEM_RESOURCE_END so that platforms can register resources. To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/814/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-au1x00/au1000.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 088c8e0f43bb..2805fc56484d 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -1659,7 +1659,7 @@ enum soc_au1200_ints { #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ #define IOPORT_RESOURCE_END 0xffffffff #define IOMEM_RESOURCE_START 0x10000000 -#define IOMEM_RESOURCE_END 0xffffffff +#define IOMEM_RESOURCE_END 0xfffffffffULL #else /* Au1000 and Au1100 and Au1200 */ @@ -1667,7 +1667,7 @@ enum soc_au1200_ints { #define IOPORT_RESOURCE_START 0x10000000 #define IOPORT_RESOURCE_END 0xffffffff #define IOMEM_RESOURCE_START 0x10000000 -#define IOMEM_RESOURCE_END 0xffffffff +#define IOMEM_RESOURCE_END 0xfffffffffULL #define PCI_IO_START 0 #define PCI_IO_END 0 -- cgit v1.2.2 From 3482d713a91befb8c96722cb8d55aed36c212d9e Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 28 Jan 2010 15:21:24 +0100 Subject: MIPS: Move arch/mips/mm/uasm.h to arch/mips/include/asm/uasm.h Signed-off-by: Florian Fainelli To: linux-mips@linux-mips.org To: David Daney Patchwork: http://patchwork.linux-mips.org/patch/887/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/uasm.h | 191 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 191 insertions(+) create mode 100644 arch/mips/include/asm/uasm.h (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h new file mode 100644 index 000000000000..3d153edaa51e --- /dev/null +++ b/arch/mips/include/asm/uasm.h @@ -0,0 +1,191 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer + * Copyright (C) 2005 Maciej W. Rozycki + * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) + */ + +#include + +#define Ip_u1u2u3(op) \ +void __cpuinit \ +uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c) + +#define Ip_u2u1u3(op) \ +void __cpuinit \ +uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c) + +#define Ip_u3u1u2(op) \ +void __cpuinit \ +uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c) + +#define Ip_u1u2s3(op) \ +void __cpuinit \ +uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c) + +#define Ip_u2s3u1(op) \ +void __cpuinit \ +uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c) + +#define Ip_u2u1s3(op) \ +void __cpuinit \ +uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c) + +#define Ip_u2u1msbu3(op) \ +void __cpuinit \ +uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \ + unsigned int d) + +#define Ip_u1u2(op) \ +void __cpuinit uasm_i##op(u32 **buf, unsigned int a, unsigned int b) + +#define Ip_u1s2(op) \ +void __cpuinit uasm_i##op(u32 **buf, unsigned int a, signed int b) + +#define Ip_u1(op) void __cpuinit uasm_i##op(u32 **buf, unsigned int a) + +#define Ip_0(op) void __cpuinit uasm_i##op(u32 **buf) + +Ip_u2u1s3(_addiu); +Ip_u3u1u2(_addu); +Ip_u2u1u3(_andi); +Ip_u3u1u2(_and); +Ip_u1u2s3(_beq); +Ip_u1u2s3(_beql); +Ip_u1s2(_bgez); +Ip_u1s2(_bgezl); +Ip_u1s2(_bltz); +Ip_u1s2(_bltzl); +Ip_u1u2s3(_bne); +Ip_u2s3u1(_cache); +Ip_u1u2u3(_dmfc0); +Ip_u1u2u3(_dmtc0); +Ip_u2u1s3(_daddiu); +Ip_u3u1u2(_daddu); +Ip_u2u1u3(_dsll); +Ip_u2u1u3(_dsll32); +Ip_u2u1u3(_dsra); +Ip_u2u1u3(_dsrl); +Ip_u2u1u3(_dsrl32); +Ip_u2u1u3(_drotr); +Ip_u3u1u2(_dsubu); +Ip_0(_eret); +Ip_u1(_j); +Ip_u1(_jal); +Ip_u1(_jr); +Ip_u2s3u1(_ld); +Ip_u2s3u1(_ll); +Ip_u2s3u1(_lld); +Ip_u1s2(_lui); +Ip_u2s3u1(_lw); +Ip_u1u2u3(_mfc0); +Ip_u1u2u3(_mtc0); +Ip_u2u1u3(_ori); +Ip_u2s3u1(_pref); +Ip_0(_rfe); +Ip_u2s3u1(_sc); +Ip_u2s3u1(_scd); +Ip_u2s3u1(_sd); +Ip_u2u1u3(_sll); +Ip_u2u1u3(_sra); +Ip_u2u1u3(_srl); +Ip_u3u1u2(_subu); +Ip_u2s3u1(_sw); +Ip_0(_tlbp); +Ip_0(_tlbwi); +Ip_0(_tlbwr); +Ip_u3u1u2(_xor); +Ip_u2u1u3(_xori); +Ip_u2u1msbu3(_dins); + +/* Handle labels. */ +struct uasm_label { + u32 *addr; + int lab; +}; + +void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid); +#ifdef CONFIG_64BIT +int uasm_in_compat_space_p(long addr); +#endif +int uasm_rel_hi(long val); +int uasm_rel_lo(long val); +void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr); +void UASM_i_LA(u32 **buf, unsigned int rs, long addr); + +#define UASM_L_LA(lb) \ +static inline void __cpuinit uasm_l##lb(struct uasm_label **lab, u32 *addr) \ +{ \ + uasm_build_label(lab, addr, label##lb); \ +} + +/* convenience macros for instructions */ +#ifdef CONFIG_64BIT +# define UASM_i_LW(buf, rs, rt, off) uasm_i_ld(buf, rs, rt, off) +# define UASM_i_SW(buf, rs, rt, off) uasm_i_sd(buf, rs, rt, off) +# define UASM_i_SLL(buf, rs, rt, sh) uasm_i_dsll(buf, rs, rt, sh) +# define UASM_i_SRA(buf, rs, rt, sh) uasm_i_dsra(buf, rs, rt, sh) +# define UASM_i_SRL(buf, rs, rt, sh) uasm_i_dsrl(buf, rs, rt, sh) +# define UASM_i_MFC0(buf, rt, rd...) uasm_i_dmfc0(buf, rt, rd) +# define UASM_i_MTC0(buf, rt, rd...) uasm_i_dmtc0(buf, rt, rd) +# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_daddiu(buf, rs, rt, val) +# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_daddu(buf, rs, rt, rd) +# define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_dsubu(buf, rs, rt, rd) +# define UASM_i_LL(buf, rs, rt, off) uasm_i_lld(buf, rs, rt, off) +# define UASM_i_SC(buf, rs, rt, off) uasm_i_scd(buf, rs, rt, off) +#else +# define UASM_i_LW(buf, rs, rt, off) uasm_i_lw(buf, rs, rt, off) +# define UASM_i_SW(buf, rs, rt, off) uasm_i_sw(buf, rs, rt, off) +# define UASM_i_SLL(buf, rs, rt, sh) uasm_i_sll(buf, rs, rt, sh) +# define UASM_i_SRA(buf, rs, rt, sh) uasm_i_sra(buf, rs, rt, sh) +# define UASM_i_SRL(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh) +# define UASM_i_MFC0(buf, rt, rd...) uasm_i_mfc0(buf, rt, rd) +# define UASM_i_MTC0(buf, rt, rd...) uasm_i_mtc0(buf, rt, rd) +# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_addiu(buf, rs, rt, val) +# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_addu(buf, rs, rt, rd) +# define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_subu(buf, rs, rt, rd) +# define UASM_i_LL(buf, rs, rt, off) uasm_i_ll(buf, rs, rt, off) +# define UASM_i_SC(buf, rs, rt, off) uasm_i_sc(buf, rs, rt, off) +#endif + +#define uasm_i_b(buf, off) uasm_i_beq(buf, 0, 0, off) +#define uasm_i_beqz(buf, rs, off) uasm_i_beq(buf, rs, 0, off) +#define uasm_i_beqzl(buf, rs, off) uasm_i_beql(buf, rs, 0, off) +#define uasm_i_bnez(buf, rs, off) uasm_i_bne(buf, rs, 0, off) +#define uasm_i_bnezl(buf, rs, off) uasm_i_bnel(buf, rs, 0, off) +#define uasm_i_move(buf, a, b) UASM_i_ADDU(buf, a, 0, b) +#define uasm_i_nop(buf) uasm_i_sll(buf, 0, 0, 0) +#define uasm_i_ssnop(buf) uasm_i_sll(buf, 0, 0, 1) +#define uasm_i_ehb(buf) uasm_i_sll(buf, 0, 0, 3) + +/* Handle relocations. */ +struct uasm_reloc { + u32 *addr; + unsigned int type; + int lab; +}; + +/* This is zero so we can use zeroed label arrays. */ +#define UASM_LABEL_INVALID 0 + +void uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid); +void uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab); +void uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off); +void uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off); +void uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, + u32 *first, u32 *end, u32 *target); +int uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr); + +/* Convenience functions for labeled branches. */ +void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); +void uasm_il_b(u32 **p, struct uasm_reloc **r, int lid); +void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); +void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); +void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1, + unsigned int reg2, int lid); +void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); +void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); +void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); -- cgit v1.2.2 From 3b839070f11295735ce8d9ef580c5eb23417aabf Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Wed, 14 Oct 2009 09:38:06 +0200 Subject: MMC: AU1xMMC: Allow platforms to disable host capabilities Although the hardware supports a 4/8bit SD interface and the driver unconditionally advertises all hardware caps to the MMC core, not all datalines may actually be wired up. This patch introduces another field to au1xmmc platform data allowing platforms to disable certain advanced host controller features. Signed-off-by: Manuel Lauss To: linux-mmc@vger.kernel.org CC: Linux-MIPS Patchwork: http://patchwork.linux-mips.org/patch/460/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-au1x00/au1100_mmc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h index 58fbe173ecde..94000a3b6f0b 100644 --- a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h +++ b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h @@ -46,6 +46,7 @@ struct au1xmmc_platform_data { int(*card_readonly)(void *mmc_host); void(*set_power)(void *mmc_host, int state); struct led_classdev *led; + unsigned long mask_host_caps; }; #define SD0_BASE 0xB0600000 -- cgit v1.2.2 From 874fd3b5acc20f2a464409045aef3b2288069787 Mon Sep 17 00:00:00 2001 From: David Daney Date: Thu, 28 Jan 2010 16:52:12 -0800 Subject: MIPS: Allow the auxv's elf_platform entry to be set. The userspace runtime linker uses the elf_platform to find the libraries optimized for the current CPU archecture variant. First we need to allow it to be set to something other than NULL. Follow-on patches will set some values for specific CPUs. GLIBC already does the right thing. The kernel just needs to supply good data. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/891/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/elf.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h index 7a6a35dbe529..e53d7bed5cda 100644 --- a/arch/mips/include/asm/elf.h +++ b/arch/mips/include/asm/elf.h @@ -334,14 +334,14 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); #define ELF_HWCAP (0) -/* This yields a string that ld.so will use to load implementation - specific libraries for optimization. This is more specific in - intent than poking at uname or /proc/cpuinfo. - - For the moment, we have only optimizations for the Intel generations, - but that could change... */ +/* + * This yields a string that ld.so will use to load implementation + * specific libraries for optimization. This is more specific in + * intent than poking at uname or /proc/cpuinfo. + */ -#define ELF_PLATFORM (NULL) +#define ELF_PLATFORM __elf_platform +extern const char *__elf_platform; /* * See comments in asm-alpha/elf.h, this is the same thing -- cgit v1.2.2 From ae7cbef5e5789e2ee6855222a3b83eb94591ef0b Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Mon, 1 Feb 2010 22:05:57 +0900 Subject: MIPS: Alchemy: Remove prom_getcmdline() Signed-off-by: Yoichi Yuasa Cc: linux-mips Patchwork: http://patchwork.linux-mips.org/patch/927/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-au1x00/prom.h | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-au1x00/prom.h b/arch/mips/include/asm/mach-au1x00/prom.h index e38715577c51..4c0e09cf1735 100644 --- a/arch/mips/include/asm/mach-au1x00/prom.h +++ b/arch/mips/include/asm/mach-au1x00/prom.h @@ -6,7 +6,6 @@ extern char **prom_argv; extern char **prom_envp; extern void prom_init_cmdline(void); -extern char *prom_getcmdline(void); extern char *prom_getenv(char *envname); extern int prom_get_ethernet_addr(char *ethernet_addr); -- cgit v1.2.2 From ab4ba291683d07038c7ddf1eec191d3d09e1f468 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Tue, 2 Feb 2010 18:40:04 +0900 Subject: MIPS: TXx9: Remove forced serial console setting It is not always used, even if it is available. Signed-off-by: Yoichi Yuasa Cc: linux-mips Patchwork: http://patchwork.linux-mips.org/patch/933/ Acked-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/include/asm/txx9/generic.h | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/txx9/generic.h b/arch/mips/include/asm/txx9/generic.h index 827dc22be2ea..64887d3c7ec3 100644 --- a/arch/mips/include/asm/txx9/generic.h +++ b/arch/mips/include/asm/txx9/generic.h @@ -42,7 +42,6 @@ struct txx9_board_vec { }; extern struct txx9_board_vec *txx9_board_vec; extern int (*txx9_irq_dispatch)(int pending); -char *prom_getcmdline(void); const char *prom_getenv(const char *name); void txx9_wdt_init(unsigned long base); void txx9_wdt_now(unsigned long base); -- cgit v1.2.2 From 9fe2e9d6f5390d7151a0b9d8c100f0da26eaa2b7 Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 10 Feb 2010 15:12:45 -0800 Subject: MIPS: Add accessor functions and bit definitions for c0_PageGrain Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/950/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mipsregs.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index edda1daf742f..49382d5e891a 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -250,6 +250,14 @@ #define PL_64M 26 #define PL_256M 28 +/* + * PageGrain bits + */ +#define PG_RIE (_ULCAST_(1) << 31) +#define PG_XIE (_ULCAST_(1) << 30) +#define PG_ELPA (_ULCAST_(1) << 29) +#define PG_ESP (_ULCAST_(1) << 28) + /* * R4x00 interrupt enable / cause bits */ @@ -830,6 +838,9 @@ do { \ #define read_c0_pagemask() __read_32bit_c0_register($5, 0) #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) +#define read_c0_pagegrain() __read_32bit_c0_register($5, 1) +#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) + #define read_c0_wired() __read_32bit_c0_register($6, 0) #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) -- cgit v1.2.2 From 32546f38fab839eee6f62b3f06c2774eade4188a Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 10 Feb 2010 15:12:46 -0800 Subject: MIPS: Add TLBR and ROTR to uasm. The soon to follow Read Inhibit/eXecute Inhibit patch needs TLBR and ROTR support in uasm. We also add a UASM_i_ROTR macro. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/953/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/uasm.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 3d153edaa51e..b99bd07e199b 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -92,9 +92,11 @@ Ip_u2s3u1(_sd); Ip_u2u1u3(_sll); Ip_u2u1u3(_sra); Ip_u2u1u3(_srl); +Ip_u2u1u3(_rotr); Ip_u3u1u2(_subu); Ip_u2s3u1(_sw); Ip_0(_tlbp); +Ip_0(_tlbr); Ip_0(_tlbwi); Ip_0(_tlbwr); Ip_u3u1u2(_xor); @@ -129,6 +131,7 @@ static inline void __cpuinit uasm_l##lb(struct uasm_label **lab, u32 *addr) \ # define UASM_i_SLL(buf, rs, rt, sh) uasm_i_dsll(buf, rs, rt, sh) # define UASM_i_SRA(buf, rs, rt, sh) uasm_i_dsra(buf, rs, rt, sh) # define UASM_i_SRL(buf, rs, rt, sh) uasm_i_dsrl(buf, rs, rt, sh) +# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_drotr(buf, rs, rt, sh) # define UASM_i_MFC0(buf, rt, rd...) uasm_i_dmfc0(buf, rt, rd) # define UASM_i_MTC0(buf, rt, rd...) uasm_i_dmtc0(buf, rt, rd) # define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_daddiu(buf, rs, rt, val) @@ -142,6 +145,7 @@ static inline void __cpuinit uasm_l##lb(struct uasm_label **lab, u32 *addr) \ # define UASM_i_SLL(buf, rs, rt, sh) uasm_i_sll(buf, rs, rt, sh) # define UASM_i_SRA(buf, rs, rt, sh) uasm_i_sra(buf, rs, rt, sh) # define UASM_i_SRL(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh) +# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_rotr(buf, rs, rt, sh) # define UASM_i_MFC0(buf, rt, rd...) uasm_i_mfc0(buf, rt, rd) # define UASM_i_MTC0(buf, rt, rd...) uasm_i_mtc0(buf, rt, rd) # define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_addiu(buf, rs, rt, val) -- cgit v1.2.2 From 6dd9344cfc41bcc60a01cdc828cb278be7a10e01 Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 10 Feb 2010 15:12:47 -0800 Subject: MIPS: Implement Read Inhibit/eXecute Inhibit The SmartMIPS ASE specifies how Read Inhibit (RI) and eXecute Inhibit (XI) bits in the page tables work. The upper two bits of EntryLo{0,1} are RI and XI when the feature is enabled in the PageGrain register. SmartMIPS only covers 32-bit systems. Cavium Octeon+ extends this to 64-bit systems by continuing to place the RI and XI bits in the top of EntryLo even when EntryLo is 64-bits wide. Because we need to carry the RI and XI bits in the PTE, the layout of the PTE is changed. There is a two instruction overhead in the TLB refill hot path to get the EntryLo bits into the proper position. Also the TLB load exception has to probe the TLB to check if RI or XI caused the exception. Also of note is that the layout of the PTE bits is done at compile and runtime rather than statically. In the 32-bit case this allows for the same number of PFN bits as before the patch as the _PAGE_HUGE is not supported in 32-bit kernels (we have _PAGE_NO_EXEC and _PAGE_NO_READ instead of _PAGE_READ and _PAGE_HUGE). The patch is tested on Cavium Octeon+, but should also work on 32-bit systems with the Smart-MIPS ASE. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/952/ Patchwork: http://patchwork.linux-mips.org/patch/956/ Patchwork: http://patchwork.linux-mips.org/patch/962/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/cpu-features.h | 3 + arch/mips/include/asm/pgtable-32.h | 4 +- arch/mips/include/asm/pgtable-64.h | 4 +- arch/mips/include/asm/pgtable-bits.h | 120 ++++++++++++++++++++++++++++++----- arch/mips/include/asm/pgtable.h | 26 +++++--- 5 files changed, 128 insertions(+), 29 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 272c5ef35bbb..ac73cede3a0a 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -95,6 +95,9 @@ #ifndef cpu_has_smartmips #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) #endif +#ifndef kernel_uses_smartmips_rixi +#define kernel_uses_smartmips_rixi 0 +#endif #ifndef cpu_has_vtag_icache #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) #endif diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h index 55813d6150c7..ae90412556d0 100644 --- a/arch/mips/include/asm/pgtable-32.h +++ b/arch/mips/include/asm/pgtable-32.h @@ -127,8 +127,8 @@ pfn_pte(unsigned long pfn, pgprot_t prot) #define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2))) #define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot)) #else -#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) -#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) +#define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT)) +#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot)) #endif #endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */ diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h index 24314d21a708..26dc69d792a6 100644 --- a/arch/mips/include/asm/pgtable-64.h +++ b/arch/mips/include/asm/pgtable-64.h @@ -211,8 +211,8 @@ static inline void pud_clear(pud_t *pudp) #define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2))) #define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot)) #else -#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) -#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) +#define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT)) +#define pfn_pte(pfn, prot) __pte(((pfn) << _PFN_SHIFT) | pgprot_val(prot)) #endif #define __pgd_offset(address) pgd_index(address) diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index 1073e6df8621..e9fe7e97ce4c 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -50,7 +50,7 @@ #define _CACHE_SHIFT 3 #define _CACHE_MASK (7<<3) -#else +#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) #define _PAGE_PRESENT (1<<0) /* implemented in software */ #define _PAGE_READ (1<<1) /* implemented in software */ @@ -59,8 +59,6 @@ #define _PAGE_MODIFIED (1<<4) /* implemented in software */ #define _PAGE_FILE (1<<4) /* set:pagecache unset:swap */ -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) - #define _PAGE_GLOBAL (1<<8) #define _PAGE_VALID (1<<9) #define _PAGE_SILENT_READ (1<<9) /* synonym */ @@ -69,21 +67,113 @@ #define _CACHE_UNCACHED (1<<11) #define _CACHE_MASK (1<<11) +#else /* 'Normal' r4K case */ +/* + * When using the RI/XI bit support, we have 13 bits of flags below + * the physical address. The RI/XI bits are placed such that a SRL 5 + * can strip off the software bits, then a ROTR 2 can move the RI/XI + * into bits [63:62]. This also limits physical address to 56 bits, + * which is more than we need right now. + */ + +/* implemented in software */ +#define _PAGE_PRESENT_SHIFT (0) +#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) +/* implemented in software, should be unused if kernel_uses_smartmips_rixi. */ +#define _PAGE_READ_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1) +#define _PAGE_READ ({if (kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_READ_SHIFT; }) +/* implemented in software */ +#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) +#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) +/* implemented in software */ +#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) +#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) +/* implemented in software */ +#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) +#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) +/* set:pagecache unset:swap */ +#define _PAGE_FILE (_PAGE_MODIFIED) + +#ifdef CONFIG_HUGETLB_PAGE +/* huge tlb page */ +#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1) +#define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT) #else +#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT) +#define _PAGE_HUGE ({BUG(); 1; }) /* Dummy value */ +#endif -#define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */ -#define _PAGE_HUGE (1<<5) /* huge tlb page */ -#define _PAGE_GLOBAL (1<<6) -#define _PAGE_VALID (1<<7) -#define _PAGE_SILENT_READ (1<<7) /* synonym */ -#define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */ -#define _PAGE_SILENT_WRITE (1<<8) -#define _CACHE_SHIFT 9 -#define _CACHE_MASK (7<<9) +/* Page cannot be executed */ +#define _PAGE_NO_EXEC_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT) +#define _PAGE_NO_EXEC ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_EXEC_SHIFT; }) + +/* Page cannot be read */ +#define _PAGE_NO_READ_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT) +#define _PAGE_NO_READ ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_READ_SHIFT; }) + +#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) +#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) + +#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) +#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) +/* synonym */ +#define _PAGE_SILENT_READ (_PAGE_VALID) + +/* The MIPS dirty bit */ +#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) +#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) +#define _PAGE_SILENT_WRITE (_PAGE_DIRTY) + +#define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1) +#define _CACHE_MASK (7 << _CACHE_SHIFT) + +#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) -#endif #endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */ +#ifndef _PFN_SHIFT +#define _PFN_SHIFT PAGE_SHIFT +#endif +#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1)) + +#ifndef _PAGE_NO_READ +#define _PAGE_NO_READ ({BUG(); 0; }) +#define _PAGE_NO_READ_SHIFT ({BUG(); 0; }) +#endif +#ifndef _PAGE_NO_EXEC +#define _PAGE_NO_EXEC ({BUG(); 0; }) +#endif +#ifndef _PAGE_GLOBAL_SHIFT +#define _PAGE_GLOBAL_SHIFT ilog2(_PAGE_GLOBAL) +#endif + + +#ifndef __ASSEMBLY__ +/* + * pte_to_entrylo converts a page table entry (PTE) into a Mips + * entrylo0/1 value. + */ +static inline uint64_t pte_to_entrylo(unsigned long pte_val) +{ + if (kernel_uses_smartmips_rixi) { + int sa; +#ifdef CONFIG_32BIT + sa = 31 - _PAGE_NO_READ_SHIFT; +#else + sa = 63 - _PAGE_NO_READ_SHIFT; +#endif + /* + * C has no way to express that this is a DSRL + * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily + * in the fast path this is done in assembly + */ + return (pte_val >> _PAGE_GLOBAL_SHIFT) | + ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa); + } + + return pte_val >> _PAGE_GLOBAL_SHIFT; +} +#endif /* * Cache attributes @@ -130,9 +220,9 @@ #endif -#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) +#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ)) #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) -#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) +#define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) #endif /* _ASM_PGTABLE_BITS_H */ diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index 02335fda9e77..93598ba01355 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h @@ -22,23 +22,24 @@ struct mm_struct; struct vm_area_struct; #define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) -#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ +#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \ _page_cachable_default) -#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ - _page_cachable_default) -#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ +#define PAGE_COPY __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \ + (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC : 0) | _page_cachable_default) +#define PAGE_READONLY __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \ _page_cachable_default) #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ _PAGE_GLOBAL | _page_cachable_default) -#define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ +#define PAGE_USERIO __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \ _page_cachable_default) #define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \ __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED) /* - * MIPS can't do page protection for execute, and considers that the same like - * read. Also, write permissions imply read permissions. This is the closest - * we can get by reasonable means.. + * If _PAGE_NO_EXEC is not defined, we can't do page protection for + * execute, and consider it to be the same as read. Also, write + * permissions imply read permissions. This is the closest we can get + * by reasonable means.. */ /* @@ -298,8 +299,13 @@ static inline pte_t pte_mkdirty(pte_t pte) static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; - if (pte_val(pte) & _PAGE_READ) - pte_val(pte) |= _PAGE_SILENT_READ; + if (kernel_uses_smartmips_rixi) { + if (!(pte_val(pte) & _PAGE_NO_READ)) + pte_val(pte) |= _PAGE_SILENT_READ; + } else { + if (pte_val(pte) & _PAGE_READ) + pte_val(pte) |= _PAGE_SILENT_READ; + } return pte; } -- cgit v1.2.2 From 6f329468f3086e9d8f3832930fdb09ab3769176b Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 10 Feb 2010 15:12:48 -0800 Subject: MIPS: Give Octeon+ CPUs their own cputype. This allows us to treat them differently at runtime. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/951/ Patchwork: http://patchwork.linux-mips.org/patch/987/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index cf373a95fe4a..a5acda416946 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -224,7 +224,7 @@ enum cpu_type_enum { * MIPS64 class processors */ CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, - CPU_CAVIUM_OCTEON, + CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_LAST }; -- cgit v1.2.2 From 27a5bd6457c8ce38151250530152e15f76b697a8 Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 10 Feb 2010 15:12:49 -0800 Subject: MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUs Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/955/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h index 425e708d4fb9..bbf054042395 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h @@ -58,6 +58,9 @@ #define cpu_has_vint 0 #define cpu_has_veic 0 #define cpu_hwrena_impl_bits 0xc0000000 + +#define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS) + #define ARCH_HAS_READ_CURRENT_TIMER 1 #define ARCH_HAS_IRQ_PER_CPU 1 #define ARCH_HAS_SPINLOCK_PREFETCH 1 -- cgit v1.2.2 From 1a6e8963e07f126a7fa3e9b446f86205cd4e81fe Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Fri, 12 Feb 2010 21:27:59 +0900 Subject: MIPS: Use generic current.h Signed-off-by: Yoichi Yuasa Cc: linux-mips Patchwork: http://patchwork.linux-mips.org/patch/957/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/current.h | 24 +----------------------- 1 file changed, 1 insertion(+), 23 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/current.h b/arch/mips/include/asm/current.h index 559db66b9790..4c51401b5537 100644 --- a/arch/mips/include/asm/current.h +++ b/arch/mips/include/asm/current.h @@ -1,23 +1 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998, 2002 Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_CURRENT_H -#define _ASM_CURRENT_H - -#include - -struct task_struct; - -static inline struct task_struct * get_current(void) -{ - return current_thread_info()->task; -} - -#define current get_current() - -#endif /* _ASM_CURRENT_H */ +#include -- cgit v1.2.2 From f51e5a07728d33b7ad59a84d1a7a0a34d4f58765 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Fri, 12 Feb 2010 21:29:14 +0900 Subject: MIPS: Use generic parport.h Signed-off-by: Yoichi Yuasa Cc: linux-mips Patchwork: http://patchwork.linux-mips.org/patch/958/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/parport.h | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/parport.h b/arch/mips/include/asm/parport.h index f52656826cce..cf252af64590 100644 --- a/arch/mips/include/asm/parport.h +++ b/arch/mips/include/asm/parport.h @@ -1,15 +1 @@ -/* - * Copyright (C) 1999, 2000 Tim Waugh - * - * This file should only be included by drivers/parport/parport_pc.c. - */ -#ifndef _ASM_PARPORT_H -#define _ASM_PARPORT_H - -static int __devinit parport_pc_find_isa_ports(int autoirq, int autodma); -static int __devinit parport_pc_find_nonpci_ports(int autoirq, int autodma) -{ - return parport_pc_find_isa_ports(autoirq, autodma); -} - -#endif /* _ASM_PARPORT_H */ +#include -- cgit v1.2.2 From 7b012cee6173cef8598a4cf27fe80b4430e1ed7f Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Fri, 12 Feb 2010 21:33:56 +0900 Subject: MIPS: Use generic serial.h Signed-off-by: Yoichi Yuasa Cc: linux-mips Patchwork: http://patchwork.linux-mips.org/patch/960/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/serial.h | 23 +---------------------- 1 file changed, 1 insertion(+), 22 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/serial.h b/arch/mips/include/asm/serial.h index c07ebd8eb9e7..a0cb0caff152 100644 --- a/arch/mips/include/asm/serial.h +++ b/arch/mips/include/asm/serial.h @@ -1,22 +1 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1999 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_SERIAL_H -#define _ASM_SERIAL_H - - -/* - * This assumes you have a 1.8432 MHz clock for your UART. - * - * It'd be nice if someone built a serial card with a 24.576 MHz - * clock, since the 16550A is capable of handling a top speed of 1.5 - * megabits/second; but this requires the faster clock. - */ -#define BASE_BAUD (1843200 / 16) - -#endif /* _ASM_SERIAL_H */ +#include -- cgit v1.2.2 From d007f991a82ed159979b7662a4ca20e978221cdb Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Fri, 12 Feb 2010 21:35:04 +0900 Subject: MIPS: Use generic ucontext.h Signed-off-by: Yoichi Yuasa Cc: linux-mips Patchwork: http://patchwork.linux-mips.org/patch/959/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/ucontext.h | 22 +--------------------- 1 file changed, 1 insertion(+), 21 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/ucontext.h b/arch/mips/include/asm/ucontext.h index 8a4b20e88b81..9bc07b9f30fb 100644 --- a/arch/mips/include/asm/ucontext.h +++ b/arch/mips/include/asm/ucontext.h @@ -1,21 +1 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Low level exception handling - * - * Copyright (C) 1998, 1999 by Ralf Baechle - */ -#ifndef _ASM_UCONTEXT_H -#define _ASM_UCONTEXT_H - -struct ucontext { - unsigned long uc_flags; - struct ucontext *uc_link; - stack_t uc_stack; - struct sigcontext uc_mcontext; - sigset_t uc_sigmask; /* mask last for extensibility */ -}; - -#endif /* _ASM_UCONTEXT_H */ +#include -- cgit v1.2.2 From 4a8a738de637dc7141de5228d2d722573a329b95 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sat, 27 Feb 2010 12:53:30 +0100 Subject: MIPS: Make various locks static. Signed-off-by: Ralf Baechle --- arch/mips/include/asm/dec/kn01.h | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/dec/kn01.h b/arch/mips/include/asm/dec/kn01.h index 28fa717ac423..88d9ffd74258 100644 --- a/arch/mips/include/asm/dec/kn01.h +++ b/arch/mips/include/asm/dec/kn01.h @@ -80,7 +80,6 @@ struct pt_regs; extern u16 cached_kn01_csr; -extern spinlock_t kn01_lock; extern void dec_kn01_be_init(void); extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup); -- cgit v1.2.2 From 896508705561bea24656680cdaf3b4095c4d7473 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sat, 27 Feb 2010 12:53:38 +0100 Subject: MIPS: i8259: Convert IRQ controller lock to raw spinlock. Signed-off-by: Ralf Baechle --- arch/mips/include/asm/i8259.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/i8259.h b/arch/mips/include/asm/i8259.h index 8572a2d90484..c7e278447c0a 100644 --- a/arch/mips/include/asm/i8259.h +++ b/arch/mips/include/asm/i8259.h @@ -35,7 +35,7 @@ #define SLAVE_ICW4_DEFAULT 0x01 #define PIC_ICW4_AEOI 2 -extern spinlock_t i8259A_lock; +extern raw_spinlock_t i8259A_lock; extern int i8259A_irq_pending(unsigned int irq); extern void make_8259A_irq(unsigned int irq); @@ -51,7 +51,7 @@ static inline int i8259_irq(void) { int irq; - spin_lock(&i8259A_lock); + raw_spin_lock(&i8259A_lock); /* Perform an interrupt acknowledge cycle on controller 1. */ outb(0x0C, PIC_MASTER_CMD); /* prepare for poll */ @@ -78,7 +78,7 @@ static inline int i8259_irq(void) irq = -1; } - spin_unlock(&i8259A_lock); + raw_spin_unlock(&i8259A_lock); return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq; } -- cgit v1.2.2 From 500c2e1fdbcc2b273bd4c695a9b8ac8196f61614 Mon Sep 17 00:00:00 2001 From: David Daney Date: Thu, 4 Feb 2010 11:31:49 -0800 Subject: MIPS: Optimize spinlocks. The current locking mechanism uses a ll/sc sequence to release a spinlock. This is slower than a wmb() followed by a store to unlock. The branching forward to .subsection 2 on sc failure slows down the contended case. So we get rid of that part too. Since we are now working on naturally aligned u16 values, we can get rid of a masking operation as the LHU already does the right thing. The ANDI are reversed for better scheduling on multi-issue CPUs On a 12 CPU 750MHz Octeon cn5750 this patch improves ipv4 UDP packet forwarding rates from 3.58*10^6 PPS to 3.99*10^6 PPS, or about 11%. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/937/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/barrier.h | 6 ++ arch/mips/include/asm/spinlock.h | 118 ++++++++++++--------------------- arch/mips/include/asm/spinlock_types.h | 24 +++++-- 3 files changed, 67 insertions(+), 81 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h index a2670a239e0c..c0884f02d3a6 100644 --- a/arch/mips/include/asm/barrier.h +++ b/arch/mips/include/asm/barrier.h @@ -168,8 +168,14 @@ #ifdef CONFIG_CPU_CAVIUM_OCTEON #define smp_mb__before_llsc() smp_wmb() +/* Cause previous writes to become visible on all CPUs as soon as possible */ +#define nudge_writes() __asm__ __volatile__(".set push\n\t" \ + ".set arch=octeon\n\t" \ + "syncw\n\t" \ + ".set pop" : : : "memory") #else #define smp_mb__before_llsc() smp_llsc_mb() +#define nudge_writes() mb() #endif #endif /* __ASM_BARRIER_H */ diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h index 5f16696eaa00..396e402fbe2c 100644 --- a/arch/mips/include/asm/spinlock.h +++ b/arch/mips/include/asm/spinlock.h @@ -36,9 +36,9 @@ static inline int arch_spin_is_locked(arch_spinlock_t *lock) { - unsigned int counters = ACCESS_ONCE(lock->lock); + u32 counters = ACCESS_ONCE(lock->lock); - return ((counters >> 14) ^ counters) & 0x1fff; + return ((counters >> 16) ^ counters) & 0xffff; } #define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock) @@ -47,9 +47,9 @@ static inline int arch_spin_is_locked(arch_spinlock_t *lock) static inline int arch_spin_is_contended(arch_spinlock_t *lock) { - unsigned int counters = ACCESS_ONCE(lock->lock); + u32 counters = ACCESS_ONCE(lock->lock); - return (((counters >> 14) - counters) & 0x1fff) > 1; + return (((counters >> 16) - counters) & 0xffff) > 1; } #define arch_spin_is_contended arch_spin_is_contended @@ -57,6 +57,7 @@ static inline void arch_spin_lock(arch_spinlock_t *lock) { int my_ticket; int tmp; + int inc = 0x10000; if (R10000_LLSC_WAR) { __asm__ __volatile__ ( @@ -64,25 +65,24 @@ static inline void arch_spin_lock(arch_spinlock_t *lock) " .set noreorder \n" " \n" "1: ll %[ticket], %[ticket_ptr] \n" - " addiu %[my_ticket], %[ticket], 0x4000 \n" + " addu %[my_ticket], %[ticket], %[inc] \n" " sc %[my_ticket], %[ticket_ptr] \n" " beqzl %[my_ticket], 1b \n" " nop \n" - " srl %[my_ticket], %[ticket], 14 \n" - " andi %[my_ticket], %[my_ticket], 0x1fff \n" - " andi %[ticket], %[ticket], 0x1fff \n" + " srl %[my_ticket], %[ticket], 16 \n" + " andi %[ticket], %[ticket], 0xffff \n" + " andi %[my_ticket], %[my_ticket], 0xffff \n" " bne %[ticket], %[my_ticket], 4f \n" " subu %[ticket], %[my_ticket], %[ticket] \n" "2: \n" " .subsection 2 \n" - "4: andi %[ticket], %[ticket], 0x1fff \n" + "4: andi %[ticket], %[ticket], 0xffff \n" " sll %[ticket], 5 \n" " \n" "6: bnez %[ticket], 6b \n" " subu %[ticket], 1 \n" " \n" - " lw %[ticket], %[ticket_ptr] \n" - " andi %[ticket], %[ticket], 0x1fff \n" + " lhu %[ticket], %[serving_now_ptr] \n" " beq %[ticket], %[my_ticket], 2b \n" " subu %[ticket], %[my_ticket], %[ticket] \n" " b 4b \n" @@ -90,36 +90,33 @@ static inline void arch_spin_lock(arch_spinlock_t *lock) " .previous \n" " .set pop \n" : [ticket_ptr] "+m" (lock->lock), + [serving_now_ptr] "+m" (lock->h.serving_now), [ticket] "=&r" (tmp), - [my_ticket] "=&r" (my_ticket)); + [my_ticket] "=&r" (my_ticket) + : [inc] "r" (inc)); } else { __asm__ __volatile__ ( " .set push # arch_spin_lock \n" " .set noreorder \n" " \n" - " ll %[ticket], %[ticket_ptr] \n" - "1: addiu %[my_ticket], %[ticket], 0x4000 \n" + "1: ll %[ticket], %[ticket_ptr] \n" + " addu %[my_ticket], %[ticket], %[inc] \n" " sc %[my_ticket], %[ticket_ptr] \n" - " beqz %[my_ticket], 3f \n" - " nop \n" - " srl %[my_ticket], %[ticket], 14 \n" - " andi %[my_ticket], %[my_ticket], 0x1fff \n" - " andi %[ticket], %[ticket], 0x1fff \n" + " beqz %[my_ticket], 1b \n" + " srl %[my_ticket], %[ticket], 16 \n" + " andi %[ticket], %[ticket], 0xffff \n" + " andi %[my_ticket], %[my_ticket], 0xffff \n" " bne %[ticket], %[my_ticket], 4f \n" " subu %[ticket], %[my_ticket], %[ticket] \n" "2: \n" " .subsection 2 \n" - "3: b 1b \n" - " ll %[ticket], %[ticket_ptr] \n" - " \n" "4: andi %[ticket], %[ticket], 0x1fff \n" " sll %[ticket], 5 \n" " \n" "6: bnez %[ticket], 6b \n" " subu %[ticket], 1 \n" " \n" - " lw %[ticket], %[ticket_ptr] \n" - " andi %[ticket], %[ticket], 0x1fff \n" + " lhu %[ticket], %[serving_now_ptr] \n" " beq %[ticket], %[my_ticket], 2b \n" " subu %[ticket], %[my_ticket], %[ticket] \n" " b 4b \n" @@ -127,8 +124,10 @@ static inline void arch_spin_lock(arch_spinlock_t *lock) " .previous \n" " .set pop \n" : [ticket_ptr] "+m" (lock->lock), + [serving_now_ptr] "+m" (lock->h.serving_now), [ticket] "=&r" (tmp), - [my_ticket] "=&r" (my_ticket)); + [my_ticket] "=&r" (my_ticket) + : [inc] "r" (inc)); } smp_llsc_mb(); @@ -136,47 +135,16 @@ static inline void arch_spin_lock(arch_spinlock_t *lock) static inline void arch_spin_unlock(arch_spinlock_t *lock) { - int tmp; - - smp_mb__before_llsc(); - - if (R10000_LLSC_WAR) { - __asm__ __volatile__ ( - " # arch_spin_unlock \n" - "1: ll %[ticket], %[ticket_ptr] \n" - " addiu %[ticket], %[ticket], 1 \n" - " ori %[ticket], %[ticket], 0x2000 \n" - " xori %[ticket], %[ticket], 0x2000 \n" - " sc %[ticket], %[ticket_ptr] \n" - " beqzl %[ticket], 1b \n" - : [ticket_ptr] "+m" (lock->lock), - [ticket] "=&r" (tmp)); - } else { - __asm__ __volatile__ ( - " .set push # arch_spin_unlock \n" - " .set noreorder \n" - " \n" - " ll %[ticket], %[ticket_ptr] \n" - "1: addiu %[ticket], %[ticket], 1 \n" - " ori %[ticket], %[ticket], 0x2000 \n" - " xori %[ticket], %[ticket], 0x2000 \n" - " sc %[ticket], %[ticket_ptr] \n" - " beqz %[ticket], 2f \n" - " nop \n" - " \n" - " .subsection 2 \n" - "2: b 1b \n" - " ll %[ticket], %[ticket_ptr] \n" - " .previous \n" - " .set pop \n" - : [ticket_ptr] "+m" (lock->lock), - [ticket] "=&r" (tmp)); - } + unsigned int serving_now = lock->h.serving_now + 1; + wmb(); + lock->h.serving_now = (u16)serving_now; + nudge_writes(); } static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock) { int tmp, tmp2, tmp3; + int inc = 0x10000; if (R10000_LLSC_WAR) { __asm__ __volatile__ ( @@ -184,11 +152,11 @@ static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock) " .set noreorder \n" " \n" "1: ll %[ticket], %[ticket_ptr] \n" - " srl %[my_ticket], %[ticket], 14 \n" - " andi %[my_ticket], %[my_ticket], 0x1fff \n" - " andi %[now_serving], %[ticket], 0x1fff \n" + " srl %[my_ticket], %[ticket], 16 \n" + " andi %[my_ticket], %[my_ticket], 0xffff \n" + " andi %[now_serving], %[ticket], 0xffff \n" " bne %[my_ticket], %[now_serving], 3f \n" - " addiu %[ticket], %[ticket], 0x4000 \n" + " addu %[ticket], %[ticket], %[inc] \n" " sc %[ticket], %[ticket_ptr] \n" " beqzl %[ticket], 1b \n" " li %[ticket], 1 \n" @@ -201,33 +169,33 @@ static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock) : [ticket_ptr] "+m" (lock->lock), [ticket] "=&r" (tmp), [my_ticket] "=&r" (tmp2), - [now_serving] "=&r" (tmp3)); + [now_serving] "=&r" (tmp3) + : [inc] "r" (inc)); } else { __asm__ __volatile__ ( " .set push # arch_spin_trylock \n" " .set noreorder \n" " \n" - " ll %[ticket], %[ticket_ptr] \n" - "1: srl %[my_ticket], %[ticket], 14 \n" - " andi %[my_ticket], %[my_ticket], 0x1fff \n" - " andi %[now_serving], %[ticket], 0x1fff \n" + "1: ll %[ticket], %[ticket_ptr] \n" + " srl %[my_ticket], %[ticket], 16 \n" + " andi %[my_ticket], %[my_ticket], 0xffff \n" + " andi %[now_serving], %[ticket], 0xffff \n" " bne %[my_ticket], %[now_serving], 3f \n" - " addiu %[ticket], %[ticket], 0x4000 \n" + " addu %[ticket], %[ticket], %[inc] \n" " sc %[ticket], %[ticket_ptr] \n" - " beqz %[ticket], 4f \n" + " beqz %[ticket], 1b \n" " li %[ticket], 1 \n" "2: \n" " .subsection 2 \n" "3: b 2b \n" " li %[ticket], 0 \n" - "4: b 1b \n" - " ll %[ticket], %[ticket_ptr] \n" " .previous \n" " .set pop \n" : [ticket_ptr] "+m" (lock->lock), [ticket] "=&r" (tmp), [my_ticket] "=&r" (tmp2), - [now_serving] "=&r" (tmp3)); + [now_serving] "=&r" (tmp3) + : [inc] "r" (inc)); } smp_llsc_mb(); diff --git a/arch/mips/include/asm/spinlock_types.h b/arch/mips/include/asm/spinlock_types.h index ee197c2f9c98..c52f36013a9d 100644 --- a/arch/mips/include/asm/spinlock_types.h +++ b/arch/mips/include/asm/spinlock_types.h @@ -5,16 +5,28 @@ # error "please don't include this file directly" #endif -typedef struct { +#include + +#include + +typedef union { /* - * bits 0..13: serving_now - * bits 14 : junk data - * bits 15..28: ticket + * bits 0..15 : serving_now + * bits 16..31 : ticket */ - unsigned int lock; + u32 lock; + struct { +#ifdef __BIG_ENDIAN + u16 ticket; + u16 serving_now; +#else + u16 serving_now; + u16 ticket; +#endif + } h; } arch_spinlock_t; -#define __ARCH_SPIN_LOCK_UNLOCKED { 0 } +#define __ARCH_SPIN_LOCK_UNLOCKED { .lock = 0 } typedef struct { volatile unsigned int lock; -- cgit v1.2.2 From 11b897cf84c37e6522db914793677e933ef311fb Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Wed, 24 Feb 2010 17:40:21 +0100 Subject: MIPS: Alchemy: use 36bit addresses for PCMCIA resources. On Alchemy the PCMCIA area lies at the end of the chips 36bit system bus area. Currently, addresses at the far end of the 32bit area are assumed to belong to the PCMCIA area and fixed up to the real 36bit address before being passed to ioremap(). A previous commit enabled 64 bit physical size for the resource datatype on Alchemy and this allows to use the correct 36bit addresses when registering the PCMCIA sockets. This patch removes the 32-to-36bit address fixup and registers the Alchemy demo board pcmcia socket with the correct 36bit physical addresses. Tested on DB1200, with a CF card (ide-cs driver) and a 3c589 PCMCIA ethernet card. Signed-off-by: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Patchwork: http://patchwork.linux-mips.org/patch/994/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-au1x00/au1000.h | 14 -------------- arch/mips/include/asm/mach-au1x00/ioremap.h | 2 +- 2 files changed, 1 insertion(+), 15 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 2805fc56484d..ae07423e6e82 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -1678,18 +1678,4 @@ enum soc_au1200_ints { #endif -/* - * All Au1xx0 SOCs have a PCMCIA controller. - * We setup our 32-bit pseudo addresses to be equal to the - * 36-bit addr >> 4, to make it easier to check the address - * and fix it. - * The PCMCIA socket 0 physical attribute address is 0xF 4000 0000. - * The pseudo address we use is 0xF400 0000. Any address over - * 0xF400 0000 is a PCMCIA pseudo address. - */ -#define PCMCIA_IO_PSEUDO_PHYS (PCMCIA_IO_PHYS_ADDR >> 4) -#define PCMCIA_ATTR_PSEUDO_PHYS (PCMCIA_ATTR_PHYS_ADDR >> 4) -#define PCMCIA_MEM_PSEUDO_PHYS (PCMCIA_MEM_PHYS_ADDR >> 4) -#define PCMCIA_PSEUDO_END (0xffffffff) - #endif diff --git a/arch/mips/include/asm/mach-au1x00/ioremap.h b/arch/mips/include/asm/mach-au1x00/ioremap.h index 364cea2dc71f..75a94ad3ac91 100644 --- a/arch/mips/include/asm/mach-au1x00/ioremap.h +++ b/arch/mips/include/asm/mach-au1x00/ioremap.h @@ -11,7 +11,7 @@ #include -#ifdef CONFIG_64BIT_PHYS_ADDR +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_PCI) extern phys_t __fixup_bigphys_addr(phys_t, phys_t); #else static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) -- cgit v1.2.2 From d891a5399242579857701c2b1185b64d7bf7936f Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Sat, 20 Feb 2010 21:20:34 +0900 Subject: MIPS: ARC: Cleanup unused definitions from sgialib.h Signed-off-by: Yoichi Yuasa Cc: linux-mips Patchwork: http://patchwork.linux-mips.org/patch/979/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/sgialib.h | 45 ----------------------------------------- 1 file changed, 45 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/sgialib.h b/arch/mips/include/asm/sgialib.h index 63741ca1e422..2a2f1bddc276 100644 --- a/arch/mips/include/asm/sgialib.h +++ b/arch/mips/include/asm/sgialib.h @@ -33,14 +33,6 @@ extern int prom_flags; extern void prom_putchar(char c); extern char prom_getchar(void); -/* Memory descriptor management. */ -#define PROM_MAX_PMEMBLOCKS 32 -struct prom_pmemblock { - LONG base; /* Within KSEG0 or XKPHYS. */ - ULONG size; /* In bytes. */ - ULONG type; /* free or prom memory */ -}; - /* Get next memory descriptor after CURR, returns first descriptor * in chain is CURR is NULL. */ @@ -51,7 +43,6 @@ extern struct linux_mdesc *prom_getmdesc(struct linux_mdesc *curr); * array. */ extern void prom_meminit(void); -extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem); /* PROM device tree library routines. */ #define PROM_NULL_COMPONENT ((pcomponent *) 0) @@ -62,20 +53,6 @@ extern pcomponent *ArcGetPeer(pcomponent *this); /* Get child component of THIS. */ extern pcomponent *ArcGetChild(pcomponent *this); -/* Get parent component of CHILD. */ -extern pcomponent *prom_getparent(pcomponent *child); - -/* Copy component opaque data of component THIS into BUFFER - * if component THIS has opaque data. Returns success or - * failure status. - */ -extern long prom_getcdata(void *buffer, pcomponent *this); - -/* Other misc. component routines. */ -extern pcomponent *prom_childadd(pcomponent *this, pcomponent *tmp, void *data); -extern long prom_delcomponent(pcomponent *this); -extern pcomponent *prom_componentbypath(char *path); - /* This is called at prom_init time to identify the * ARC architecture we are running on */ @@ -88,35 +65,13 @@ extern LONG ArcSetEnvironmentVariable(PCHAR name, PCHAR value); /* ARCS command line parsing. */ extern void prom_init_cmdline(void); -/* Acquiring info about the current time, etc. */ -extern struct linux_tinfo *prom_gettinfo(void); -extern unsigned long prom_getrtime(void); - /* File operations. */ -extern long prom_getvdirent(unsigned long fd, struct linux_vdirent *ent, unsigned long num, unsigned long *cnt); -extern long prom_open(char *name, enum linux_omode md, unsigned long *fd); -extern long prom_close(unsigned long fd); extern LONG ArcRead(ULONG fd, PVOID buf, ULONG num, PULONG cnt); -extern long prom_getrstatus(unsigned long fd); extern LONG ArcWrite(ULONG fd, PVOID buf, ULONG num, PULONG cnt); -extern long prom_seek(unsigned long fd, struct linux_bigint *off, enum linux_seekmode sm); -extern long prom_mount(char *name, enum linux_mountops op); -extern long prom_getfinfo(unsigned long fd, struct linux_finfo *buf); -extern long prom_setfinfo(unsigned long fd, unsigned long flags, unsigned long msk); - -/* Running stand-along programs. */ -extern long prom_load(char *name, unsigned long end, unsigned long *pc, unsigned long *eaddr); -extern long prom_invoke(unsigned long pc, unsigned long sp, long argc, char **argv, char **envp); -extern long prom_exec(char *name, long argc, char **argv, char **envp); /* Misc. routines. */ -extern VOID prom_halt(VOID) __attribute__((noreturn)); -extern VOID prom_powerdown(VOID) __attribute__((noreturn)); -extern VOID prom_restart(VOID) __attribute__((noreturn)); extern VOID ArcReboot(VOID) __attribute__((noreturn)); extern VOID ArcEnterInteractiveMode(VOID) __attribute__((noreturn)); -extern long prom_cfgsave(VOID); -extern struct linux_sysid *prom_getsysid(VOID); extern VOID ArcFlushAllCaches(VOID); extern DISPLAY_STATUS *ArcGetDisplayStatus(ULONG FileID); -- cgit v1.2.2