From 0c3263870f5f80cf7b6cb322bd8e708ce568d36b Mon Sep 17 00:00:00 2001 From: David Daney Date: Fri, 25 Mar 2011 12:38:51 -0700 Subject: MIPS: Octeon: Rewrite interrupt handling code. This includes conversion to new style irq_chip functions, and correctly enabling/disabling per-CPU interrupts. The hardware interrupt bit to irq number mapping is now done with a flexible map, instead of by bit twiddling the irq number. [ tglx: Adjusted to new irq_cpu_on/offline callbacks and __irq_set_affinity_lock ] Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Cc: ralf@linux-mips.org LKML-Reference: <1301081931-11240-5-git-send-email-ddaney@caviumnetworks.com> Signed-off-by: Thomas Gleixner --- arch/mips/include/asm/octeon/octeon.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/mips/include/asm/octeon') diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h index 6b34afd0d4e7..f72f768cd3a4 100644 --- a/arch/mips/include/asm/octeon/octeon.h +++ b/arch/mips/include/asm/octeon/octeon.h @@ -257,4 +257,6 @@ extern struct cvmx_bootinfo *octeon_bootinfo; extern uint64_t octeon_bootloader_entry_addr; +extern void (*octeon_irq_setup_secondary)(void); + #endif /* __ASM_OCTEON_OCTEON_H */ -- cgit v1.2.2