From 74181295fbc6e65047e85529aa74457d82355ffc Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 27 May 2010 22:46:46 +0000 Subject: Blackfin: allow cache funcs to be in L1 for IFLUSH Anomaly 05000491 Anomaly 05000491 says that IFLUSH cannot have certain types of memory stalls triggered before it has completed in order to function correctly. One such condition is that it be in L1 instruction. So add a config option to move it there, default it to on, and throw up a warning when it is turned off and this anomaly exists. Since the anomaly should be worked around, we can drop the older method of calling IFLUSH multiple times. Signed-off-by: Mike Frysinger Signed-off-by: Sonic Zhang --- arch/blackfin/mach-common/arch_checks.c | 4 ++++ arch/blackfin/mach-common/cache.S | 15 ++++----------- 2 files changed, 8 insertions(+), 11 deletions(-) (limited to 'arch/blackfin/mach-common') diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c index 77d1c320d7e6..bceb98126c21 100644 --- a/arch/blackfin/mach-common/arch_checks.c +++ b/arch/blackfin/mach-common/arch_checks.c @@ -60,3 +60,7 @@ (defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)) # error "Anomaly 05000220 does not allow you to use Write Back cache with L2 or External Memory" #endif + +#if ANOMALY_05000491 && !defined(CONFIG_CACHE_FLUSH_L1) +# error You need IFLUSH in L1 inst while Anomaly 05000491 applies +#endif diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S index ea540318a228..790c767ca95a 100644 --- a/arch/blackfin/mach-common/cache.S +++ b/arch/blackfin/mach-common/cache.S @@ -11,7 +11,11 @@ #include #include +#ifdef CONFIG_CACHE_FLUSH_L1 +.section .l1.text +#else .text +#endif /* 05000443 - IFLUSH cannot be last instruction in hardware loop */ #if ANOMALY_05000443 @@ -64,17 +68,6 @@ /* Invalidate all instruction cache lines assocoiated with this memory area */ ENTRY(_blackfin_icache_flush_range) -/* - * Walkaround to avoid loading wrong instruction after invalidating icache - * and following sequence is met. - * - * 1) One instruction address is cached in the instruction cache. - * 2) This instruction in SDRAM is changed. - * 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range(). - * 4) This instruction is executed again, but the old one is loaded. - */ - P0 = R0; - IFLUSH[P0]; do_flush IFLUSH ENDPROC(_blackfin_icache_flush_range) -- cgit v1.2.2