From 6ed839423073251b513664fdadb180634aed704b Mon Sep 17 00:00:00 2001 From: Graf Yang Date: Thu, 24 Apr 2008 04:43:14 +0800 Subject: [Blackfin] arch: Resolve the clash issue of UART defines between blackfin headers and include/linux/serial_reg. Signed-off-by: Graf Yang Cc: Robin Getz Signed-off-by: Bryan Wu --- arch/blackfin/mach-bf537/head.S | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/blackfin/mach-bf537') diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S index ac85fdfbfd01..9e9fac9c6345 100644 --- a/arch/blackfin/mach-bf537/head.S +++ b/arch/blackfin/mach-bf537/head.S @@ -182,26 +182,26 @@ ENTRY(__start) /* Initialise UART - when booting from u-boot, the UART is not disabled * so if we dont initalize here, our serial console gets hosed */ - p0.h = hi(UART_LCR); - p0.l = lo(UART_LCR); + p0.h = hi(BFIN_UART_LCR); + p0.l = lo(BFIN_UART_LCR); r0 = 0x0(Z); w[p0] = r0.L; /* To enable DLL writes */ ssync; - p0.h = hi(UART_DLL); - p0.l = lo(UART_DLL); + p0.h = hi(BFIN_UART_DLL); + p0.l = lo(BFIN_UART_DLL); r0 = 0x0(Z); w[p0] = r0.L; ssync; - p0.h = hi(UART_DLH); - p0.l = lo(UART_DLH); + p0.h = hi(BFIN_UART_DLH); + p0.l = lo(BFIN_UART_DLH); r0 = 0x00(Z); w[p0] = r0.L; ssync; - p0.h = hi(UART_GCTL); - p0.l = lo(UART_GCTL); + p0.h = hi(BFIN_UART_GCTL); + p0.l = lo(BFIN_UART_GCTL); r0 = 0x0(Z); w[p0] = r0.L; /* To enable UART clock */ ssync; -- cgit v1.2.2