From 412b400278ed0f71712387d0b9b31cbdd8a18efc Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Sat, 30 May 2009 13:56:12 +0100 Subject: RealView: Allow SMP when the Cortex-A9 tile is enabled for EB Signed-off-by: Catalin Marinas --- arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9d02cdb15b23..a8d88af7fe88 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -859,7 +859,7 @@ source "kernel/time/Kconfig" config SMP bool "Symmetric Multi-Processing (EXPERIMENTAL)" - depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP) + depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || MACH_REALVIEW_PB11MP) select USE_GENERIC_SMP_HELPERS help This enables support for systems with more than one CPU. If you have -- cgit v1.2.2 From 1b504bbe7a4a6c251cdc9dcba1fab72234827945 Mon Sep 17 00:00:00 2001 From: Colin Tuckley Date: Sat, 30 May 2009 13:56:12 +0100 Subject: RealView: Add support for the RealView/PBX platform This is a RealView platform supporting core tiles with ARM11MPCore, Cortex-A8 or Cortex-A9 (multicore) processors. It has support for MMC, CompactFlash, PCI-E. Signed-off-by: Colin Tuckley Signed-off-by: Catalin Marinas --- arch/arm/Kconfig | 4 +- arch/arm/include/asm/hardware/cache-l2x0.h | 2 + arch/arm/mach-realview/Kconfig | 7 + arch/arm/mach-realview/Makefile | 1 + arch/arm/mach-realview/include/mach/board-pbx.h | 203 +++++++++++++ arch/arm/mach-realview/include/mach/debug-macro.S | 3 +- arch/arm/mach-realview/include/mach/irqs.h | 1 + arch/arm/mach-realview/include/mach/uncompress.h | 3 + arch/arm/mach-realview/platsmp.c | 4 + arch/arm/mach-realview/realview_pbx.c | 335 ++++++++++++++++++++++ arch/arm/mm/Kconfig | 6 +- 11 files changed, 563 insertions(+), 6 deletions(-) create mode 100644 arch/arm/mach-realview/include/mach/board-pbx.h create mode 100644 arch/arm/mach-realview/realview_pbx.c (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a8d88af7fe88..cb7b38831436 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -859,7 +859,7 @@ source "kernel/time/Kconfig" config SMP bool "Symmetric Multi-Processing (EXPERIMENTAL)" - depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || MACH_REALVIEW_PB11MP) + depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX) select USE_GENERIC_SMP_HELPERS help This enables support for systems with more than one CPU. If you have @@ -916,7 +916,7 @@ config HOTPLUG_CPU config LOCAL_TIMERS bool "Use local timer interrupts" - depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || REALVIEW_EB_A9MP) + depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || REALVIEW_EB_A9MP || MACH_REALVIEW_PBX) default y help Enable support for local timers on SMP platforms, rather then the diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 64f2252a25cd..cdb9022716fd 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -24,6 +24,8 @@ #define L2X0_CACHE_TYPE 0x004 #define L2X0_CTRL 0x100 #define L2X0_AUX_CTRL 0x104 +#define L2X0_TAG_LATENCY_CTRL 0x108 +#define L2X0_DATA_LATENCY_CTRL 0x10C #define L2X0_EVENT_CNT_CTRL 0x200 #define L2X0_EVENT_CNT1_CFG 0x204 #define L2X0_EVENT_CNT0_CFG 0x208 diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index b6ec10627776..368b58ae3043 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig @@ -58,6 +58,13 @@ config MACH_REALVIEW_PBA8 PB-A8 is a platform with an on-board Cortex-A8 and has support for PCI-E and Compact Flash. +config MACH_REALVIEW_PBX + bool "Support RealView/PBX platform" + select ARM_GIC + select HAVE_PATA_PLATFORM + help + Include support for the ARM(R) RealView PBX platform. + config REALVIEW_HIGH_PHYS_OFFSET bool "High physical base address for the RealView platform" depends on !MACH_REALVIEW_PB1176 diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile index 7bea8ffc4b59..7df1931ff443 100644 --- a/arch/arm/mach-realview/Makefile +++ b/arch/arm/mach-realview/Makefile @@ -7,5 +7,6 @@ obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o obj-$(CONFIG_MACH_REALVIEW_PB11MP) += realview_pb11mp.o obj-$(CONFIG_MACH_REALVIEW_PB1176) += realview_pb1176.o obj-$(CONFIG_MACH_REALVIEW_PBA8) += realview_pba8.o +obj-$(CONFIG_MACH_REALVIEW_PBX) += realview_pbx.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/arm/mach-realview/include/mach/board-pbx.h b/arch/arm/mach-realview/include/mach/board-pbx.h new file mode 100644 index 000000000000..c26509388828 --- /dev/null +++ b/arch/arm/mach-realview/include/mach/board-pbx.h @@ -0,0 +1,203 @@ +/* + * arch/arm/mach-realview/include/mach/board-pbx.h + * + * Copyright (C) 2009 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_BOARD_PBX_H +#define __ASM_ARCH_BOARD_PBX_H + +#include + +/* + * Peripheral addresses + */ +#define REALVIEW_PBX_UART0_BASE 0x10009000 /* UART 0 */ +#define REALVIEW_PBX_UART1_BASE 0x1000A000 /* UART 1 */ +#define REALVIEW_PBX_UART2_BASE 0x1000B000 /* UART 2 */ +#define REALVIEW_PBX_UART3_BASE 0x1000C000 /* UART 3 */ +#define REALVIEW_PBX_SSP_BASE 0x1000D000 /* Synchronous Serial Port */ +#define REALVIEW_PBX_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */ +#define REALVIEW_PBX_WATCHDOG_BASE 0x10010000 /* watchdog interface */ +#define REALVIEW_PBX_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */ +#define REALVIEW_PBX_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */ +#define REALVIEW_PBX_GPIO0_BASE 0x10013000 /* GPIO port 0 */ +#define REALVIEW_PBX_RTC_BASE 0x10017000 /* Real Time Clock */ +#define REALVIEW_PBX_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */ +#define REALVIEW_PBX_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */ +#define REALVIEW_PBX_SCTL_BASE 0x1001A000 /* System Controller */ +#define REALVIEW_PBX_CLCD_BASE 0x10020000 /* CLCD */ +#define REALVIEW_PBX_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */ +#define REALVIEW_PBX_DMC_BASE 0x100E0000 /* DMC configuration */ +#define REALVIEW_PBX_SMC_BASE 0x100E1000 /* SMC configuration */ +#define REALVIEW_PBX_CAN_BASE 0x100E2000 /* CAN bus */ +#define REALVIEW_PBX_GIC_CPU_BASE 0x1E000000 /* Generic interrupt controller CPU interface */ +#define REALVIEW_PBX_FLASH0_BASE 0x40000000 +#define REALVIEW_PBX_FLASH0_SIZE SZ_64M +#define REALVIEW_PBX_FLASH1_BASE 0x44000000 +#define REALVIEW_PBX_FLASH1_SIZE SZ_64M +#define REALVIEW_PBX_ETH_BASE 0x4E000000 /* Ethernet */ +#define REALVIEW_PBX_USB_BASE 0x4F000000 /* USB */ +#define REALVIEW_PBX_GIC_DIST_BASE 0x1E001000 /* Generic interrupt controller distributor */ +#define REALVIEW_PBX_LT_BASE 0xC0000000 /* Logic Tile expansion */ +#define REALVIEW_PBX_SDRAM6_BASE 0x70000000 /* SDRAM bank 6 256MB */ +#define REALVIEW_PBX_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */ + +/* + * Tile-specific addresses + */ +#define REALVIEW_PBX_TILE_SCU_BASE 0x1F000000 /* SCU registers */ +#define REALVIEW_PBX_TILE_GIC_CPU_BASE 0x1F000100 /* Private Generic interrupt controller CPU interface */ +#define REALVIEW_PBX_TILE_TWD_BASE 0x1F000600 +#define REALVIEW_PBX_TILE_TWD_PERCPU_BASE 0x1F000700 +#define REALVIEW_PBX_TILE_TWD_SIZE 0x00000100 +#define REALVIEW_PBX_TILE_GIC_DIST_BASE 0x1F001000 /* Private Generic interrupt controller distributor */ +#define REALVIEW_PBX_TILE_L220_BASE 0x1F002000 /* L220 registers */ + +#define REALVIEW_PBX_SYS_PLD_CTRL1 0x74 + +/* + * PBX PCI regions + */ +#define REALVIEW_PBX_PCI_BASE 0x90040000 /* PCI-X Unit base */ +#define REALVIEW_PBX_PCI_IO_BASE 0x90050000 /* IO Region on AHB */ +#define REALVIEW_PBX_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */ + +#define REALVIEW_PBX_PCI_BASE_SIZE 0x10000 /* 16 Kb */ +#define REALVIEW_PBX_PCI_IO_SIZE 0x1000 /* 4 Kb */ +#define REALVIEW_PBX_PCI_MEM_SIZE 0x20000000 /* 512 MB */ + +/* + * Irqs + */ +#define IRQ_PBX_GIC_START 32 + +/* L220 +#define IRQ_PBX_L220_EVENT (IRQ_PBX_GIC_START + 29) +#define IRQ_PBX_L220_SLAVE (IRQ_PBX_GIC_START + 30) +#define IRQ_PBX_L220_DECODE (IRQ_PBX_GIC_START + 31) +*/ + +/* + * PB-X on-board gic irq sources + */ +#define IRQ_PBX_WATCHDOG (IRQ_PBX_GIC_START + 0) /* Watchdog timer */ +#define IRQ_PBX_SOFT (IRQ_PBX_GIC_START + 1) /* Software interrupt */ +#define IRQ_PBX_COMMRx (IRQ_PBX_GIC_START + 2) /* Debug Comm Rx interrupt */ +#define IRQ_PBX_COMMTx (IRQ_PBX_GIC_START + 3) /* Debug Comm Tx interrupt */ +#define IRQ_PBX_TIMER0_1 (IRQ_PBX_GIC_START + 4) /* Timer 0/1 (default timer) */ +#define IRQ_PBX_TIMER2_3 (IRQ_PBX_GIC_START + 5) /* Timer 2/3 */ +#define IRQ_PBX_GPIO0 (IRQ_PBX_GIC_START + 6) /* GPIO 0 */ +#define IRQ_PBX_GPIO1 (IRQ_PBX_GIC_START + 7) /* GPIO 1 */ +#define IRQ_PBX_GPIO2 (IRQ_PBX_GIC_START + 8) /* GPIO 2 */ + /* 9 reserved */ +#define IRQ_PBX_RTC (IRQ_PBX_GIC_START + 10) /* Real Time Clock */ +#define IRQ_PBX_SSP (IRQ_PBX_GIC_START + 11) /* Synchronous Serial Port */ +#define IRQ_PBX_UART0 (IRQ_PBX_GIC_START + 12) /* UART 0 on development chip */ +#define IRQ_PBX_UART1 (IRQ_PBX_GIC_START + 13) /* UART 1 on development chip */ +#define IRQ_PBX_UART2 (IRQ_PBX_GIC_START + 14) /* UART 2 on development chip */ +#define IRQ_PBX_UART3 (IRQ_PBX_GIC_START + 15) /* UART 3 on development chip */ +#define IRQ_PBX_SCI (IRQ_PBX_GIC_START + 16) /* Smart Card Interface */ +#define IRQ_PBX_MMCI0A (IRQ_PBX_GIC_START + 17) /* Multimedia Card 0A */ +#define IRQ_PBX_MMCI0B (IRQ_PBX_GIC_START + 18) /* Multimedia Card 0B */ +#define IRQ_PBX_AACI (IRQ_PBX_GIC_START + 19) /* Audio Codec */ +#define IRQ_PBX_KMI0 (IRQ_PBX_GIC_START + 20) /* Keyboard/Mouse port 0 */ +#define IRQ_PBX_KMI1 (IRQ_PBX_GIC_START + 21) /* Keyboard/Mouse port 1 */ +#define IRQ_PBX_CHARLCD (IRQ_PBX_GIC_START + 22) /* Character LCD */ +#define IRQ_PBX_CLCD (IRQ_PBX_GIC_START + 23) /* CLCD controller */ +#define IRQ_PBX_DMAC (IRQ_PBX_GIC_START + 24) /* DMA controller */ +#define IRQ_PBX_PWRFAIL (IRQ_PBX_GIC_START + 25) /* Power failure */ +#define IRQ_PBX_PISMO (IRQ_PBX_GIC_START + 26) /* PISMO interface */ +#define IRQ_PBX_DoC (IRQ_PBX_GIC_START + 27) /* Disk on Chip memory controller */ +#define IRQ_PBX_ETH (IRQ_PBX_GIC_START + 28) /* Ethernet controller */ +#define IRQ_PBX_USB (IRQ_PBX_GIC_START + 29) /* USB controller */ +#define IRQ_PBX_TSPEN (IRQ_PBX_GIC_START + 30) /* Touchscreen pen */ +#define IRQ_PBX_TSKPAD (IRQ_PBX_GIC_START + 31) /* Touchscreen keypad */ + +#define IRQ_PBX_PMU_SCU0 (IRQ_PBX_GIC_START + 32) /* SCU PMU Interrupts (11mp) */ +#define IRQ_PBX_PMU_SCU1 (IRQ_PBX_GIC_START + 33) +#define IRQ_PBX_PMU_SCU2 (IRQ_PBX_GIC_START + 34) +#define IRQ_PBX_PMU_SCU3 (IRQ_PBX_GIC_START + 35) +#define IRQ_PBX_PMU_SCU4 (IRQ_PBX_GIC_START + 36) +#define IRQ_PBX_PMU_SCU5 (IRQ_PBX_GIC_START + 37) +#define IRQ_PBX_PMU_SCU6 (IRQ_PBX_GIC_START + 38) +#define IRQ_PBX_PMU_SCU7 (IRQ_PBX_GIC_START + 39) + +#define IRQ_PBX_WATCHDOG1 (IRQ_PBX_GIC_START + 40) /* Watchdog1 timer */ +#define IRQ_PBX_TIMER4_5 (IRQ_PBX_GIC_START + 41) /* Timer 0/1 (default timer) */ +#define IRQ_PBX_TIMER6_7 (IRQ_PBX_GIC_START + 42) /* Timer 2/3 */ +/* ... */ +#define IRQ_PBX_PMU_CPU3 (IRQ_PBX_GIC_START + 44) /* CPU PMU Interrupts */ +#define IRQ_PBX_PMU_CPU2 (IRQ_PBX_GIC_START + 45) +#define IRQ_PBX_PMU_CPU1 (IRQ_PBX_GIC_START + 46) +#define IRQ_PBX_PMU_CPU0 (IRQ_PBX_GIC_START + 47) + +/* ... */ +#define IRQ_PBX_PCI0 (IRQ_PBX_GIC_START + 50) +#define IRQ_PBX_PCI1 (IRQ_PBX_GIC_START + 51) +#define IRQ_PBX_PCI2 (IRQ_PBX_GIC_START + 52) +#define IRQ_PBX_PCI3 (IRQ_PBX_GIC_START + 53) + +#define IRQ_PBX_SMC -1 +#define IRQ_PBX_SCTL -1 + +#define NR_GIC_PBX 1 + +/* + * Only define NR_IRQS if less than NR_IRQS_PBX + */ +#define NR_IRQS_PBX (IRQ_PBX_GIC_START + 96) + +#if defined(CONFIG_MACH_REALVIEW_PBX) + +#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PBX) +#undef NR_IRQS +#define NR_IRQS NR_IRQS_PBX +#endif + +#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PBX) +#undef MAX_GIC_NR +#define MAX_GIC_NR NR_GIC_PBX +#endif + +#endif /* CONFIG_MACH_REALVIEW_PBX */ + +/* + * Core tile identification (REALVIEW_SYS_PROCID) + */ +#define REALVIEW_PBX_PROC_MASK 0xFF000000 +#define REALVIEW_PBX_PROC_ARM7TDMI 0x00000000 +#define REALVIEW_PBX_PROC_ARM9 0x02000000 +#define REALVIEW_PBX_PROC_ARM11 0x04000000 +#define REALVIEW_PBX_PROC_ARM11MP 0x06000000 +#define REALVIEW_PBX_PROC_A9MP 0x0C000000 +#define REALVIEW_PBX_PROC_A8 0x0E000000 + +#define check_pbx_proc(proc_type) \ + ((readl(__io_address(REALVIEW_SYS_PROCID)) & REALVIEW_PBX_PROC_MASK) \ + == proc_type) + +#ifdef CONFIG_MACH_REALVIEW_PBX +#define core_tile_pbx11mp() check_pbx_proc(REALVIEW_PBX_PROC_ARM11MP) +#define core_tile_pbxa9mp() check_pbx_proc(REALVIEW_PBX_PROC_A9MP) +#define core_tile_pbxa8() check_pbx_proc(REALVIEW_PBX_PROC_A8) +#else +#define core_tile_pbx11mp() 0 +#define core_tile_pbxa9mp() 0 +#define core_tile_pbxa8() 0 +#endif + +#endif /* __ASM_ARCH_BOARD_PBX_H */ diff --git a/arch/arm/mach-realview/include/mach/debug-macro.S b/arch/arm/mach-realview/include/mach/debug-macro.S index 92dbcb9e1792..932d8af18062 100644 --- a/arch/arm/mach-realview/include/mach/debug-macro.S +++ b/arch/arm/mach-realview/include/mach/debug-macro.S @@ -12,7 +12,8 @@ #if defined(CONFIG_MACH_REALVIEW_EB) || \ defined(CONFIG_MACH_REALVIEW_PB11MP) || \ - defined(CONFIG_MACH_REALVIEW_PBA8) + defined(CONFIG_MACH_REALVIEW_PBA8) || \ + defined(CONFIG_MACH_REALVIEW_PBX) #ifndef DEBUG_LL_UART_OFFSET #define DEBUG_LL_UART_OFFSET 0x00009000 #elif DEBUG_LL_UART_OFFSET != 0x00009000 diff --git a/arch/arm/mach-realview/include/mach/irqs.h b/arch/arm/mach-realview/include/mach/irqs.h index fe5cb987aa21..e9e38264671e 100644 --- a/arch/arm/mach-realview/include/mach/irqs.h +++ b/arch/arm/mach-realview/include/mach/irqs.h @@ -26,6 +26,7 @@ #include #include #include +#include #define IRQ_LOCALTIMER 29 #define IRQ_LOCALWDOG 30 diff --git a/arch/arm/mach-realview/include/mach/uncompress.h b/arch/arm/mach-realview/include/mach/uncompress.h index 415d634d52ab..83050378ffd2 100644 --- a/arch/arm/mach-realview/include/mach/uncompress.h +++ b/arch/arm/mach-realview/include/mach/uncompress.h @@ -24,6 +24,7 @@ #include #include #include +#include #define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00)) #define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c)) @@ -43,6 +44,8 @@ static inline unsigned long get_uart_base(void) return REALVIEW_PB1176_UART0_BASE; else if (machine_is_realview_pba8()) return REALVIEW_PBA8_UART0_BASE; + else if (machine_is_realview_pbx()) + return REALVIEW_PBX_UART0_BASE; else return 0; } diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index 30a9c68591f6..e3bd9345c6a1 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c @@ -22,6 +22,7 @@ #include #include +#include #include #include "core.h" @@ -40,6 +41,9 @@ static void __iomem *scu_base_addr(void) return __io_address(REALVIEW_EB11MP_SCU_BASE); else if (machine_is_realview_pb11mp()) return __io_address(REALVIEW_TC11MP_SCU_BASE); + else if (machine_is_realview_pbx() && + (core_tile_pbx11mp() || core_tile_pbxa9mp())) + return __io_address(REALVIEW_PBX_TILE_SCU_BASE); else return (void __iomem *)0; } diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c new file mode 100644 index 000000000000..1fe294d0bf9d --- /dev/null +++ b/arch/arm/mach-realview/realview_pbx.c @@ -0,0 +1,335 @@ +/* + * arch/arm/mach-realview/realview_pbx.c + * + * Copyright (C) 2009 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "core.h" + +static struct map_desc realview_pbx_io_desc[] __initdata = { + { + .virtual = IO_ADDRESS(REALVIEW_SYS_BASE), + .pfn = __phys_to_pfn(REALVIEW_SYS_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_PBX_GIC_CPU_BASE), + .pfn = __phys_to_pfn(REALVIEW_PBX_GIC_CPU_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_PBX_GIC_DIST_BASE), + .pfn = __phys_to_pfn(REALVIEW_PBX_GIC_DIST_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE), + .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_PBX_TIMER0_1_BASE), + .pfn = __phys_to_pfn(REALVIEW_PBX_TIMER0_1_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_PBX_TIMER2_3_BASE), + .pfn = __phys_to_pfn(REALVIEW_PBX_TIMER2_3_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, +#ifdef CONFIG_PCI + { + .virtual = PCIX_UNIT_BASE, + .pfn = __phys_to_pfn(REALVIEW_PBX_PCI_BASE), + .length = REALVIEW_PBX_PCI_BASE_SIZE, + .type = MT_DEVICE, + }, +#endif +#ifdef CONFIG_DEBUG_LL + { + .virtual = IO_ADDRESS(REALVIEW_PBX_UART0_BASE), + .pfn = __phys_to_pfn(REALVIEW_PBX_UART0_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, +#endif +}; + +static struct map_desc realview_local_io_desc[] __initdata = { + { + .virtual = IO_ADDRESS(REALVIEW_PBX_TILE_GIC_CPU_BASE), + .pfn = __phys_to_pfn(REALVIEW_PBX_TILE_GIC_CPU_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_PBX_TILE_GIC_DIST_BASE), + .pfn = __phys_to_pfn(REALVIEW_PBX_TILE_GIC_DIST_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_PBX_TILE_L220_BASE), + .pfn = __phys_to_pfn(REALVIEW_PBX_TILE_L220_BASE), + .length = SZ_8K, + .type = MT_DEVICE, + } +}; + +static void __init realview_pbx_map_io(void) +{ + iotable_init(realview_pbx_io_desc, ARRAY_SIZE(realview_pbx_io_desc)); + if (core_tile_pbx11mp() || core_tile_pbxa9mp()) + iotable_init(realview_local_io_desc, ARRAY_SIZE(realview_local_io_desc)); +} + +/* + * RealView PBXCore AMBA devices + */ + +#define GPIO2_IRQ { IRQ_PBX_GPIO2, NO_IRQ } +#define GPIO2_DMA { 0, 0 } +#define GPIO3_IRQ { IRQ_PBX_GPIO3, NO_IRQ } +#define GPIO3_DMA { 0, 0 } +#define AACI_IRQ { IRQ_PBX_AACI, NO_IRQ } +#define AACI_DMA { 0x80, 0x81 } +#define MMCI0_IRQ { IRQ_PBX_MMCI0A, IRQ_PBX_MMCI0B } +#define MMCI0_DMA { 0x84, 0 } +#define KMI0_IRQ { IRQ_PBX_KMI0, NO_IRQ } +#define KMI0_DMA { 0, 0 } +#define KMI1_IRQ { IRQ_PBX_KMI1, NO_IRQ } +#define KMI1_DMA { 0, 0 } +#define PBX_SMC_IRQ { NO_IRQ, NO_IRQ } +#define PBX_SMC_DMA { 0, 0 } +#define MPMC_IRQ { NO_IRQ, NO_IRQ } +#define MPMC_DMA { 0, 0 } +#define PBX_CLCD_IRQ { IRQ_PBX_CLCD, NO_IRQ } +#define PBX_CLCD_DMA { 0, 0 } +#define DMAC_IRQ { IRQ_PBX_DMAC, NO_IRQ } +#define DMAC_DMA { 0, 0 } +#define SCTL_IRQ { NO_IRQ, NO_IRQ } +#define SCTL_DMA { 0, 0 } +#define PBX_WATCHDOG_IRQ { IRQ_PBX_WATCHDOG, NO_IRQ } +#define PBX_WATCHDOG_DMA { 0, 0 } +#define PBX_GPIO0_IRQ { IRQ_PBX_GPIO0, NO_IRQ } +#define PBX_GPIO0_DMA { 0, 0 } +#define GPIO1_IRQ { IRQ_PBX_GPIO1, NO_IRQ } +#define GPIO1_DMA { 0, 0 } +#define PBX_RTC_IRQ { IRQ_PBX_RTC, NO_IRQ } +#define PBX_RTC_DMA { 0, 0 } +#define SCI_IRQ { IRQ_PBX_SCI, NO_IRQ } +#define SCI_DMA { 7, 6 } +#define PBX_UART0_IRQ { IRQ_PBX_UART0, NO_IRQ } +#define PBX_UART0_DMA { 15, 14 } +#define PBX_UART1_IRQ { IRQ_PBX_UART1, NO_IRQ } +#define PBX_UART1_DMA { 13, 12 } +#define PBX_UART2_IRQ { IRQ_PBX_UART2, NO_IRQ } +#define PBX_UART2_DMA { 11, 10 } +#define PBX_UART3_IRQ { IRQ_PBX_UART3, NO_IRQ } +#define PBX_UART3_DMA { 0x86, 0x87 } +#define PBX_SSP_IRQ { IRQ_PBX_SSP, NO_IRQ } +#define PBX_SSP_DMA { 9, 8 } + +/* FPGA Primecells */ +AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); +AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data); +AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL); +AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL); +AMBA_DEVICE(uart3, "fpga:09", PBX_UART3, NULL); + +/* DevChip Primecells */ +AMBA_DEVICE(smc, "dev:00", PBX_SMC, NULL); +AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); +AMBA_DEVICE(wdog, "dev:e1", PBX_WATCHDOG, NULL); +AMBA_DEVICE(gpio0, "dev:e4", PBX_GPIO0, NULL); +AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL); +AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL); +AMBA_DEVICE(rtc, "dev:e8", PBX_RTC, NULL); +AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); +AMBA_DEVICE(uart0, "dev:f1", PBX_UART0, NULL); +AMBA_DEVICE(uart1, "dev:f2", PBX_UART1, NULL); +AMBA_DEVICE(uart2, "dev:f3", PBX_UART2, NULL); +AMBA_DEVICE(ssp0, "dev:f4", PBX_SSP, NULL); + +/* Primecells on the NEC ISSP chip */ +AMBA_DEVICE(clcd, "issp:20", PBX_CLCD, &clcd_plat_data); +AMBA_DEVICE(dmac, "issp:30", DMAC, NULL); + +static struct amba_device *amba_devs[] __initdata = { + &dmac_device, + &uart0_device, + &uart1_device, + &uart2_device, + &uart3_device, + &smc_device, + &clcd_device, + &sctl_device, + &wdog_device, + &gpio0_device, + &gpio1_device, + &gpio2_device, + &rtc_device, + &sci0_device, + &ssp0_device, + &aaci_device, + &mmc0_device, + &kmi0_device, + &kmi1_device, +}; + +/* + * RealView PB-X platform devices + */ +static struct resource realview_pbx_flash_resources[] = { + [0] = { + .start = REALVIEW_PBX_FLASH0_BASE, + .end = REALVIEW_PBX_FLASH0_BASE + REALVIEW_PBX_FLASH0_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = REALVIEW_PBX_FLASH1_BASE, + .end = REALVIEW_PBX_FLASH1_BASE + REALVIEW_PBX_FLASH1_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource realview_pbx_smsc911x_resources[] = { + [0] = { + .start = REALVIEW_PBX_ETH_BASE, + .end = REALVIEW_PBX_ETH_BASE + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_PBX_ETH, + .end = IRQ_PBX_ETH, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource realview_pbx_isp1761_resources[] = { + [0] = { + .start = REALVIEW_PBX_USB_BASE, + .end = REALVIEW_PBX_USB_BASE + SZ_128K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_PBX_USB, + .end = IRQ_PBX_USB, + .flags = IORESOURCE_IRQ, + }, +}; + +static void __init gic_init_irq(void) +{ + /* ARM PBX on-board GIC */ + if (core_tile_pbx11mp() || core_tile_pbxa9mp()) { + gic_cpu_base_addr = __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE); + gic_dist_init(0, __io_address(REALVIEW_PBX_TILE_GIC_DIST_BASE), + 29); + gic_cpu_init(0, __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE)); + } else { + gic_cpu_base_addr = __io_address(REALVIEW_PBX_GIC_CPU_BASE); + gic_dist_init(0, __io_address(REALVIEW_PBX_GIC_DIST_BASE), + IRQ_PBX_GIC_START); + gic_cpu_init(0, __io_address(REALVIEW_PBX_GIC_CPU_BASE)); + } +} + +static void __init realview_pbx_timer_init(void) +{ + timer0_va_base = __io_address(REALVIEW_PBX_TIMER0_1_BASE); + timer1_va_base = __io_address(REALVIEW_PBX_TIMER0_1_BASE) + 0x20; + timer2_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE); + timer3_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE) + 0x20; + +#ifdef CONFIG_LOCAL_TIMERS + if (core_tile_pbx11mp() || core_tile_pbxa9mp()) + twd_base = __io_address(REALVIEW_PBX_TILE_TWD_BASE); +#endif + realview_timer_init(IRQ_PBX_TIMER0_1); +} + +static struct sys_timer realview_pbx_timer = { + .init = realview_pbx_timer_init, +}; + +static void __init realview_pbx_init(void) +{ + int i; + +#ifdef CONFIG_CACHE_L2X0 + if (core_tile_pbxa9mp()) { + void __iomem *l2x0_base = + __io_address(REALVIEW_PBX_TILE_L220_BASE); + + /* set RAM latencies to 1 cycle for eASIC */ + writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL); + writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL); + + /* 16KB way size, 8-way associativity, parity disabled + * Bits: .. 0 0 0 0 1 00 1 0 1 001 0 000 0 .... .... .... */ + l2x0_init(l2x0_base, 0x02520000, 0xc0000fff); + } +#endif + + realview_flash_register(realview_pbx_flash_resources, + ARRAY_SIZE(realview_pbx_flash_resources)); + realview_eth_register(NULL, realview_pbx_smsc911x_resources); + platform_device_register(&realview_i2c_device); + platform_device_register(&realview_cf_device); + realview_usb_register(realview_pbx_isp1761_resources); + + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { + struct amba_device *d = amba_devs[i]; + amba_device_register(d, &iomem_resource); + } + +#ifdef CONFIG_LEDS + leds_event = realview_leds_event; +#endif +} + +MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX") + /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ + .phys_io = REALVIEW_PBX_UART0_BASE, + .io_pg_offst = (IO_ADDRESS(REALVIEW_PBX_UART0_BASE) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x00000100, + .map_io = realview_pbx_map_io, + .init_irq = gic_init_irq, + .timer = &realview_pbx_timer, + .init_machine = realview_pbx_init, +MACHINE_END diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 20979564e7ee..76bbcde049b0 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -391,7 +391,7 @@ config CPU_FEROCEON_OLD_ID # ARMv6 config CPU_V6 - bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB + bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX select CPU_32v6 select CPU_ABRT_EV6 select CPU_PABRT_NOIFAR @@ -416,7 +416,7 @@ config CPU_32v6K # ARMv7 config CPU_V7 - bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB + bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX select CPU_32v6K select CPU_32v7 select CPU_ABRT_EV7 @@ -747,7 +747,7 @@ config CACHE_FEROCEON_L2_WRITETHROUGH config CACHE_L2X0 bool "Enable the L2x0 outer cache controller" depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ - REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 + REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX default y select OUTER_CACHE help -- cgit v1.2.2 From af607747def54d8f76d2509c1394587da5d9bdfd Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Sat, 30 May 2009 13:56:13 +0100 Subject: RealView: Allow access to the secure flash memory block on PB1176 This patch adds a Kconfig option for specifying whether Linux will only be run in secure mode on the RealView PB1176 platform. Enabling it will make the secure flash memory block (64MB @ 0x3c000000) available to Linux. Signed-off-by: Catalin Marinas --- arch/arm/mach-realview/Kconfig | 9 +++++++++ arch/arm/mach-realview/include/mach/board-pb1176.h | 2 ++ arch/arm/mach-realview/realview_pb1176.c | 23 +++++++++++++++++----- 3 files changed, 29 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index 368b58ae3043..e09f540f3217 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig @@ -48,6 +48,15 @@ config MACH_REALVIEW_PB1176 help Include support for the ARM(R) RealView ARM1176 Platform Baseboard. +config REALVIEW_PB1176_SECURE_FLASH + bool "Allow access to the secure flash memory block" + depends on MACH_REALVIEW_PB1176 + default n + help + Select this option if Linux will only run in secure mode on the + RealView PB1176 platform and access to the secure flash memory + block (64MB @ 0x3c000000) is required. + config MACH_REALVIEW_PBA8 bool "Support RealView/PB-A8 platform" select CPU_V7 diff --git a/arch/arm/mach-realview/include/mach/board-pb1176.h b/arch/arm/mach-realview/include/mach/board-pb1176.h index 858eea7b1adc..e4d0e8046ea5 100644 --- a/arch/arm/mach-realview/include/mach/board-pb1176.h +++ b/arch/arm/mach-realview/include/mach/board-pb1176.h @@ -32,6 +32,8 @@ #define REALVIEW_PB1176_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */ #define REALVIEW_PB1176_FLASH_BASE 0x30000000 #define REALVIEW_PB1176_FLASH_SIZE SZ_64M +#define REALVIEW_PB1176_SEC_FLASH_BASE 0x3C000000 /* Secure flash */ +#define REALVIEW_PB1176_SEC_FLASH_SIZE SZ_64M #define REALVIEW_PB1176_TIMER0_1_BASE 0x10104000 /* Timer 0 and 1 */ #define REALVIEW_PB1176_TIMER2_3_BASE 0x10105000 /* Timer 2 and 3 */ diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c index a64b84a7a3df..25efe71a67c7 100644 --- a/arch/arm/mach-realview/realview_pb1176.c +++ b/arch/arm/mach-realview/realview_pb1176.c @@ -203,11 +203,23 @@ static struct amba_device *amba_devs[] __initdata = { /* * RealView PB1176 platform devices */ -static struct resource realview_pb1176_flash_resource = { - .start = REALVIEW_PB1176_FLASH_BASE, - .end = REALVIEW_PB1176_FLASH_BASE + REALVIEW_PB1176_FLASH_SIZE - 1, - .flags = IORESOURCE_MEM, +static struct resource realview_pb1176_flash_resources[] = { + [0] = { + .start = REALVIEW_PB1176_FLASH_BASE, + .end = REALVIEW_PB1176_FLASH_BASE + REALVIEW_PB1176_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = REALVIEW_PB1176_SEC_FLASH_BASE, + .end = REALVIEW_PB1176_SEC_FLASH_BASE + REALVIEW_PB1176_SEC_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, + }, }; +#ifdef CONFIG_REALVIEW_PB1176_SECURE_FLASH +#define PB1176_FLASH_BLOCKS 2 +#else +#define PB1176_FLASH_BLOCKS 1 +#endif static struct resource realview_pb1176_smsc911x_resources[] = { [0] = { @@ -271,7 +283,8 @@ static void __init realview_pb1176_init(void) l2x0_init(__io_address(REALVIEW_PB1176_L220_BASE), 0x00730000, 0xfe000fff); #endif - realview_flash_register(&realview_pb1176_flash_resource, 1); + realview_flash_register(realview_pb1176_flash_resources, + PB1176_FLASH_BLOCKS); realview_eth_register(NULL, realview_pb1176_smsc911x_resources); platform_device_register(&realview_i2c_device); realview_usb_register(realview_pb1176_isp1761_resources); -- cgit v1.2.2 From ff3042fb6f1a0f6faf527390a8a943a3e4296741 Mon Sep 17 00:00:00 2001 From: Colin Tuckley Date: Sat, 30 May 2009 13:56:13 +0100 Subject: RealView: Allow CONFIG_LEDS on this platform Signed-off-by: Colin Tuckley Signed-off-by: Catalin Marinas --- arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index cb7b38831436..ceb549ca9635 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1027,7 +1027,7 @@ config LEDS ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ ARCH_AT91 || ARCH_DAVINCI || \ - ARCH_KS8695 || MACH_RD88F5182 + ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW help If you say Y here, the LEDs on your machine will be used to provide useful information about your current system status. -- cgit v1.2.2 From da055eb52ec067d51dc08c7e86baf92dd5c01599 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Sat, 30 May 2009 13:56:16 +0100 Subject: RealView: Toggle one LED per CPU If CONFIG_LEDS is enabled, it makes more sense to toggle one LED per CPU in SMP systems rather than a single LED for all the CPUs. Signed-off-by: Catalin Marinas --- arch/arm/mach-realview/core.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 076acbc50706..346cbf0cd13e 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -578,21 +578,22 @@ void realview_leds_event(led_event_t ledevt) { unsigned long flags; u32 val; + u32 led = 1 << smp_processor_id(); local_irq_save(flags); val = readl(VA_LEDS_BASE); switch (ledevt) { case led_idle_start: - val = val & ~REALVIEW_SYS_LED0; + val = val & ~led; break; case led_idle_end: - val = val | REALVIEW_SYS_LED0; + val = val | led; break; case led_timer: - val = val ^ REALVIEW_SYS_LED1; + val = val ^ REALVIEW_SYS_LED7; break; case led_halted: -- cgit v1.2.2 From faa7bc51c11d5bbe440ac04710fd7a3208782000 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Sat, 30 May 2009 14:00:14 +0100 Subject: Check whether the TLB operations need broadcasting on SMP systems ARMv7 SMP hardware can handle the TLB maintenance operations broadcasting in hardware so that the software can avoid the costly IPIs. This patch adds the necessary checks (the MMFR3 CPUID register) to avoid the broadcasting if already supported by the hardware. (this patch is based on the work done by Tony Thompson @ ARM) Signed-off-by: Catalin Marinas --- arch/arm/include/asm/cputype.h | 25 +++++++++++++++ arch/arm/include/asm/tlbflush.h | 26 ++++++++++++++-- arch/arm/kernel/smp.c | 69 +++++++++++++++++++++++++---------------- arch/arm/mm/proc-v7.S | 4 +-- arch/arm/mm/tlb-v7.S | 17 ++++++---- 5 files changed, 105 insertions(+), 36 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index 7b9d27e749b8..b3e656c6fb78 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -8,6 +8,21 @@ #define CPUID_TCM 2 #define CPUID_TLBTYPE 3 +#define CPUID_EXT_PFR0 "c1, 0" +#define CPUID_EXT_PFR1 "c1, 1" +#define CPUID_EXT_DFR0 "c1, 2" +#define CPUID_EXT_AFR0 "c1, 3" +#define CPUID_EXT_MMFR0 "c1, 4" +#define CPUID_EXT_MMFR1 "c1, 5" +#define CPUID_EXT_MMFR2 "c1, 6" +#define CPUID_EXT_MMFR3 "c1, 7" +#define CPUID_EXT_ISAR0 "c2, 0" +#define CPUID_EXT_ISAR1 "c2, 1" +#define CPUID_EXT_ISAR2 "c2, 2" +#define CPUID_EXT_ISAR3 "c2, 3" +#define CPUID_EXT_ISAR4 "c2, 4" +#define CPUID_EXT_ISAR5 "c2, 5" + #ifdef CONFIG_CPU_CP15 #define read_cpuid(reg) \ ({ \ @@ -18,9 +33,19 @@ : "cc"); \ __val; \ }) +#define read_cpuid_ext(ext_reg) \ + ({ \ + unsigned int __val; \ + asm("mrc p15, 0, %0, c0, " ext_reg \ + : "=r" (__val) \ + : \ + : "cc"); \ + __val; \ + }) #else extern unsigned int processor_id; #define read_cpuid(reg) (processor_id) +#define read_cpuid_ext(reg) 0 #endif /* diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index a62218013c78..c964f3fc3bc5 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h @@ -40,6 +40,12 @@ #define TLB_V6_I_ASID (1 << 18) #define TLB_BTB (1 << 28) + +/* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */ +#define TLB_V7_UIS_PAGE (1 << 19) +#define TLB_V7_UIS_FULL (1 << 20) +#define TLB_V7_UIS_ASID (1 << 21) + #define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */ #define TLB_DCLEAN (1 << 30) #define TLB_WB (1 << 31) @@ -176,9 +182,17 @@ # define v6wbi_always_flags (-1UL) #endif +#ifdef CONFIG_SMP +#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \ + TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID) +#else +#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \ + TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID) +#endif + #ifdef CONFIG_CPU_TLB_V7 -# define v7wbi_possible_flags v6wbi_tlb_flags -# define v7wbi_always_flags v6wbi_tlb_flags +# define v7wbi_possible_flags v7wbi_tlb_flags +# define v7wbi_always_flags v7wbi_tlb_flags # ifdef _TLB # define MULTI_TLB 1 # else @@ -316,6 +330,8 @@ static inline void local_flush_tlb_all(void) asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc"); if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL)) asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); + if (tlb_flag(TLB_V7_UIS_FULL)) + asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc"); if (tlb_flag(TLB_BTB)) { /* flush the branch target cache */ @@ -351,6 +367,8 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc"); if (tlb_flag(TLB_V6_I_ASID)) asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc"); + if (tlb_flag(TLB_V7_UIS_ASID)) + asm("mcr p15, 0, %0, c8, c3, 2" : : "r" (asid) : "cc"); if (tlb_flag(TLB_BTB)) { /* flush the branch target cache */ @@ -389,6 +407,8 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc"); if (tlb_flag(TLB_V6_I_PAGE)) asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc"); + if (tlb_flag(TLB_V7_UIS_PAGE)) + asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (uaddr) : "cc"); if (tlb_flag(TLB_BTB)) { /* flush the branch target cache */ @@ -424,6 +444,8 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc"); if (tlb_flag(TLB_V6_I_PAGE)) asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc"); + if (tlb_flag(TLB_V7_UIS_PAGE)) + asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (kaddr) : "cc"); if (tlb_flag(TLB_BTB)) { /* flush the branch target cache */ diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 6014dfd22af4..ece658e773a6 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -32,6 +32,7 @@ #include #include #include +#include /* * as from 2.5, kernels no longer have an init_tasks structure @@ -545,6 +546,12 @@ struct tlb_args { unsigned long ta_end; }; +/* all SMP configurations have the extended CPUID registers */ +static inline int tlb_ops_need_broadcast(void) +{ + return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2; +} + static inline void ipi_flush_tlb_all(void *ignored) { local_flush_tlb_all(); @@ -587,51 +594,61 @@ static inline void ipi_flush_tlb_kernel_range(void *arg) void flush_tlb_all(void) { - on_each_cpu(ipi_flush_tlb_all, NULL, 1); + if (tlb_ops_need_broadcast()) + on_each_cpu(ipi_flush_tlb_all, NULL, 1); + else + local_flush_tlb_all(); } void flush_tlb_mm(struct mm_struct *mm) { - on_each_cpu_mask(ipi_flush_tlb_mm, mm, 1, &mm->cpu_vm_mask); + if (tlb_ops_need_broadcast()) + on_each_cpu_mask(ipi_flush_tlb_mm, mm, 1, &mm->cpu_vm_mask); + else + local_flush_tlb_mm(mm); } void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) { - struct tlb_args ta; - - ta.ta_vma = vma; - ta.ta_start = uaddr; - - on_each_cpu_mask(ipi_flush_tlb_page, &ta, 1, &vma->vm_mm->cpu_vm_mask); + if (tlb_ops_need_broadcast()) { + struct tlb_args ta; + ta.ta_vma = vma; + ta.ta_start = uaddr; + on_each_cpu_mask(ipi_flush_tlb_page, &ta, 1, &vma->vm_mm->cpu_vm_mask); + } else + local_flush_tlb_page(vma, uaddr); } void flush_tlb_kernel_page(unsigned long kaddr) { - struct tlb_args ta; - - ta.ta_start = kaddr; - - on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1); + if (tlb_ops_need_broadcast()) { + struct tlb_args ta; + ta.ta_start = kaddr; + on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1); + } else + local_flush_tlb_kernel_page(kaddr); } void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - struct tlb_args ta; - - ta.ta_vma = vma; - ta.ta_start = start; - ta.ta_end = end; - - on_each_cpu_mask(ipi_flush_tlb_range, &ta, 1, &vma->vm_mm->cpu_vm_mask); + if (tlb_ops_need_broadcast()) { + struct tlb_args ta; + ta.ta_vma = vma; + ta.ta_start = start; + ta.ta_end = end; + on_each_cpu_mask(ipi_flush_tlb_range, &ta, 1, &vma->vm_mm->cpu_vm_mask); + } else + local_flush_tlb_range(vma, start, end); } void flush_tlb_kernel_range(unsigned long start, unsigned long end) { - struct tlb_args ta; - - ta.ta_start = start; - ta.ta_end = end; - - on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1); + if (tlb_ops_need_broadcast()) { + struct tlb_args ta; + ta.ta_start = start; + ta.ta_end = end; + on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1); + } else + local_flush_tlb_kernel_range(start, end); } diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 3397f1e64d76..c3f737516836 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -176,8 +176,8 @@ cpu_v7_name: */ __v7_setup: #ifdef CONFIG_SMP - mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode - orr r0, r0, #(0x1 << 6) + mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode and + orr r0, r0, #(1 << 6) | (1 << 0) @ TLB ops broadcasting mcr p15, 0, r0, c1, c0, 1 #endif adr r12, __v7_setup_stack @ the local stack diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S index b637e7380ab7..a26a605b73bd 100644 --- a/arch/arm/mm/tlb-v7.S +++ b/arch/arm/mm/tlb-v7.S @@ -42,9 +42,11 @@ ENTRY(v7wbi_flush_user_tlb_range) mov r1, r1, lsl #PAGE_SHIFT vma_vm_flags r2, r2 @ get vma->vm_flags 1: - mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1) - tst r2, #VM_EXEC @ Executable area ? - mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1) +#ifdef CONFIG_SMP + mcr p15, 0, r0, c8, c3, 1 @ TLB invalidate U MVA (shareable) +#else + mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate U MVA +#endif add r0, r0, #PAGE_SZ cmp r0, r1 blo 1b @@ -69,8 +71,11 @@ ENTRY(v7wbi_flush_kern_tlb_range) mov r0, r0, lsl #PAGE_SHIFT mov r1, r1, lsl #PAGE_SHIFT 1: - mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA - mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA +#ifdef CONFIG_SMP + mcr p15, 0, r0, c8, c3, 1 @ TLB invalidate U MVA (shareable) +#else + mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate U MVA +#endif add r0, r0, #PAGE_SZ cmp r0, r1 blo 1b @@ -87,5 +92,5 @@ ENDPROC(v7wbi_flush_kern_tlb_range) ENTRY(v7wbi_tlb_fns) .long v7wbi_flush_user_tlb_range .long v7wbi_flush_kern_tlb_range - .long v6wbi_tlb_flags + .long v7wbi_tlb_flags .size v7wbi_tlb_fns, . - v7wbi_tlb_fns -- cgit v1.2.2 From ba3c02636a0743a62cb50b920d36e1c046ab88cf Mon Sep 17 00:00:00 2001 From: Tony Thompson Date: Sat, 30 May 2009 14:00:15 +0100 Subject: ARMv7: Mark the PTWs inner WBWA on SMP and WB on UP There are additional bits to set for the ARMv7 SMP extensions in the TTBR registers. The IRGN bits order is counter-intuitive but it allows software built for the ARMv7 base architecture to run on an implementation with the MP extensions. Signed-off-by: Tony Thompson Signed-off-by: Catalin Marinas --- arch/arm/mm/proc-v7.S | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index c3f737516836..a18aace32990 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -19,17 +19,23 @@ #include "proc-macros.S" -#define TTB_C (1 << 0) #define TTB_S (1 << 1) #define TTB_RGN_NC (0 << 3) #define TTB_RGN_OC_WBWA (1 << 3) #define TTB_RGN_OC_WT (2 << 3) #define TTB_RGN_OC_WB (3 << 3) +#define TTB_NOS (1 << 5) +#define TTB_IRGN_NC ((0 << 0) | (0 << 6)) +#define TTB_IRGN_WBWA ((0 << 0) | (1 << 6)) +#define TTB_IRGN_WT ((1 << 0) | (0 << 6)) +#define TTB_IRGN_WB ((1 << 0) | (1 << 6)) #ifndef CONFIG_SMP -#define TTB_FLAGS TTB_C|TTB_RGN_OC_WB @ mark PTWs cacheable, outer WB +/* PTWs cacheable, inner WB not shareable, outer WB not shareable */ +#define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB #else -#define TTB_FLAGS TTB_C|TTB_S|TTB_RGN_OC_WBWA @ mark PTWs cacheable and shared, outer WBWA +/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ +#define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA #endif ENTRY(cpu_v7_proc_init) -- cgit v1.2.2 From d71e1352e240dea32d481ad8d662e8de4406ac7e Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Sat, 30 May 2009 14:00:15 +0100 Subject: Clear the IT state when invoking a Thumb-2 signal handler If a process is interrupted during an If-Then block and a signal is invoked, the ITSTATE bits must be cleared otherwise the handler would not run correctly. Signed-off-by: Catalin Marinas Cc: Joseph S. Myers --- arch/arm/include/asm/ptrace.h | 7 +++++++ arch/arm/kernel/signal.c | 8 ++++++-- 2 files changed, 13 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h index 236a06b9b7ce..4a4290f7b4a2 100644 --- a/arch/arm/include/asm/ptrace.h +++ b/arch/arm/include/asm/ptrace.h @@ -65,6 +65,13 @@ #define PSR_x 0x0000ff00 /* Extension */ #define PSR_c 0x000000ff /* Control */ +/* + * ARMv7 groups of APSR bits + */ +#define PSR_ISET_MASK 0x01000010 /* ISA state (J, T) mask */ +#define PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */ +#define PSR_ENDIAN_MASK 0x00000200 /* Endianness state mask */ + #ifndef __ASSEMBLY__ /* diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index 80b8b5c7e07a..442b87476f97 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -426,9 +426,13 @@ setup_return(struct pt_regs *regs, struct k_sigaction *ka, */ thumb = handler & 1; - if (thumb) + if (thumb) { cpsr |= PSR_T_BIT; - else +#if __LINUX_ARM_ARCH__ >= 7 + /* clear the If-Then Thumb-2 execution state */ + cpsr &= ~PSR_IT_MASK; +#endif + } else cpsr &= ~PSR_T_BIT; } #endif -- cgit v1.2.2 From 213fb2a8ee81ec106b9b370a07ccad575e9d3748 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Sat, 30 May 2009 14:00:16 +0100 Subject: ARMv7: Enable the SWP instruction The SWP instruction has been deprecated starting with the ARMv6 architecture. On ARMv7 processors with the multiprocessor extensions (like Cortex-A9), this instruction is disabled by default but it can be enabled by setting bit 10 in the System Control register. Note that setting this bit is safe even if the ARMv7 processor has the SWP instruction enabled by default. Signed-off-by: Catalin Marinas --- arch/arm/mm/proc-v7.S | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index a18aace32990..095b69f5a833 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -232,14 +232,14 @@ __v7_setup: ENDPROC(__v7_setup) /* AT - * TFR EV X F I D LR - * .EEE ..EE PUI. .T.T 4RVI ZFRS BLDP WCAM + * TFR EV X F I D LR S + * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced - * 1 0 110 0011 1.00 .111 1101 < we want + * 1 0 110 0011 1100 .111 1101 < we want */ .type v7_crval, #object v7_crval: - crval clear=0x0120c302, mmuset=0x10c0387d, ucset=0x00c0187c + crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c __v7_setup_stack: .space 4 * 11 @ 11 registers -- cgit v1.2.2 From 23d1c515d8fc6d74bea442a4b687c3b5b8627ec4 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Sat, 30 May 2009 14:00:16 +0100 Subject: ARMv7: Document the PRRR and NMRR registers setting This patch adds a comment to the proc-v7.S file for the setting of the PRRR and NMRR registers. It also sets the PRRR[13:12] bits to 0 (corresponding to the reserved TEX[0]CB encoding 110) to be consistent with the documentation. Signed-off-by: Catalin Marinas --- arch/arm/mm/proc-v7.S | 32 ++++++++++++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 095b69f5a833..0a8ffd3c03fd 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -219,8 +219,36 @@ __v7_setup: mov r10, #0x1f @ domains 0, 1 = manager mcr p15, 0, r10, c3, c0, 0 @ load domain access register #endif - ldr r5, =0xff0aa1a8 - ldr r6, =0x40e040e0 + /* + * Memory region attributes with SCTLR.TRE=1 + * + * n = TEX[0],C,B + * TR = PRRR[2n+1:2n] - memory type + * IR = NMRR[2n+1:2n] - inner cacheable property + * OR = NMRR[2n+17:2n+16] - outer cacheable property + * + * n TR IR OR + * UNCACHED 000 00 + * BUFFERABLE 001 10 00 00 + * WRITETHROUGH 010 10 10 10 + * WRITEBACK 011 10 11 11 + * reserved 110 + * WRITEALLOC 111 10 01 01 + * DEV_SHARED 100 01 + * DEV_NONSHARED 100 01 + * DEV_WC 001 10 + * DEV_CACHED 011 10 + * + * Other attributes: + * + * DS0 = PRRR[16] = 0 - device shareable property + * DS1 = PRRR[17] = 1 - device shareable property + * NS0 = PRRR[18] = 0 - normal shareable property + * NS1 = PRRR[19] = 1 - normal shareable property + * NOS = PRRR[24+n] = 1 - not outer shareable + */ + ldr r5, =0xff0a81a8 @ PRRR + ldr r6, =0x40e040e0 @ NMRR mcr p15, 0, r5, c10, c2, 0 @ write PRRR mcr p15, 0, r6, c10, c2, 1 @ write NMRR adr r5, v7_crval -- cgit v1.2.2 From 8c7e65742fd05f27071282d260376adb98e0e9ac Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Sat, 30 May 2009 14:00:17 +0100 Subject: arm: Provide _sdata and __bss_stop in the vmlinux.lds.S file _sdata and __bss_stop are common symbols defined by many architectures and made available to the kernel via asm-generic/sections.h. Kmemleak uses these symbols when scanning the data sections. Signed-off-by: Catalin Marinas --- arch/arm/kernel/vmlinux.lds.S | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index c90f27250ead..6c0779792546 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S @@ -141,6 +141,7 @@ SECTIONS .data : AT(__data_loc) { _data = .; /* address in memory */ + _sdata = .; /* * first, the init task union, aligned @@ -192,6 +193,7 @@ SECTIONS __bss_start = .; /* BSS */ *(.bss) *(COMMON) + __bss_stop = .; _end = .; } /* Stabs debugging sections. */ -- cgit v1.2.2 From ee8c9571191e588ede9a220ded807e33c4897d91 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Sat, 30 May 2009 14:00:17 +0100 Subject: RealView: Move the IRQ_* definitions out of the board-*.h files The IRQ_* macros need to be made visible via the mach/irqs.h file but without the additional macros defined in the board-*.h files. Signed-off-by: Catalin Marinas --- arch/arm/mach-realview/core.c | 3 + arch/arm/mach-realview/include/mach/board-eb.h | 105 ----------------- arch/arm/mach-realview/include/mach/board-pb1176.h | 78 ------------- arch/arm/mach-realview/include/mach/board-pb11mp.h | 101 ---------------- arch/arm/mach-realview/include/mach/board-pba8.h | 77 ------------ arch/arm/mach-realview/include/mach/board-pbx.h | 95 --------------- arch/arm/mach-realview/include/mach/irqs-eb.h | 129 +++++++++++++++++++++ arch/arm/mach-realview/include/mach/irqs-pb1176.h | 99 ++++++++++++++++ arch/arm/mach-realview/include/mach/irqs-pb11mp.h | 122 +++++++++++++++++++ arch/arm/mach-realview/include/mach/irqs-pba8.h | 98 ++++++++++++++++ arch/arm/mach-realview/include/mach/irqs-pbx.h | 115 ++++++++++++++++++ arch/arm/mach-realview/include/mach/irqs.h | 10 +- arch/arm/oprofile/op_model_mpcore.c | 1 + 13 files changed, 572 insertions(+), 461 deletions(-) create mode 100644 arch/arm/mach-realview/include/mach/irqs-eb.h create mode 100644 arch/arm/mach-realview/include/mach/irqs-pb1176.h create mode 100644 arch/arm/mach-realview/include/mach/irqs-pb11mp.h create mode 100644 arch/arm/mach-realview/include/mach/irqs-pba8.h create mode 100644 arch/arm/mach-realview/include/mach/irqs-pbx.h (limited to 'arch/arm') diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 346cbf0cd13e..9ea9c05093cd 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -48,6 +48,9 @@ #include +#include +#include + #include "core.h" #include "clock.h" diff --git a/arch/arm/mach-realview/include/mach/board-eb.h b/arch/arm/mach-realview/include/mach/board-eb.h index 268d7701fa9b..794a8d91a6a6 100644 --- a/arch/arm/mach-realview/include/mach/board-eb.h +++ b/arch/arm/mach-realview/include/mach/board-eb.h @@ -62,111 +62,6 @@ #define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */ #endif -#define IRQ_EB_GIC_START 32 - -/* - * RealView EB interrupt sources - */ -#define IRQ_EB_WDOG (IRQ_EB_GIC_START + 0) /* Watchdog timer */ -#define IRQ_EB_SOFT (IRQ_EB_GIC_START + 1) /* Software interrupt */ -#define IRQ_EB_COMMRx (IRQ_EB_GIC_START + 2) /* Debug Comm Rx interrupt */ -#define IRQ_EB_COMMTx (IRQ_EB_GIC_START + 3) /* Debug Comm Tx interrupt */ -#define IRQ_EB_TIMER0_1 (IRQ_EB_GIC_START + 4) /* Timer 0 and 1 */ -#define IRQ_EB_TIMER2_3 (IRQ_EB_GIC_START + 5) /* Timer 2 and 3 */ -#define IRQ_EB_GPIO0 (IRQ_EB_GIC_START + 6) /* GPIO 0 */ -#define IRQ_EB_GPIO1 (IRQ_EB_GIC_START + 7) /* GPIO 1 */ -#define IRQ_EB_GPIO2 (IRQ_EB_GIC_START + 8) /* GPIO 2 */ - /* 9 reserved */ -#define IRQ_EB_RTC (IRQ_EB_GIC_START + 10) /* Real Time Clock */ -#define IRQ_EB_SSP (IRQ_EB_GIC_START + 11) /* Synchronous Serial Port */ -#define IRQ_EB_UART0 (IRQ_EB_GIC_START + 12) /* UART 0 on development chip */ -#define IRQ_EB_UART1 (IRQ_EB_GIC_START + 13) /* UART 1 on development chip */ -#define IRQ_EB_UART2 (IRQ_EB_GIC_START + 14) /* UART 2 on development chip */ -#define IRQ_EB_UART3 (IRQ_EB_GIC_START + 15) /* UART 3 on development chip */ -#define IRQ_EB_SCI (IRQ_EB_GIC_START + 16) /* Smart Card Interface */ -#define IRQ_EB_MMCI0A (IRQ_EB_GIC_START + 17) /* Multimedia Card 0A */ -#define IRQ_EB_MMCI0B (IRQ_EB_GIC_START + 18) /* Multimedia Card 0B */ -#define IRQ_EB_AACI (IRQ_EB_GIC_START + 19) /* Audio Codec */ -#define IRQ_EB_KMI0 (IRQ_EB_GIC_START + 20) /* Keyboard/Mouse port 0 */ -#define IRQ_EB_KMI1 (IRQ_EB_GIC_START + 21) /* Keyboard/Mouse port 1 */ -#define IRQ_EB_CHARLCD (IRQ_EB_GIC_START + 22) /* Character LCD */ -#define IRQ_EB_CLCD (IRQ_EB_GIC_START + 23) /* CLCD controller */ -#define IRQ_EB_DMA (IRQ_EB_GIC_START + 24) /* DMA controller */ -#define IRQ_EB_PWRFAIL (IRQ_EB_GIC_START + 25) /* Power failure */ -#define IRQ_EB_PISMO (IRQ_EB_GIC_START + 26) /* PISMO interface */ -#define IRQ_EB_DoC (IRQ_EB_GIC_START + 27) /* Disk on Chip memory controller */ -#define IRQ_EB_ETH (IRQ_EB_GIC_START + 28) /* Ethernet controller */ -#define IRQ_EB_USB (IRQ_EB_GIC_START + 29) /* USB controller */ -#define IRQ_EB_TSPEN (IRQ_EB_GIC_START + 30) /* Touchscreen pen */ -#define IRQ_EB_TSKPAD (IRQ_EB_GIC_START + 31) /* Touchscreen keypad */ - -/* - * RealView EB + ARM11MPCore interrupt sources (primary GIC on the core tile) - */ -#define IRQ_EB11MP_AACI (IRQ_EB_GIC_START + 0) -#define IRQ_EB11MP_TIMER0_1 (IRQ_EB_GIC_START + 1) -#define IRQ_EB11MP_TIMER2_3 (IRQ_EB_GIC_START + 2) -#define IRQ_EB11MP_USB (IRQ_EB_GIC_START + 3) -#define IRQ_EB11MP_UART0 (IRQ_EB_GIC_START + 4) -#define IRQ_EB11MP_UART1 (IRQ_EB_GIC_START + 5) -#define IRQ_EB11MP_RTC (IRQ_EB_GIC_START + 6) -#define IRQ_EB11MP_KMI0 (IRQ_EB_GIC_START + 7) -#define IRQ_EB11MP_KMI1 (IRQ_EB_GIC_START + 8) -#define IRQ_EB11MP_ETH (IRQ_EB_GIC_START + 9) -#define IRQ_EB11MP_EB_IRQ1 (IRQ_EB_GIC_START + 10) /* main GIC */ -#define IRQ_EB11MP_EB_IRQ2 (IRQ_EB_GIC_START + 11) /* tile GIC */ -#define IRQ_EB11MP_EB_FIQ1 (IRQ_EB_GIC_START + 12) /* main GIC */ -#define IRQ_EB11MP_EB_FIQ2 (IRQ_EB_GIC_START + 13) /* tile GIC */ -#define IRQ_EB11MP_MMCI0A (IRQ_EB_GIC_START + 14) -#define IRQ_EB11MP_MMCI0B (IRQ_EB_GIC_START + 15) - -#define IRQ_EB11MP_PMU_CPU0 (IRQ_EB_GIC_START + 17) -#define IRQ_EB11MP_PMU_CPU1 (IRQ_EB_GIC_START + 18) -#define IRQ_EB11MP_PMU_CPU2 (IRQ_EB_GIC_START + 19) -#define IRQ_EB11MP_PMU_CPU3 (IRQ_EB_GIC_START + 20) -#define IRQ_EB11MP_PMU_SCU0 (IRQ_EB_GIC_START + 21) -#define IRQ_EB11MP_PMU_SCU1 (IRQ_EB_GIC_START + 22) -#define IRQ_EB11MP_PMU_SCU2 (IRQ_EB_GIC_START + 23) -#define IRQ_EB11MP_PMU_SCU3 (IRQ_EB_GIC_START + 24) -#define IRQ_EB11MP_PMU_SCU4 (IRQ_EB_GIC_START + 25) -#define IRQ_EB11MP_PMU_SCU5 (IRQ_EB_GIC_START + 26) -#define IRQ_EB11MP_PMU_SCU6 (IRQ_EB_GIC_START + 27) -#define IRQ_EB11MP_PMU_SCU7 (IRQ_EB_GIC_START + 28) - -#define IRQ_EB11MP_L220_EVENT (IRQ_EB_GIC_START + 29) -#define IRQ_EB11MP_L220_SLAVE (IRQ_EB_GIC_START + 30) -#define IRQ_EB11MP_L220_DECODE (IRQ_EB_GIC_START + 31) - -#define IRQ_EB11MP_UART2 -1 -#define IRQ_EB11MP_UART3 -1 -#define IRQ_EB11MP_CLCD -1 -#define IRQ_EB11MP_DMA -1 -#define IRQ_EB11MP_WDOG -1 -#define IRQ_EB11MP_GPIO0 -1 -#define IRQ_EB11MP_GPIO1 -1 -#define IRQ_EB11MP_GPIO2 -1 -#define IRQ_EB11MP_SCI -1 -#define IRQ_EB11MP_SSP -1 - -#define NR_GIC_EB11MP 2 - -/* - * Only define NR_IRQS if less than NR_IRQS_EB - */ -#define NR_IRQS_EB (IRQ_EB_GIC_START + 96) - -#if defined(CONFIG_MACH_REALVIEW_EB) \ - && (!defined(NR_IRQS) || (NR_IRQS < NR_IRQS_EB)) -#undef NR_IRQS -#define NR_IRQS NR_IRQS_EB -#endif - -#if defined(CONFIG_REALVIEW_EB_ARM11MP) || defined(CONFIG_REALVIEW_EB_A9MP) \ - && (!defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_EB11MP)) -#undef MAX_GIC_NR -#define MAX_GIC_NR NR_GIC_EB11MP -#endif - /* * Core tile identification (REALVIEW_SYS_PROCID) */ diff --git a/arch/arm/mach-realview/include/mach/board-pb1176.h b/arch/arm/mach-realview/include/mach/board-pb1176.h index e4d0e8046ea5..98f8e7eeacc2 100644 --- a/arch/arm/mach-realview/include/mach/board-pb1176.h +++ b/arch/arm/mach-realview/include/mach/board-pb1176.h @@ -73,82 +73,4 @@ #define REALVIEW_PB1176_GIC_DIST_BASE 0x10041000 /* GIC distributor, on FPGA */ #define REALVIEW_PB1176_L220_BASE 0x10110000 /* L220 registers */ -/* - * Irqs - */ -#define IRQ_DC1176_GIC_START 32 -#define IRQ_PB1176_GIC_START 64 - -/* - * ARM1176 DevChip interrupt sources (primary GIC) - */ -#define IRQ_DC1176_WATCHDOG (IRQ_DC1176_GIC_START + 0) /* Watchdog timer */ -#define IRQ_DC1176_SOFTINT (IRQ_DC1176_GIC_START + 1) /* Software interrupt */ -#define IRQ_DC1176_COMMRx (IRQ_DC1176_GIC_START + 2) /* Debug Comm Rx interrupt */ -#define IRQ_DC1176_COMMTx (IRQ_DC1176_GIC_START + 3) /* Debug Comm Tx interrupt */ -#define IRQ_DC1176_TIMER0 (IRQ_DC1176_GIC_START + 8) /* Timer 0 */ -#define IRQ_DC1176_TIMER1 (IRQ_DC1176_GIC_START + 9) /* Timer 1 */ -#define IRQ_DC1176_TIMER2 (IRQ_DC1176_GIC_START + 10) /* Timer 2 */ -#define IRQ_DC1176_APC (IRQ_DC1176_GIC_START + 11) -#define IRQ_DC1176_IEC (IRQ_DC1176_GIC_START + 12) -#define IRQ_DC1176_L2CC (IRQ_DC1176_GIC_START + 13) -#define IRQ_DC1176_RTC (IRQ_DC1176_GIC_START + 14) -#define IRQ_DC1176_CLCD (IRQ_DC1176_GIC_START + 15) /* CLCD controller */ -#define IRQ_DC1176_UART0 (IRQ_DC1176_GIC_START + 18) /* UART 0 on development chip */ -#define IRQ_DC1176_UART1 (IRQ_DC1176_GIC_START + 19) /* UART 1 on development chip */ -#define IRQ_DC1176_UART2 (IRQ_DC1176_GIC_START + 20) /* UART 2 on development chip */ -#define IRQ_DC1176_UART3 (IRQ_DC1176_GIC_START + 21) /* UART 3 on development chip */ - -#define IRQ_DC1176_PB_IRQ2 (IRQ_DC1176_GIC_START + 30) /* tile GIC */ -#define IRQ_DC1176_PB_IRQ1 (IRQ_DC1176_GIC_START + 31) /* main GIC */ - -/* - * RealView PB1176 interrupt sources (secondary GIC) - */ -#define IRQ_PB1176_MMCI0A (IRQ_PB1176_GIC_START + 1) /* Multimedia Card 0A */ -#define IRQ_PB1176_MMCI0B (IRQ_PB1176_GIC_START + 2) /* Multimedia Card 0A */ -#define IRQ_PB1176_KMI0 (IRQ_PB1176_GIC_START + 3) /* Keyboard/Mouse port 0 */ -#define IRQ_PB1176_KMI1 (IRQ_PB1176_GIC_START + 4) /* Keyboard/Mouse port 1 */ -#define IRQ_PB1176_SCI (IRQ_PB1176_GIC_START + 5) -#define IRQ_PB1176_UART4 (IRQ_PB1176_GIC_START + 6) /* UART 4 on baseboard */ -#define IRQ_PB1176_CHARLCD (IRQ_PB1176_GIC_START + 7) /* Character LCD */ -#define IRQ_PB1176_GPIO1 (IRQ_PB1176_GIC_START + 8) -#define IRQ_PB1176_GPIO2 (IRQ_PB1176_GIC_START + 9) -#define IRQ_PB1176_ETH (IRQ_PB1176_GIC_START + 10) /* Ethernet controller */ -#define IRQ_PB1176_USB (IRQ_PB1176_GIC_START + 11) /* USB controller */ - -#define IRQ_PB1176_PISMO (IRQ_PB1176_GIC_START + 16) - -#define IRQ_PB1176_AACI (IRQ_PB1176_GIC_START + 19) /* Audio Codec */ - -#define IRQ_PB1176_TIMER0_1 (IRQ_PB1176_GIC_START + 22) -#define IRQ_PB1176_TIMER2_3 (IRQ_PB1176_GIC_START + 23) -#define IRQ_PB1176_DMAC (IRQ_PB1176_GIC_START + 24) /* DMA controller */ -#define IRQ_PB1176_RTC (IRQ_PB1176_GIC_START + 25) /* Real Time Clock */ - -#define IRQ_PB1176_GPIO0 -1 -#define IRQ_PB1176_SSP -1 -#define IRQ_PB1176_SCTL -1 - -#define NR_GIC_PB1176 2 - -/* - * Only define NR_IRQS if less than NR_IRQS_PB1176 - */ -#define NR_IRQS_PB1176 (IRQ_DC1176_GIC_START + 96) - -#if defined(CONFIG_MACH_REALVIEW_PB1176) - -#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB1176) -#undef NR_IRQS -#define NR_IRQS NR_IRQS_PB1176 -#endif - -#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB1176) -#undef MAX_GIC_NR -#define MAX_GIC_NR NR_GIC_PB1176 -#endif - -#endif /* CONFIG_MACH_REALVIEW_PB1176 */ - #endif /* __ASM_ARCH_BOARD_PB1176_H */ diff --git a/arch/arm/mach-realview/include/mach/board-pb11mp.h b/arch/arm/mach-realview/include/mach/board-pb11mp.h index 53ea0e7a1267..f0d68e0fea01 100644 --- a/arch/arm/mach-realview/include/mach/board-pb11mp.h +++ b/arch/arm/mach-realview/include/mach/board-pb11mp.h @@ -81,105 +81,4 @@ #define REALVIEW_TC11MP_GIC_DIST_BASE 0x1F001000 /* Test chip interrupt controller distributor */ #define REALVIEW_TC11MP_L220_BASE 0x1F002000 /* L220 registers */ -/* - * Irqs - */ -#define IRQ_TC11MP_GIC_START 32 -#define IRQ_PB11MP_GIC_START 64 - -/* - * ARM11MPCore test chip interrupt sources (primary GIC on the test chip) - */ -#define IRQ_TC11MP_AACI (IRQ_TC11MP_GIC_START + 0) -#define IRQ_TC11MP_TIMER0_1 (IRQ_TC11MP_GIC_START + 1) -#define IRQ_TC11MP_TIMER2_3 (IRQ_TC11MP_GIC_START + 2) -#define IRQ_TC11MP_USB (IRQ_TC11MP_GIC_START + 3) -#define IRQ_TC11MP_UART0 (IRQ_TC11MP_GIC_START + 4) -#define IRQ_TC11MP_UART1 (IRQ_TC11MP_GIC_START + 5) -#define IRQ_TC11MP_RTC (IRQ_TC11MP_GIC_START + 6) -#define IRQ_TC11MP_KMI0 (IRQ_TC11MP_GIC_START + 7) -#define IRQ_TC11MP_KMI1 (IRQ_TC11MP_GIC_START + 8) -#define IRQ_TC11MP_ETH (IRQ_TC11MP_GIC_START + 9) -#define IRQ_TC11MP_PB_IRQ1 (IRQ_TC11MP_GIC_START + 10) /* main GIC */ -#define IRQ_TC11MP_PB_IRQ2 (IRQ_TC11MP_GIC_START + 11) /* tile GIC */ -#define IRQ_TC11MP_PB_FIQ1 (IRQ_TC11MP_GIC_START + 12) /* main GIC */ -#define IRQ_TC11MP_PB_FIQ2 (IRQ_TC11MP_GIC_START + 13) /* tile GIC */ -#define IRQ_TC11MP_MMCI0A (IRQ_TC11MP_GIC_START + 14) -#define IRQ_TC11MP_MMCI0B (IRQ_TC11MP_GIC_START + 15) - -#define IRQ_TC11MP_PMU_CPU0 (IRQ_TC11MP_GIC_START + 17) -#define IRQ_TC11MP_PMU_CPU1 (IRQ_TC11MP_GIC_START + 18) -#define IRQ_TC11MP_PMU_CPU2 (IRQ_TC11MP_GIC_START + 19) -#define IRQ_TC11MP_PMU_CPU3 (IRQ_TC11MP_GIC_START + 20) -#define IRQ_TC11MP_PMU_SCU0 (IRQ_TC11MP_GIC_START + 21) -#define IRQ_TC11MP_PMU_SCU1 (IRQ_TC11MP_GIC_START + 22) -#define IRQ_TC11MP_PMU_SCU2 (IRQ_TC11MP_GIC_START + 23) -#define IRQ_TC11MP_PMU_SCU3 (IRQ_TC11MP_GIC_START + 24) -#define IRQ_TC11MP_PMU_SCU4 (IRQ_TC11MP_GIC_START + 25) -#define IRQ_TC11MP_PMU_SCU5 (IRQ_TC11MP_GIC_START + 26) -#define IRQ_TC11MP_PMU_SCU6 (IRQ_TC11MP_GIC_START + 27) -#define IRQ_TC11MP_PMU_SCU7 (IRQ_TC11MP_GIC_START + 28) - -#define IRQ_TC11MP_L220_EVENT (IRQ_TC11MP_GIC_START + 29) -#define IRQ_TC11MP_L220_SLAVE (IRQ_TC11MP_GIC_START + 30) -#define IRQ_TC11MP_L220_DECODE (IRQ_TC11MP_GIC_START + 31) - -/* - * RealView PB11MPCore GIC interrupt sources (secondary GIC on the board) - */ -#define IRQ_PB11MP_WATCHDOG (IRQ_PB11MP_GIC_START + 0) /* Watchdog timer */ -#define IRQ_PB11MP_SOFT (IRQ_PB11MP_GIC_START + 1) /* Software interrupt */ -#define IRQ_PB11MP_COMMRx (IRQ_PB11MP_GIC_START + 2) /* Debug Comm Rx interrupt */ -#define IRQ_PB11MP_COMMTx (IRQ_PB11MP_GIC_START + 3) /* Debug Comm Tx interrupt */ -#define IRQ_PB11MP_GPIO0 (IRQ_PB11MP_GIC_START + 6) /* GPIO 0 */ -#define IRQ_PB11MP_GPIO1 (IRQ_PB11MP_GIC_START + 7) /* GPIO 1 */ -#define IRQ_PB11MP_GPIO2 (IRQ_PB11MP_GIC_START + 8) /* GPIO 2 */ - /* 9 reserved */ -#define IRQ_PB11MP_RTC_GIC1 (IRQ_PB11MP_GIC_START + 10) /* Real Time Clock */ -#define IRQ_PB11MP_SSP (IRQ_PB11MP_GIC_START + 11) /* Synchronous Serial Port */ -#define IRQ_PB11MP_UART0_GIC1 (IRQ_PB11MP_GIC_START + 12) /* UART 0 on development chip */ -#define IRQ_PB11MP_UART1_GIC1 (IRQ_PB11MP_GIC_START + 13) /* UART 1 on development chip */ -#define IRQ_PB11MP_UART2 (IRQ_PB11MP_GIC_START + 14) /* UART 2 on development chip */ -#define IRQ_PB11MP_UART3 (IRQ_PB11MP_GIC_START + 15) /* UART 3 on development chip */ -#define IRQ_PB11MP_SCI (IRQ_PB11MP_GIC_START + 16) /* Smart Card Interface */ -#define IRQ_PB11MP_MMCI0A_GIC1 (IRQ_PB11MP_GIC_START + 17) /* Multimedia Card 0A */ -#define IRQ_PB11MP_MMCI0B_GIC1 (IRQ_PB11MP_GIC_START + 18) /* Multimedia Card 0B */ -#define IRQ_PB11MP_AACI_GIC1 (IRQ_PB11MP_GIC_START + 19) /* Audio Codec */ -#define IRQ_PB11MP_KMI0_GIC1 (IRQ_PB11MP_GIC_START + 20) /* Keyboard/Mouse port 0 */ -#define IRQ_PB11MP_KMI1_GIC1 (IRQ_PB11MP_GIC_START + 21) /* Keyboard/Mouse port 1 */ -#define IRQ_PB11MP_CHARLCD (IRQ_PB11MP_GIC_START + 22) /* Character LCD */ -#define IRQ_PB11MP_CLCD (IRQ_PB11MP_GIC_START + 23) /* CLCD controller */ -#define IRQ_PB11MP_DMAC (IRQ_PB11MP_GIC_START + 24) /* DMA controller */ -#define IRQ_PB11MP_PWRFAIL (IRQ_PB11MP_GIC_START + 25) /* Power failure */ -#define IRQ_PB11MP_PISMO (IRQ_PB11MP_GIC_START + 26) /* PISMO interface */ -#define IRQ_PB11MP_DoC (IRQ_PB11MP_GIC_START + 27) /* Disk on Chip memory controller */ -#define IRQ_PB11MP_ETH_GIC1 (IRQ_PB11MP_GIC_START + 28) /* Ethernet controller */ -#define IRQ_PB11MP_USB_GIC1 (IRQ_PB11MP_GIC_START + 29) /* USB controller */ -#define IRQ_PB11MP_TSPEN (IRQ_PB11MP_GIC_START + 30) /* Touchscreen pen */ -#define IRQ_PB11MP_TSKPAD (IRQ_PB11MP_GIC_START + 31) /* Touchscreen keypad */ - -#define IRQ_PB11MP_SMC -1 -#define IRQ_PB11MP_SCTL -1 - -#define NR_GIC_PB11MP 2 - -/* - * Only define NR_IRQS if less than NR_IRQS_PB11MP - */ -#define NR_IRQS_PB11MP (IRQ_TC11MP_GIC_START + 96) - -#if defined(CONFIG_MACH_REALVIEW_PB11MP) - -#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB11MP) -#undef NR_IRQS -#define NR_IRQS NR_IRQS_PB11MP -#endif - -#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB11MP) -#undef MAX_GIC_NR -#define MAX_GIC_NR NR_GIC_PB11MP -#endif - -#endif /* CONFIG_MACH_REALVIEW_PB11MP */ - #endif /* __ASM_ARCH_BOARD_PB11MP_H */ diff --git a/arch/arm/mach-realview/include/mach/board-pba8.h b/arch/arm/mach-realview/include/mach/board-pba8.h index 307f97b16e5b..4dfc67a4f45f 100644 --- a/arch/arm/mach-realview/include/mach/board-pba8.h +++ b/arch/arm/mach-realview/include/mach/board-pba8.h @@ -70,81 +70,4 @@ #define REALVIEW_PBA8_PCI_IO_SIZE 0x1000 /* 4 Kb */ #define REALVIEW_PBA8_PCI_MEM_SIZE 0x20000000 /* 512 MB */ -/* - * Irqs - */ -#define IRQ_PBA8_GIC_START 32 - -/* L220 -#define IRQ_PBA8_L220_EVENT (IRQ_PBA8_GIC_START + 29) -#define IRQ_PBA8_L220_SLAVE (IRQ_PBA8_GIC_START + 30) -#define IRQ_PBA8_L220_DECODE (IRQ_PBA8_GIC_START + 31) -*/ - -/* - * PB-A8 on-board gic irq sources - */ -#define IRQ_PBA8_WATCHDOG (IRQ_PBA8_GIC_START + 0) /* Watchdog timer */ -#define IRQ_PBA8_SOFT (IRQ_PBA8_GIC_START + 1) /* Software interrupt */ -#define IRQ_PBA8_COMMRx (IRQ_PBA8_GIC_START + 2) /* Debug Comm Rx interrupt */ -#define IRQ_PBA8_COMMTx (IRQ_PBA8_GIC_START + 3) /* Debug Comm Tx interrupt */ -#define IRQ_PBA8_TIMER0_1 (IRQ_PBA8_GIC_START + 4) /* Timer 0/1 (default timer) */ -#define IRQ_PBA8_TIMER2_3 (IRQ_PBA8_GIC_START + 5) /* Timer 2/3 */ -#define IRQ_PBA8_GPIO0 (IRQ_PBA8_GIC_START + 6) /* GPIO 0 */ -#define IRQ_PBA8_GPIO1 (IRQ_PBA8_GIC_START + 7) /* GPIO 1 */ -#define IRQ_PBA8_GPIO2 (IRQ_PBA8_GIC_START + 8) /* GPIO 2 */ - /* 9 reserved */ -#define IRQ_PBA8_RTC (IRQ_PBA8_GIC_START + 10) /* Real Time Clock */ -#define IRQ_PBA8_SSP (IRQ_PBA8_GIC_START + 11) /* Synchronous Serial Port */ -#define IRQ_PBA8_UART0 (IRQ_PBA8_GIC_START + 12) /* UART 0 on development chip */ -#define IRQ_PBA8_UART1 (IRQ_PBA8_GIC_START + 13) /* UART 1 on development chip */ -#define IRQ_PBA8_UART2 (IRQ_PBA8_GIC_START + 14) /* UART 2 on development chip */ -#define IRQ_PBA8_UART3 (IRQ_PBA8_GIC_START + 15) /* UART 3 on development chip */ -#define IRQ_PBA8_SCI (IRQ_PBA8_GIC_START + 16) /* Smart Card Interface */ -#define IRQ_PBA8_MMCI0A (IRQ_PBA8_GIC_START + 17) /* Multimedia Card 0A */ -#define IRQ_PBA8_MMCI0B (IRQ_PBA8_GIC_START + 18) /* Multimedia Card 0B */ -#define IRQ_PBA8_AACI (IRQ_PBA8_GIC_START + 19) /* Audio Codec */ -#define IRQ_PBA8_KMI0 (IRQ_PBA8_GIC_START + 20) /* Keyboard/Mouse port 0 */ -#define IRQ_PBA8_KMI1 (IRQ_PBA8_GIC_START + 21) /* Keyboard/Mouse port 1 */ -#define IRQ_PBA8_CHARLCD (IRQ_PBA8_GIC_START + 22) /* Character LCD */ -#define IRQ_PBA8_CLCD (IRQ_PBA8_GIC_START + 23) /* CLCD controller */ -#define IRQ_PBA8_DMAC (IRQ_PBA8_GIC_START + 24) /* DMA controller */ -#define IRQ_PBA8_PWRFAIL (IRQ_PBA8_GIC_START + 25) /* Power failure */ -#define IRQ_PBA8_PISMO (IRQ_PBA8_GIC_START + 26) /* PISMO interface */ -#define IRQ_PBA8_DoC (IRQ_PBA8_GIC_START + 27) /* Disk on Chip memory controller */ -#define IRQ_PBA8_ETH (IRQ_PBA8_GIC_START + 28) /* Ethernet controller */ -#define IRQ_PBA8_USB (IRQ_PBA8_GIC_START + 29) /* USB controller */ -#define IRQ_PBA8_TSPEN (IRQ_PBA8_GIC_START + 30) /* Touchscreen pen */ -#define IRQ_PBA8_TSKPAD (IRQ_PBA8_GIC_START + 31) /* Touchscreen keypad */ - -/* ... */ -#define IRQ_PBA8_PCI0 (IRQ_PBA8_GIC_START + 50) -#define IRQ_PBA8_PCI1 (IRQ_PBA8_GIC_START + 51) -#define IRQ_PBA8_PCI2 (IRQ_PBA8_GIC_START + 52) -#define IRQ_PBA8_PCI3 (IRQ_PBA8_GIC_START + 53) - -#define IRQ_PBA8_SMC -1 -#define IRQ_PBA8_SCTL -1 - -#define NR_GIC_PBA8 1 - -/* - * Only define NR_IRQS if less than NR_IRQS_PBA8 - */ -#define NR_IRQS_PBA8 (IRQ_PBA8_GIC_START + 64) - -#if defined(CONFIG_MACH_REALVIEW_PBA8) - -#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PBA8) -#undef NR_IRQS -#define NR_IRQS NR_IRQS_PBA8 -#endif - -#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PBA8) -#undef MAX_GIC_NR -#define MAX_GIC_NR NR_GIC_PBA8 -#endif - -#endif /* CONFIG_MACH_REALVIEW_PBA8 */ - #endif /* __ASM_ARCH_BOARD_PBA8_H */ diff --git a/arch/arm/mach-realview/include/mach/board-pbx.h b/arch/arm/mach-realview/include/mach/board-pbx.h index c26509388828..848bfff6d8f1 100644 --- a/arch/arm/mach-realview/include/mach/board-pbx.h +++ b/arch/arm/mach-realview/include/mach/board-pbx.h @@ -80,101 +80,6 @@ #define REALVIEW_PBX_PCI_IO_SIZE 0x1000 /* 4 Kb */ #define REALVIEW_PBX_PCI_MEM_SIZE 0x20000000 /* 512 MB */ -/* - * Irqs - */ -#define IRQ_PBX_GIC_START 32 - -/* L220 -#define IRQ_PBX_L220_EVENT (IRQ_PBX_GIC_START + 29) -#define IRQ_PBX_L220_SLAVE (IRQ_PBX_GIC_START + 30) -#define IRQ_PBX_L220_DECODE (IRQ_PBX_GIC_START + 31) -*/ - -/* - * PB-X on-board gic irq sources - */ -#define IRQ_PBX_WATCHDOG (IRQ_PBX_GIC_START + 0) /* Watchdog timer */ -#define IRQ_PBX_SOFT (IRQ_PBX_GIC_START + 1) /* Software interrupt */ -#define IRQ_PBX_COMMRx (IRQ_PBX_GIC_START + 2) /* Debug Comm Rx interrupt */ -#define IRQ_PBX_COMMTx (IRQ_PBX_GIC_START + 3) /* Debug Comm Tx interrupt */ -#define IRQ_PBX_TIMER0_1 (IRQ_PBX_GIC_START + 4) /* Timer 0/1 (default timer) */ -#define IRQ_PBX_TIMER2_3 (IRQ_PBX_GIC_START + 5) /* Timer 2/3 */ -#define IRQ_PBX_GPIO0 (IRQ_PBX_GIC_START + 6) /* GPIO 0 */ -#define IRQ_PBX_GPIO1 (IRQ_PBX_GIC_START + 7) /* GPIO 1 */ -#define IRQ_PBX_GPIO2 (IRQ_PBX_GIC_START + 8) /* GPIO 2 */ - /* 9 reserved */ -#define IRQ_PBX_RTC (IRQ_PBX_GIC_START + 10) /* Real Time Clock */ -#define IRQ_PBX_SSP (IRQ_PBX_GIC_START + 11) /* Synchronous Serial Port */ -#define IRQ_PBX_UART0 (IRQ_PBX_GIC_START + 12) /* UART 0 on development chip */ -#define IRQ_PBX_UART1 (IRQ_PBX_GIC_START + 13) /* UART 1 on development chip */ -#define IRQ_PBX_UART2 (IRQ_PBX_GIC_START + 14) /* UART 2 on development chip */ -#define IRQ_PBX_UART3 (IRQ_PBX_GIC_START + 15) /* UART 3 on development chip */ -#define IRQ_PBX_SCI (IRQ_PBX_GIC_START + 16) /* Smart Card Interface */ -#define IRQ_PBX_MMCI0A (IRQ_PBX_GIC_START + 17) /* Multimedia Card 0A */ -#define IRQ_PBX_MMCI0B (IRQ_PBX_GIC_START + 18) /* Multimedia Card 0B */ -#define IRQ_PBX_AACI (IRQ_PBX_GIC_START + 19) /* Audio Codec */ -#define IRQ_PBX_KMI0 (IRQ_PBX_GIC_START + 20) /* Keyboard/Mouse port 0 */ -#define IRQ_PBX_KMI1 (IRQ_PBX_GIC_START + 21) /* Keyboard/Mouse port 1 */ -#define IRQ_PBX_CHARLCD (IRQ_PBX_GIC_START + 22) /* Character LCD */ -#define IRQ_PBX_CLCD (IRQ_PBX_GIC_START + 23) /* CLCD controller */ -#define IRQ_PBX_DMAC (IRQ_PBX_GIC_START + 24) /* DMA controller */ -#define IRQ_PBX_PWRFAIL (IRQ_PBX_GIC_START + 25) /* Power failure */ -#define IRQ_PBX_PISMO (IRQ_PBX_GIC_START + 26) /* PISMO interface */ -#define IRQ_PBX_DoC (IRQ_PBX_GIC_START + 27) /* Disk on Chip memory controller */ -#define IRQ_PBX_ETH (IRQ_PBX_GIC_START + 28) /* Ethernet controller */ -#define IRQ_PBX_USB (IRQ_PBX_GIC_START + 29) /* USB controller */ -#define IRQ_PBX_TSPEN (IRQ_PBX_GIC_START + 30) /* Touchscreen pen */ -#define IRQ_PBX_TSKPAD (IRQ_PBX_GIC_START + 31) /* Touchscreen keypad */ - -#define IRQ_PBX_PMU_SCU0 (IRQ_PBX_GIC_START + 32) /* SCU PMU Interrupts (11mp) */ -#define IRQ_PBX_PMU_SCU1 (IRQ_PBX_GIC_START + 33) -#define IRQ_PBX_PMU_SCU2 (IRQ_PBX_GIC_START + 34) -#define IRQ_PBX_PMU_SCU3 (IRQ_PBX_GIC_START + 35) -#define IRQ_PBX_PMU_SCU4 (IRQ_PBX_GIC_START + 36) -#define IRQ_PBX_PMU_SCU5 (IRQ_PBX_GIC_START + 37) -#define IRQ_PBX_PMU_SCU6 (IRQ_PBX_GIC_START + 38) -#define IRQ_PBX_PMU_SCU7 (IRQ_PBX_GIC_START + 39) - -#define IRQ_PBX_WATCHDOG1 (IRQ_PBX_GIC_START + 40) /* Watchdog1 timer */ -#define IRQ_PBX_TIMER4_5 (IRQ_PBX_GIC_START + 41) /* Timer 0/1 (default timer) */ -#define IRQ_PBX_TIMER6_7 (IRQ_PBX_GIC_START + 42) /* Timer 2/3 */ -/* ... */ -#define IRQ_PBX_PMU_CPU3 (IRQ_PBX_GIC_START + 44) /* CPU PMU Interrupts */ -#define IRQ_PBX_PMU_CPU2 (IRQ_PBX_GIC_START + 45) -#define IRQ_PBX_PMU_CPU1 (IRQ_PBX_GIC_START + 46) -#define IRQ_PBX_PMU_CPU0 (IRQ_PBX_GIC_START + 47) - -/* ... */ -#define IRQ_PBX_PCI0 (IRQ_PBX_GIC_START + 50) -#define IRQ_PBX_PCI1 (IRQ_PBX_GIC_START + 51) -#define IRQ_PBX_PCI2 (IRQ_PBX_GIC_START + 52) -#define IRQ_PBX_PCI3 (IRQ_PBX_GIC_START + 53) - -#define IRQ_PBX_SMC -1 -#define IRQ_PBX_SCTL -1 - -#define NR_GIC_PBX 1 - -/* - * Only define NR_IRQS if less than NR_IRQS_PBX - */ -#define NR_IRQS_PBX (IRQ_PBX_GIC_START + 96) - -#if defined(CONFIG_MACH_REALVIEW_PBX) - -#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PBX) -#undef NR_IRQS -#define NR_IRQS NR_IRQS_PBX -#endif - -#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PBX) -#undef MAX_GIC_NR -#define MAX_GIC_NR NR_GIC_PBX -#endif - -#endif /* CONFIG_MACH_REALVIEW_PBX */ - /* * Core tile identification (REALVIEW_SYS_PROCID) */ diff --git a/arch/arm/mach-realview/include/mach/irqs-eb.h b/arch/arm/mach-realview/include/mach/irqs-eb.h new file mode 100644 index 000000000000..204d5378f309 --- /dev/null +++ b/arch/arm/mach-realview/include/mach/irqs-eb.h @@ -0,0 +1,129 @@ +/* + * arch/arm/mach-realview/include/mach/irqs-eb.h + * + * Copyright (C) 2007 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_IRQS_EB_H +#define __MACH_IRQS_EB_H + +#define IRQ_EB_GIC_START 32 + +/* + * RealView EB interrupt sources + */ +#define IRQ_EB_WDOG (IRQ_EB_GIC_START + 0) /* Watchdog timer */ +#define IRQ_EB_SOFT (IRQ_EB_GIC_START + 1) /* Software interrupt */ +#define IRQ_EB_COMMRx (IRQ_EB_GIC_START + 2) /* Debug Comm Rx interrupt */ +#define IRQ_EB_COMMTx (IRQ_EB_GIC_START + 3) /* Debug Comm Tx interrupt */ +#define IRQ_EB_TIMER0_1 (IRQ_EB_GIC_START + 4) /* Timer 0 and 1 */ +#define IRQ_EB_TIMER2_3 (IRQ_EB_GIC_START + 5) /* Timer 2 and 3 */ +#define IRQ_EB_GPIO0 (IRQ_EB_GIC_START + 6) /* GPIO 0 */ +#define IRQ_EB_GPIO1 (IRQ_EB_GIC_START + 7) /* GPIO 1 */ +#define IRQ_EB_GPIO2 (IRQ_EB_GIC_START + 8) /* GPIO 2 */ + /* 9 reserved */ +#define IRQ_EB_RTC (IRQ_EB_GIC_START + 10) /* Real Time Clock */ +#define IRQ_EB_SSP (IRQ_EB_GIC_START + 11) /* Synchronous Serial Port */ +#define IRQ_EB_UART0 (IRQ_EB_GIC_START + 12) /* UART 0 on development chip */ +#define IRQ_EB_UART1 (IRQ_EB_GIC_START + 13) /* UART 1 on development chip */ +#define IRQ_EB_UART2 (IRQ_EB_GIC_START + 14) /* UART 2 on development chip */ +#define IRQ_EB_UART3 (IRQ_EB_GIC_START + 15) /* UART 3 on development chip */ +#define IRQ_EB_SCI (IRQ_EB_GIC_START + 16) /* Smart Card Interface */ +#define IRQ_EB_MMCI0A (IRQ_EB_GIC_START + 17) /* Multimedia Card 0A */ +#define IRQ_EB_MMCI0B (IRQ_EB_GIC_START + 18) /* Multimedia Card 0B */ +#define IRQ_EB_AACI (IRQ_EB_GIC_START + 19) /* Audio Codec */ +#define IRQ_EB_KMI0 (IRQ_EB_GIC_START + 20) /* Keyboard/Mouse port 0 */ +#define IRQ_EB_KMI1 (IRQ_EB_GIC_START + 21) /* Keyboard/Mouse port 1 */ +#define IRQ_EB_CHARLCD (IRQ_EB_GIC_START + 22) /* Character LCD */ +#define IRQ_EB_CLCD (IRQ_EB_GIC_START + 23) /* CLCD controller */ +#define IRQ_EB_DMA (IRQ_EB_GIC_START + 24) /* DMA controller */ +#define IRQ_EB_PWRFAIL (IRQ_EB_GIC_START + 25) /* Power failure */ +#define IRQ_EB_PISMO (IRQ_EB_GIC_START + 26) /* PISMO interface */ +#define IRQ_EB_DoC (IRQ_EB_GIC_START + 27) /* Disk on Chip memory controller */ +#define IRQ_EB_ETH (IRQ_EB_GIC_START + 28) /* Ethernet controller */ +#define IRQ_EB_USB (IRQ_EB_GIC_START + 29) /* USB controller */ +#define IRQ_EB_TSPEN (IRQ_EB_GIC_START + 30) /* Touchscreen pen */ +#define IRQ_EB_TSKPAD (IRQ_EB_GIC_START + 31) /* Touchscreen keypad */ + +/* + * RealView EB + ARM11MPCore interrupt sources (primary GIC on the core tile) + */ +#define IRQ_EB11MP_AACI (IRQ_EB_GIC_START + 0) +#define IRQ_EB11MP_TIMER0_1 (IRQ_EB_GIC_START + 1) +#define IRQ_EB11MP_TIMER2_3 (IRQ_EB_GIC_START + 2) +#define IRQ_EB11MP_USB (IRQ_EB_GIC_START + 3) +#define IRQ_EB11MP_UART0 (IRQ_EB_GIC_START + 4) +#define IRQ_EB11MP_UART1 (IRQ_EB_GIC_START + 5) +#define IRQ_EB11MP_RTC (IRQ_EB_GIC_START + 6) +#define IRQ_EB11MP_KMI0 (IRQ_EB_GIC_START + 7) +#define IRQ_EB11MP_KMI1 (IRQ_EB_GIC_START + 8) +#define IRQ_EB11MP_ETH (IRQ_EB_GIC_START + 9) +#define IRQ_EB11MP_EB_IRQ1 (IRQ_EB_GIC_START + 10) /* main GIC */ +#define IRQ_EB11MP_EB_IRQ2 (IRQ_EB_GIC_START + 11) /* tile GIC */ +#define IRQ_EB11MP_EB_FIQ1 (IRQ_EB_GIC_START + 12) /* main GIC */ +#define IRQ_EB11MP_EB_FIQ2 (IRQ_EB_GIC_START + 13) /* tile GIC */ +#define IRQ_EB11MP_MMCI0A (IRQ_EB_GIC_START + 14) +#define IRQ_EB11MP_MMCI0B (IRQ_EB_GIC_START + 15) + +#define IRQ_EB11MP_PMU_CPU0 (IRQ_EB_GIC_START + 17) +#define IRQ_EB11MP_PMU_CPU1 (IRQ_EB_GIC_START + 18) +#define IRQ_EB11MP_PMU_CPU2 (IRQ_EB_GIC_START + 19) +#define IRQ_EB11MP_PMU_CPU3 (IRQ_EB_GIC_START + 20) +#define IRQ_EB11MP_PMU_SCU0 (IRQ_EB_GIC_START + 21) +#define IRQ_EB11MP_PMU_SCU1 (IRQ_EB_GIC_START + 22) +#define IRQ_EB11MP_PMU_SCU2 (IRQ_EB_GIC_START + 23) +#define IRQ_EB11MP_PMU_SCU3 (IRQ_EB_GIC_START + 24) +#define IRQ_EB11MP_PMU_SCU4 (IRQ_EB_GIC_START + 25) +#define IRQ_EB11MP_PMU_SCU5 (IRQ_EB_GIC_START + 26) +#define IRQ_EB11MP_PMU_SCU6 (IRQ_EB_GIC_START + 27) +#define IRQ_EB11MP_PMU_SCU7 (IRQ_EB_GIC_START + 28) + +#define IRQ_EB11MP_L220_EVENT (IRQ_EB_GIC_START + 29) +#define IRQ_EB11MP_L220_SLAVE (IRQ_EB_GIC_START + 30) +#define IRQ_EB11MP_L220_DECODE (IRQ_EB_GIC_START + 31) + +#define IRQ_EB11MP_UART2 -1 +#define IRQ_EB11MP_UART3 -1 +#define IRQ_EB11MP_CLCD -1 +#define IRQ_EB11MP_DMA -1 +#define IRQ_EB11MP_WDOG -1 +#define IRQ_EB11MP_GPIO0 -1 +#define IRQ_EB11MP_GPIO1 -1 +#define IRQ_EB11MP_GPIO2 -1 +#define IRQ_EB11MP_SCI -1 +#define IRQ_EB11MP_SSP -1 + +#define NR_GIC_EB11MP 2 + +/* + * Only define NR_IRQS if less than NR_IRQS_EB + */ +#define NR_IRQS_EB (IRQ_EB_GIC_START + 96) + +#if defined(CONFIG_MACH_REALVIEW_EB) \ + && (!defined(NR_IRQS) || (NR_IRQS < NR_IRQS_EB)) +#undef NR_IRQS +#define NR_IRQS NR_IRQS_EB +#endif + +#if defined(CONFIG_REALVIEW_EB_ARM11MP) || defined(CONFIG_REALVIEW_EB_A9MP) \ + && (!defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_EB11MP)) +#undef MAX_GIC_NR +#define MAX_GIC_NR NR_GIC_EB11MP +#endif + +#endif /* __MACH_IRQS_EB_H */ diff --git a/arch/arm/mach-realview/include/mach/irqs-pb1176.h b/arch/arm/mach-realview/include/mach/irqs-pb1176.h new file mode 100644 index 000000000000..2410d4f8ddd3 --- /dev/null +++ b/arch/arm/mach-realview/include/mach/irqs-pb1176.h @@ -0,0 +1,99 @@ +/* + * arch/arm/mach-realview/include/mach/irqs-pb1176.h + * + * Copyright (C) 2008 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_IRQS_PB1176_H +#define __MACH_IRQS_PB1176_H + +#define IRQ_DC1176_GIC_START 32 +#define IRQ_PB1176_GIC_START 64 + +/* + * ARM1176 DevChip interrupt sources (primary GIC) + */ +#define IRQ_DC1176_WATCHDOG (IRQ_DC1176_GIC_START + 0) /* Watchdog timer */ +#define IRQ_DC1176_SOFTINT (IRQ_DC1176_GIC_START + 1) /* Software interrupt */ +#define IRQ_DC1176_COMMRx (IRQ_DC1176_GIC_START + 2) /* Debug Comm Rx interrupt */ +#define IRQ_DC1176_COMMTx (IRQ_DC1176_GIC_START + 3) /* Debug Comm Tx interrupt */ +#define IRQ_DC1176_TIMER0 (IRQ_DC1176_GIC_START + 8) /* Timer 0 */ +#define IRQ_DC1176_TIMER1 (IRQ_DC1176_GIC_START + 9) /* Timer 1 */ +#define IRQ_DC1176_TIMER2 (IRQ_DC1176_GIC_START + 10) /* Timer 2 */ +#define IRQ_DC1176_APC (IRQ_DC1176_GIC_START + 11) +#define IRQ_DC1176_IEC (IRQ_DC1176_GIC_START + 12) +#define IRQ_DC1176_L2CC (IRQ_DC1176_GIC_START + 13) +#define IRQ_DC1176_RTC (IRQ_DC1176_GIC_START + 14) +#define IRQ_DC1176_CLCD (IRQ_DC1176_GIC_START + 15) /* CLCD controller */ +#define IRQ_DC1176_UART0 (IRQ_DC1176_GIC_START + 18) /* UART 0 on development chip */ +#define IRQ_DC1176_UART1 (IRQ_DC1176_GIC_START + 19) /* UART 1 on development chip */ +#define IRQ_DC1176_UART2 (IRQ_DC1176_GIC_START + 20) /* UART 2 on development chip */ +#define IRQ_DC1176_UART3 (IRQ_DC1176_GIC_START + 21) /* UART 3 on development chip */ + +#define IRQ_DC1176_PB_IRQ2 (IRQ_DC1176_GIC_START + 30) /* tile GIC */ +#define IRQ_DC1176_PB_IRQ1 (IRQ_DC1176_GIC_START + 31) /* main GIC */ + +/* + * RealView PB1176 interrupt sources (secondary GIC) + */ +#define IRQ_PB1176_MMCI0A (IRQ_PB1176_GIC_START + 1) /* Multimedia Card 0A */ +#define IRQ_PB1176_MMCI0B (IRQ_PB1176_GIC_START + 2) /* Multimedia Card 0A */ +#define IRQ_PB1176_KMI0 (IRQ_PB1176_GIC_START + 3) /* Keyboard/Mouse port 0 */ +#define IRQ_PB1176_KMI1 (IRQ_PB1176_GIC_START + 4) /* Keyboard/Mouse port 1 */ +#define IRQ_PB1176_SCI (IRQ_PB1176_GIC_START + 5) +#define IRQ_PB1176_UART4 (IRQ_PB1176_GIC_START + 6) /* UART 4 on baseboard */ +#define IRQ_PB1176_CHARLCD (IRQ_PB1176_GIC_START + 7) /* Character LCD */ +#define IRQ_PB1176_GPIO1 (IRQ_PB1176_GIC_START + 8) +#define IRQ_PB1176_GPIO2 (IRQ_PB1176_GIC_START + 9) +#define IRQ_PB1176_ETH (IRQ_PB1176_GIC_START + 10) /* Ethernet controller */ +#define IRQ_PB1176_USB (IRQ_PB1176_GIC_START + 11) /* USB controller */ + +#define IRQ_PB1176_PISMO (IRQ_PB1176_GIC_START + 16) + +#define IRQ_PB1176_AACI (IRQ_PB1176_GIC_START + 19) /* Audio Codec */ + +#define IRQ_PB1176_TIMER0_1 (IRQ_PB1176_GIC_START + 22) +#define IRQ_PB1176_TIMER2_3 (IRQ_PB1176_GIC_START + 23) +#define IRQ_PB1176_DMAC (IRQ_PB1176_GIC_START + 24) /* DMA controller */ +#define IRQ_PB1176_RTC (IRQ_PB1176_GIC_START + 25) /* Real Time Clock */ + +#define IRQ_PB1176_GPIO0 -1 +#define IRQ_PB1176_SSP -1 +#define IRQ_PB1176_SCTL -1 + +#define NR_GIC_PB1176 2 + +/* + * Only define NR_IRQS if less than NR_IRQS_PB1176 + */ +#define NR_IRQS_PB1176 (IRQ_DC1176_GIC_START + 96) + +#if defined(CONFIG_MACH_REALVIEW_PB1176) + +#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB1176) +#undef NR_IRQS +#define NR_IRQS NR_IRQS_PB1176 +#endif + +#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB1176) +#undef MAX_GIC_NR +#define MAX_GIC_NR NR_GIC_PB1176 +#endif + +#endif /* CONFIG_MACH_REALVIEW_PB1176 */ + +#endif /* __MACH_IRQS_PB1176_H */ diff --git a/arch/arm/mach-realview/include/mach/irqs-pb11mp.h b/arch/arm/mach-realview/include/mach/irqs-pb11mp.h new file mode 100644 index 000000000000..34e255add21e --- /dev/null +++ b/arch/arm/mach-realview/include/mach/irqs-pb11mp.h @@ -0,0 +1,122 @@ +/* + * arch/arm/mach-realview/include/mach/irqs-pb11mp.h + * + * Copyright (C) 2008 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_IRQS_PB11MP_H +#define __MACH_IRQS_PB11MP_H + +#define IRQ_TC11MP_GIC_START 32 +#define IRQ_PB11MP_GIC_START 64 + +/* + * ARM11MPCore test chip interrupt sources (primary GIC on the test chip) + */ +#define IRQ_TC11MP_AACI (IRQ_TC11MP_GIC_START + 0) +#define IRQ_TC11MP_TIMER0_1 (IRQ_TC11MP_GIC_START + 1) +#define IRQ_TC11MP_TIMER2_3 (IRQ_TC11MP_GIC_START + 2) +#define IRQ_TC11MP_USB (IRQ_TC11MP_GIC_START + 3) +#define IRQ_TC11MP_UART0 (IRQ_TC11MP_GIC_START + 4) +#define IRQ_TC11MP_UART1 (IRQ_TC11MP_GIC_START + 5) +#define IRQ_TC11MP_RTC (IRQ_TC11MP_GIC_START + 6) +#define IRQ_TC11MP_KMI0 (IRQ_TC11MP_GIC_START + 7) +#define IRQ_TC11MP_KMI1 (IRQ_TC11MP_GIC_START + 8) +#define IRQ_TC11MP_ETH (IRQ_TC11MP_GIC_START + 9) +#define IRQ_TC11MP_PB_IRQ1 (IRQ_TC11MP_GIC_START + 10) /* main GIC */ +#define IRQ_TC11MP_PB_IRQ2 (IRQ_TC11MP_GIC_START + 11) /* tile GIC */ +#define IRQ_TC11MP_PB_FIQ1 (IRQ_TC11MP_GIC_START + 12) /* main GIC */ +#define IRQ_TC11MP_PB_FIQ2 (IRQ_TC11MP_GIC_START + 13) /* tile GIC */ +#define IRQ_TC11MP_MMCI0A (IRQ_TC11MP_GIC_START + 14) +#define IRQ_TC11MP_MMCI0B (IRQ_TC11MP_GIC_START + 15) + +#define IRQ_TC11MP_PMU_CPU0 (IRQ_TC11MP_GIC_START + 17) +#define IRQ_TC11MP_PMU_CPU1 (IRQ_TC11MP_GIC_START + 18) +#define IRQ_TC11MP_PMU_CPU2 (IRQ_TC11MP_GIC_START + 19) +#define IRQ_TC11MP_PMU_CPU3 (IRQ_TC11MP_GIC_START + 20) +#define IRQ_TC11MP_PMU_SCU0 (IRQ_TC11MP_GIC_START + 21) +#define IRQ_TC11MP_PMU_SCU1 (IRQ_TC11MP_GIC_START + 22) +#define IRQ_TC11MP_PMU_SCU2 (IRQ_TC11MP_GIC_START + 23) +#define IRQ_TC11MP_PMU_SCU3 (IRQ_TC11MP_GIC_START + 24) +#define IRQ_TC11MP_PMU_SCU4 (IRQ_TC11MP_GIC_START + 25) +#define IRQ_TC11MP_PMU_SCU5 (IRQ_TC11MP_GIC_START + 26) +#define IRQ_TC11MP_PMU_SCU6 (IRQ_TC11MP_GIC_START + 27) +#define IRQ_TC11MP_PMU_SCU7 (IRQ_TC11MP_GIC_START + 28) + +#define IRQ_TC11MP_L220_EVENT (IRQ_TC11MP_GIC_START + 29) +#define IRQ_TC11MP_L220_SLAVE (IRQ_TC11MP_GIC_START + 30) +#define IRQ_TC11MP_L220_DECODE (IRQ_TC11MP_GIC_START + 31) + +/* + * RealView PB11MPCore GIC interrupt sources (secondary GIC on the board) + */ +#define IRQ_PB11MP_WATCHDOG (IRQ_PB11MP_GIC_START + 0) /* Watchdog timer */ +#define IRQ_PB11MP_SOFT (IRQ_PB11MP_GIC_START + 1) /* Software interrupt */ +#define IRQ_PB11MP_COMMRx (IRQ_PB11MP_GIC_START + 2) /* Debug Comm Rx interrupt */ +#define IRQ_PB11MP_COMMTx (IRQ_PB11MP_GIC_START + 3) /* Debug Comm Tx interrupt */ +#define IRQ_PB11MP_GPIO0 (IRQ_PB11MP_GIC_START + 6) /* GPIO 0 */ +#define IRQ_PB11MP_GPIO1 (IRQ_PB11MP_GIC_START + 7) /* GPIO 1 */ +#define IRQ_PB11MP_GPIO2 (IRQ_PB11MP_GIC_START + 8) /* GPIO 2 */ + /* 9 reserved */ +#define IRQ_PB11MP_RTC_GIC1 (IRQ_PB11MP_GIC_START + 10) /* Real Time Clock */ +#define IRQ_PB11MP_SSP (IRQ_PB11MP_GIC_START + 11) /* Synchronous Serial Port */ +#define IRQ_PB11MP_UART0_GIC1 (IRQ_PB11MP_GIC_START + 12) /* UART 0 on development chip */ +#define IRQ_PB11MP_UART1_GIC1 (IRQ_PB11MP_GIC_START + 13) /* UART 1 on development chip */ +#define IRQ_PB11MP_UART2 (IRQ_PB11MP_GIC_START + 14) /* UART 2 on development chip */ +#define IRQ_PB11MP_UART3 (IRQ_PB11MP_GIC_START + 15) /* UART 3 on development chip */ +#define IRQ_PB11MP_SCI (IRQ_PB11MP_GIC_START + 16) /* Smart Card Interface */ +#define IRQ_PB11MP_MMCI0A_GIC1 (IRQ_PB11MP_GIC_START + 17) /* Multimedia Card 0A */ +#define IRQ_PB11MP_MMCI0B_GIC1 (IRQ_PB11MP_GIC_START + 18) /* Multimedia Card 0B */ +#define IRQ_PB11MP_AACI_GIC1 (IRQ_PB11MP_GIC_START + 19) /* Audio Codec */ +#define IRQ_PB11MP_KMI0_GIC1 (IRQ_PB11MP_GIC_START + 20) /* Keyboard/Mouse port 0 */ +#define IRQ_PB11MP_KMI1_GIC1 (IRQ_PB11MP_GIC_START + 21) /* Keyboard/Mouse port 1 */ +#define IRQ_PB11MP_CHARLCD (IRQ_PB11MP_GIC_START + 22) /* Character LCD */ +#define IRQ_PB11MP_CLCD (IRQ_PB11MP_GIC_START + 23) /* CLCD controller */ +#define IRQ_PB11MP_DMAC (IRQ_PB11MP_GIC_START + 24) /* DMA controller */ +#define IRQ_PB11MP_PWRFAIL (IRQ_PB11MP_GIC_START + 25) /* Power failure */ +#define IRQ_PB11MP_PISMO (IRQ_PB11MP_GIC_START + 26) /* PISMO interface */ +#define IRQ_PB11MP_DoC (IRQ_PB11MP_GIC_START + 27) /* Disk on Chip memory controller */ +#define IRQ_PB11MP_ETH_GIC1 (IRQ_PB11MP_GIC_START + 28) /* Ethernet controller */ +#define IRQ_PB11MP_USB_GIC1 (IRQ_PB11MP_GIC_START + 29) /* USB controller */ +#define IRQ_PB11MP_TSPEN (IRQ_PB11MP_GIC_START + 30) /* Touchscreen pen */ +#define IRQ_PB11MP_TSKPAD (IRQ_PB11MP_GIC_START + 31) /* Touchscreen keypad */ + +#define IRQ_PB11MP_SMC -1 +#define IRQ_PB11MP_SCTL -1 + +#define NR_GIC_PB11MP 2 + +/* + * Only define NR_IRQS if less than NR_IRQS_PB11MP + */ +#define NR_IRQS_PB11MP (IRQ_TC11MP_GIC_START + 96) + +#if defined(CONFIG_MACH_REALVIEW_PB11MP) + +#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB11MP) +#undef NR_IRQS +#define NR_IRQS NR_IRQS_PB11MP +#endif + +#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB11MP) +#undef MAX_GIC_NR +#define MAX_GIC_NR NR_GIC_PB11MP +#endif + +#endif /* CONFIG_MACH_REALVIEW_PB11MP */ + +#endif /* __MACH_IRQS_PB11MP_H */ diff --git a/arch/arm/mach-realview/include/mach/irqs-pba8.h b/arch/arm/mach-realview/include/mach/irqs-pba8.h new file mode 100644 index 000000000000..86792a9f2ab6 --- /dev/null +++ b/arch/arm/mach-realview/include/mach/irqs-pba8.h @@ -0,0 +1,98 @@ +/* + * arch/arm/mach-realview/include/mach/irqs-pba8.h + * + * Copyright (C) 2008 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_IRQS_PBA8_H +#define __MACH_IRQS_PBA8_H + +#define IRQ_PBA8_GIC_START 32 + +/* L220 +#define IRQ_PBA8_L220_EVENT (IRQ_PBA8_GIC_START + 29) +#define IRQ_PBA8_L220_SLAVE (IRQ_PBA8_GIC_START + 30) +#define IRQ_PBA8_L220_DECODE (IRQ_PBA8_GIC_START + 31) +*/ + +/* + * PB-A8 on-board gic irq sources + */ +#define IRQ_PBA8_WATCHDOG (IRQ_PBA8_GIC_START + 0) /* Watchdog timer */ +#define IRQ_PBA8_SOFT (IRQ_PBA8_GIC_START + 1) /* Software interrupt */ +#define IRQ_PBA8_COMMRx (IRQ_PBA8_GIC_START + 2) /* Debug Comm Rx interrupt */ +#define IRQ_PBA8_COMMTx (IRQ_PBA8_GIC_START + 3) /* Debug Comm Tx interrupt */ +#define IRQ_PBA8_TIMER0_1 (IRQ_PBA8_GIC_START + 4) /* Timer 0/1 (default timer) */ +#define IRQ_PBA8_TIMER2_3 (IRQ_PBA8_GIC_START + 5) /* Timer 2/3 */ +#define IRQ_PBA8_GPIO0 (IRQ_PBA8_GIC_START + 6) /* GPIO 0 */ +#define IRQ_PBA8_GPIO1 (IRQ_PBA8_GIC_START + 7) /* GPIO 1 */ +#define IRQ_PBA8_GPIO2 (IRQ_PBA8_GIC_START + 8) /* GPIO 2 */ + /* 9 reserved */ +#define IRQ_PBA8_RTC (IRQ_PBA8_GIC_START + 10) /* Real Time Clock */ +#define IRQ_PBA8_SSP (IRQ_PBA8_GIC_START + 11) /* Synchronous Serial Port */ +#define IRQ_PBA8_UART0 (IRQ_PBA8_GIC_START + 12) /* UART 0 on development chip */ +#define IRQ_PBA8_UART1 (IRQ_PBA8_GIC_START + 13) /* UART 1 on development chip */ +#define IRQ_PBA8_UART2 (IRQ_PBA8_GIC_START + 14) /* UART 2 on development chip */ +#define IRQ_PBA8_UART3 (IRQ_PBA8_GIC_START + 15) /* UART 3 on development chip */ +#define IRQ_PBA8_SCI (IRQ_PBA8_GIC_START + 16) /* Smart Card Interface */ +#define IRQ_PBA8_MMCI0A (IRQ_PBA8_GIC_START + 17) /* Multimedia Card 0A */ +#define IRQ_PBA8_MMCI0B (IRQ_PBA8_GIC_START + 18) /* Multimedia Card 0B */ +#define IRQ_PBA8_AACI (IRQ_PBA8_GIC_START + 19) /* Audio Codec */ +#define IRQ_PBA8_KMI0 (IRQ_PBA8_GIC_START + 20) /* Keyboard/Mouse port 0 */ +#define IRQ_PBA8_KMI1 (IRQ_PBA8_GIC_START + 21) /* Keyboard/Mouse port 1 */ +#define IRQ_PBA8_CHARLCD (IRQ_PBA8_GIC_START + 22) /* Character LCD */ +#define IRQ_PBA8_CLCD (IRQ_PBA8_GIC_START + 23) /* CLCD controller */ +#define IRQ_PBA8_DMAC (IRQ_PBA8_GIC_START + 24) /* DMA controller */ +#define IRQ_PBA8_PWRFAIL (IRQ_PBA8_GIC_START + 25) /* Power failure */ +#define IRQ_PBA8_PISMO (IRQ_PBA8_GIC_START + 26) /* PISMO interface */ +#define IRQ_PBA8_DoC (IRQ_PBA8_GIC_START + 27) /* Disk on Chip memory controller */ +#define IRQ_PBA8_ETH (IRQ_PBA8_GIC_START + 28) /* Ethernet controller */ +#define IRQ_PBA8_USB (IRQ_PBA8_GIC_START + 29) /* USB controller */ +#define IRQ_PBA8_TSPEN (IRQ_PBA8_GIC_START + 30) /* Touchscreen pen */ +#define IRQ_PBA8_TSKPAD (IRQ_PBA8_GIC_START + 31) /* Touchscreen keypad */ + +/* ... */ +#define IRQ_PBA8_PCI0 (IRQ_PBA8_GIC_START + 50) +#define IRQ_PBA8_PCI1 (IRQ_PBA8_GIC_START + 51) +#define IRQ_PBA8_PCI2 (IRQ_PBA8_GIC_START + 52) +#define IRQ_PBA8_PCI3 (IRQ_PBA8_GIC_START + 53) + +#define IRQ_PBA8_SMC -1 +#define IRQ_PBA8_SCTL -1 + +#define NR_GIC_PBA8 1 + +/* + * Only define NR_IRQS if less than NR_IRQS_PBA8 + */ +#define NR_IRQS_PBA8 (IRQ_PBA8_GIC_START + 64) + +#if defined(CONFIG_MACH_REALVIEW_PBA8) + +#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PBA8) +#undef NR_IRQS +#define NR_IRQS NR_IRQS_PBA8 +#endif + +#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PBA8) +#undef MAX_GIC_NR +#define MAX_GIC_NR NR_GIC_PBA8 +#endif + +#endif /* CONFIG_MACH_REALVIEW_PBA8 */ + +#endif /* __MACH_IRQS_PBA8_H */ diff --git a/arch/arm/mach-realview/include/mach/irqs-pbx.h b/arch/arm/mach-realview/include/mach/irqs-pbx.h new file mode 100644 index 000000000000..deaad4302b17 --- /dev/null +++ b/arch/arm/mach-realview/include/mach/irqs-pbx.h @@ -0,0 +1,115 @@ +/* + * arch/arm/mach-realview/include/mach/irqs-pbx.h + * + * Copyright (C) 2009 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __MACH_IRQS_PBX_H +#define __MACH_IRQS_PBX_H + +#define IRQ_PBX_GIC_START 32 + +/* L220 +#define IRQ_PBX_L220_EVENT (IRQ_PBX_GIC_START + 29) +#define IRQ_PBX_L220_SLAVE (IRQ_PBX_GIC_START + 30) +#define IRQ_PBX_L220_DECODE (IRQ_PBX_GIC_START + 31) +*/ + +/* + * PBX on-board gic irq sources + */ +#define IRQ_PBX_WATCHDOG (IRQ_PBX_GIC_START + 0) /* Watchdog timer */ +#define IRQ_PBX_SOFT (IRQ_PBX_GIC_START + 1) /* Software interrupt */ +#define IRQ_PBX_COMMRx (IRQ_PBX_GIC_START + 2) /* Debug Comm Rx interrupt */ +#define IRQ_PBX_COMMTx (IRQ_PBX_GIC_START + 3) /* Debug Comm Tx interrupt */ +#define IRQ_PBX_TIMER0_1 (IRQ_PBX_GIC_START + 4) /* Timer 0/1 (default timer) */ +#define IRQ_PBX_TIMER2_3 (IRQ_PBX_GIC_START + 5) /* Timer 2/3 */ +#define IRQ_PBX_GPIO0 (IRQ_PBX_GIC_START + 6) /* GPIO 0 */ +#define IRQ_PBX_GPIO1 (IRQ_PBX_GIC_START + 7) /* GPIO 1 */ +#define IRQ_PBX_GPIO2 (IRQ_PBX_GIC_START + 8) /* GPIO 2 */ + /* 9 reserved */ +#define IRQ_PBX_RTC (IRQ_PBX_GIC_START + 10) /* Real Time Clock */ +#define IRQ_PBX_SSP (IRQ_PBX_GIC_START + 11) /* Synchronous Serial Port */ +#define IRQ_PBX_UART0 (IRQ_PBX_GIC_START + 12) /* UART 0 on development chip */ +#define IRQ_PBX_UART1 (IRQ_PBX_GIC_START + 13) /* UART 1 on development chip */ +#define IRQ_PBX_UART2 (IRQ_PBX_GIC_START + 14) /* UART 2 on development chip */ +#define IRQ_PBX_UART3 (IRQ_PBX_GIC_START + 15) /* UART 3 on development chip */ +#define IRQ_PBX_SCI (IRQ_PBX_GIC_START + 16) /* Smart Card Interface */ +#define IRQ_PBX_MMCI0A (IRQ_PBX_GIC_START + 17) /* Multimedia Card 0A */ +#define IRQ_PBX_MMCI0B (IRQ_PBX_GIC_START + 18) /* Multimedia Card 0B */ +#define IRQ_PBX_AACI (IRQ_PBX_GIC_START + 19) /* Audio Codec */ +#define IRQ_PBX_KMI0 (IRQ_PBX_GIC_START + 20) /* Keyboard/Mouse port 0 */ +#define IRQ_PBX_KMI1 (IRQ_PBX_GIC_START + 21) /* Keyboard/Mouse port 1 */ +#define IRQ_PBX_CHARLCD (IRQ_PBX_GIC_START + 22) /* Character LCD */ +#define IRQ_PBX_CLCD (IRQ_PBX_GIC_START + 23) /* CLCD controller */ +#define IRQ_PBX_DMAC (IRQ_PBX_GIC_START + 24) /* DMA controller */ +#define IRQ_PBX_PWRFAIL (IRQ_PBX_GIC_START + 25) /* Power failure */ +#define IRQ_PBX_PISMO (IRQ_PBX_GIC_START + 26) /* PISMO interface */ +#define IRQ_PBX_DoC (IRQ_PBX_GIC_START + 27) /* Disk on Chip memory controller */ +#define IRQ_PBX_ETH (IRQ_PBX_GIC_START + 28) /* Ethernet controller */ +#define IRQ_PBX_USB (IRQ_PBX_GIC_START + 29) /* USB controller */ +#define IRQ_PBX_TSPEN (IRQ_PBX_GIC_START + 30) /* Touchscreen pen */ +#define IRQ_PBX_TSKPAD (IRQ_PBX_GIC_START + 31) /* Touchscreen keypad */ + +#define IRQ_PBX_PMU_SCU0 (IRQ_PBX_GIC_START + 32) /* SCU PMU Interrupts (11mp) */ +#define IRQ_PBX_PMU_SCU1 (IRQ_PBX_GIC_START + 33) +#define IRQ_PBX_PMU_SCU2 (IRQ_PBX_GIC_START + 34) +#define IRQ_PBX_PMU_SCU3 (IRQ_PBX_GIC_START + 35) +#define IRQ_PBX_PMU_SCU4 (IRQ_PBX_GIC_START + 36) +#define IRQ_PBX_PMU_SCU5 (IRQ_PBX_GIC_START + 37) +#define IRQ_PBX_PMU_SCU6 (IRQ_PBX_GIC_START + 38) +#define IRQ_PBX_PMU_SCU7 (IRQ_PBX_GIC_START + 39) + +#define IRQ_PBX_WATCHDOG1 (IRQ_PBX_GIC_START + 40) /* Watchdog1 timer */ +#define IRQ_PBX_TIMER4_5 (IRQ_PBX_GIC_START + 41) /* Timer 0/1 (default timer) */ +#define IRQ_PBX_TIMER6_7 (IRQ_PBX_GIC_START + 42) /* Timer 2/3 */ +/* ... */ +#define IRQ_PBX_PMU_CPU3 (IRQ_PBX_GIC_START + 44) /* CPU PMU Interrupts */ +#define IRQ_PBX_PMU_CPU2 (IRQ_PBX_GIC_START + 45) +#define IRQ_PBX_PMU_CPU1 (IRQ_PBX_GIC_START + 46) +#define IRQ_PBX_PMU_CPU0 (IRQ_PBX_GIC_START + 47) + +/* ... */ +#define IRQ_PBX_PCI0 (IRQ_PBX_GIC_START + 50) +#define IRQ_PBX_PCI1 (IRQ_PBX_GIC_START + 51) +#define IRQ_PBX_PCI2 (IRQ_PBX_GIC_START + 52) +#define IRQ_PBX_PCI3 (IRQ_PBX_GIC_START + 53) + +#define IRQ_PBX_SMC -1 +#define IRQ_PBX_SCTL -1 + +#define NR_GIC_PBX 1 + +/* + * Only define NR_IRQS if less than NR_IRQS_PBX + */ +#define NR_IRQS_PBX (IRQ_PBX_GIC_START + 96) + +#if defined(CONFIG_MACH_REALVIEW_PBX) + +#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PBX) +#undef NR_IRQS +#define NR_IRQS NR_IRQS_PBX +#endif + +#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PBX) +#undef MAX_GIC_NR +#define MAX_GIC_NR NR_GIC_PBX +#endif + +#endif /* CONFIG_MACH_REALVIEW_PBX */ + +#endif /* __MACH_IRQS_PBX_H */ diff --git a/arch/arm/mach-realview/include/mach/irqs.h b/arch/arm/mach-realview/include/mach/irqs.h index e9e38264671e..78854f2fa323 100644 --- a/arch/arm/mach-realview/include/mach/irqs.h +++ b/arch/arm/mach-realview/include/mach/irqs.h @@ -22,11 +22,11 @@ #ifndef __ASM_ARCH_IRQS_H #define __ASM_ARCH_IRQS_H -#include -#include -#include -#include -#include +#include +#include +#include +#include +#include #define IRQ_LOCALTIMER 29 #define IRQ_LOCALWDOG 30 diff --git a/arch/arm/oprofile/op_model_mpcore.c b/arch/arm/oprofile/op_model_mpcore.c index 853d42bb8682..4ce0f9801e2e 100644 --- a/arch/arm/oprofile/op_model_mpcore.c +++ b/arch/arm/oprofile/op_model_mpcore.c @@ -41,6 +41,7 @@ #include #include #include +#include #include #include "op_counter.h" -- cgit v1.2.2 From 26584853a44c58f3d6ac7360d697a2ddcd1a3efa Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Sat, 30 May 2009 14:00:18 +0100 Subject: Add core support for ARMv6/v7 big-endian Starting with ARMv6, the CPUs support the BE-8 variant of big-endian (byte-invariant). This patch adds the core support: - setting of the BE-8 mode via the CPSR.E register for both kernel and user threads - big-endian page table walking - REV used to rotate instructions read from memory during fault processing as they are still little-endian format - Kconfig and Makefile support for BE-8. The --be8 option must be passed to the final linking stage to convert the instructions to little-endian Signed-off-by: Catalin Marinas --- arch/arm/Makefile | 3 +++ arch/arm/boot/compressed/Makefile | 5 ++++- arch/arm/boot/compressed/head.S | 6 ++++++ arch/arm/include/asm/processor.h | 1 + arch/arm/include/asm/ptrace.h | 10 ++++++++++ arch/arm/kernel/entry-armv.S | 3 +++ arch/arm/kernel/entry-common.S | 3 +++ arch/arm/kernel/process.c | 2 +- arch/arm/mm/Kconfig | 14 ++++++++++++++ arch/arm/mm/abort-ev6.S | 3 +++ arch/arm/mm/proc-v6.S | 3 +++ arch/arm/mm/proc-v7.S | 3 +++ 12 files changed, 54 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Makefile b/arch/arm/Makefile index e84729bf13d4..1167a4e8c7a8 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -11,6 +11,9 @@ # Copyright (C) 1995-2001 by Russell King LDFLAGS_vmlinux :=-p --no-undefined -X +ifeq ($(CONFIG_CPU_ENDIAN_BE8),y) +LDFLAGS_vmlinux += --be8 +endif CPPFLAGS_vmlinux.lds = -DTEXT_OFFSET=$(TEXT_OFFSET) OBJCOPYFLAGS :=-O binary -R .note -R .note.gnu.build-id -R .comment -S GZFLAGS :=-9 diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index fbe5eef1f6c9..ce39dc540085 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -40,7 +40,7 @@ ifeq ($(CONFIG_PXA_SHARPSL),y) OBJS += head-sharpsl.o endif -ifeq ($(CONFIG_CPU_BIG_ENDIAN),y) +ifeq ($(CONFIG_CPU_ENDIAN_BE32),y) ifeq ($(CONFIG_CPU_CP15),y) OBJS += big-endian.o else @@ -78,6 +78,9 @@ EXTRA_AFLAGS := -Wa,-march=all # linker symbols. We only define initrd_phys and params_phys if the # machine class defined the corresponding makefile variable. LDFLAGS_vmlinux := --defsym zreladdr=$(ZRELADDR) +ifeq ($(CONFIG_CPU_ENDIAN_BE8),y) +LDFLAGS_vmlinux += --be8 +endif ifneq ($(INITRD_PHYS),) LDFLAGS_vmlinux += --defsym initrd_phys=$(INITRD_PHYS) endif diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index b371fba1b954..01d49be3b2ca 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -438,6 +438,9 @@ __armv4_mmu_cache_on: mrc p15, 0, r0, c1, c0, 0 @ read control reg orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement orr r0, r0, #0x0030 +#ifdef CONFIG_CPU_ENDIAN_BE8 + orr r0, r0, #1 << 25 @ big-endian page tables +#endif bl __common_mmu_cache_on mov r0, #0 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs @@ -455,6 +458,9 @@ __armv7_mmu_cache_on: mrc p15, 0, r0, c1, c0, 0 @ read control reg orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement orr r0, r0, #0x003c @ write buffer +#ifdef CONFIG_CPU_ENDIAN_BE8 + orr r0, r0, #1 << 25 @ big-endian page tables +#endif orrne r0, r0, #1 @ MMU enabled movne r1, #-1 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h index 1845892260e7..6a89567ffc5b 100644 --- a/arch/arm/include/asm/processor.h +++ b/arch/arm/include/asm/processor.h @@ -71,6 +71,7 @@ struct thread_struct { regs->ARM_cpsr = USR26_MODE; \ if (elf_hwcap & HWCAP_THUMB && pc & 1) \ regs->ARM_cpsr |= PSR_T_BIT; \ + regs->ARM_cpsr |= PSR_ENDSTATE; \ regs->ARM_pc = pc & ~1; /* pc */ \ regs->ARM_sp = sp; /* sp */ \ regs->ARM_r2 = stack[2]; /* r2 (envp) */ \ diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h index 4a4290f7b4a2..67b833c9b6b9 100644 --- a/arch/arm/include/asm/ptrace.h +++ b/arch/arm/include/asm/ptrace.h @@ -50,6 +50,7 @@ #define PSR_F_BIT 0x00000040 #define PSR_I_BIT 0x00000080 #define PSR_A_BIT 0x00000100 +#define PSR_E_BIT 0x00000200 #define PSR_J_BIT 0x01000000 #define PSR_Q_BIT 0x08000000 #define PSR_V_BIT 0x10000000 @@ -72,6 +73,15 @@ #define PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */ #define PSR_ENDIAN_MASK 0x00000200 /* Endianness state mask */ +/* + * Default endianness state + */ +#ifdef CONFIG_CPU_ENDIAN_BE8 +#define PSR_ENDSTATE PSR_E_BIT +#else +#define PSR_ENDSTATE 0 +#endif + #ifndef __ASSEMBLY__ /* diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index d662a2f1fd85..9d7ce4377c5e 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -482,6 +482,9 @@ __und_usr: subeq r4, r2, #4 @ ARM instr at LR - 4 subne r4, r2, #2 @ Thumb instr at LR - 2 1: ldreqt r0, [r4] +#ifdef CONFIG_CPU_ENDIAN_BE8 + reveq r0, r0 @ little endian instruction +#endif beq call_fpe @ Thumb instruction #if __LINUX_ARM_ARCH__ >= 7 diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index b55cb0331809..366e5097a41a 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -210,6 +210,9 @@ ENTRY(vector_swi) A710( teq ip, #0x0f000000 ) A710( bne .Larm710bug ) #endif +#ifdef CONFIG_CPU_ENDIAN_BE8 + rev r10, r10 @ little endian instruction +#endif #elif defined(CONFIG_AEABI) diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index c3265a2e7cd4..1585423699ee 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -365,7 +365,7 @@ pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags) regs.ARM_r2 = (unsigned long)fn; regs.ARM_r3 = (unsigned long)do_exit; regs.ARM_pc = (unsigned long)kernel_thread_helper; - regs.ARM_cpsr = SVC_MODE; + regs.ARM_cpsr = SVC_MODE | PSR_ENDSTATE; return do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, ®s, 0, NULL, NULL); } diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 76bbcde049b0..a25f34bd99da 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -639,6 +639,20 @@ config CPU_BIG_ENDIAN port must properly enable any big-endian related features of your chipset/board/processor. +config CPU_ENDIAN_BE8 + bool + depends on CPU_BIG_ENDIAN + default CPU_V6 || CPU_V7 + help + Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors. + +config CPU_ENDIAN_BE32 + bool + depends on CPU_BIG_ENDIAN + default !CPU_ENDIAN_BE8 + help + Support for the BE-32 (big-endian) mode on pre-ARMv6 processors. + config CPU_HIGH_VECTOR depends on !MMU && CPU_CP15 && !CPU_ARM740T bool "Select the High exception vector" diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S index 6f7e70907e44..f332df7f0d37 100644 --- a/arch/arm/mm/abort-ev6.S +++ b/arch/arm/mm/abort-ev6.S @@ -37,6 +37,9 @@ ENTRY(v6_early_abort) movne pc, lr do_thumb_abort ldreq r3, [r2] @ read aborted ARM instruction +#ifdef CONFIG_CPU_ENDIAN_BE8 + reveq r3, r3 +#endif do_ldrd_abort tst r3, #1 << 20 @ L = 0 -> write orreq r1, r1, #1 << 11 @ yes. diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 087e239704df..524ddae92595 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -170,6 +170,9 @@ __v6_setup: #endif /* CONFIG_MMU */ adr r5, v6_crval ldmia r5, {r5, r6} +#ifdef CONFIG_CPU_ENDIAN_BE8 + orr r6, r6, #1 << 25 @ big-endian page tables +#endif mrc p15, 0, r0, c1, c0, 0 @ read control register bic r0, r0, r5 @ clear bits them orr r0, r0, r6 @ set them diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 0a8ffd3c03fd..4f8486475a79 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -253,6 +253,9 @@ __v7_setup: mcr p15, 0, r6, c10, c2, 1 @ write NMRR adr r5, v7_crval ldmia r5, {r5, r6} +#ifdef CONFIG_CPU_ENDIAN_BE8 + orr r6, r6, #1 << 25 @ big-endian page tables +#endif mrc p15, 0, r0, c1, c0, 0 @ read control register bic r0, r0, r5 @ clear bits them orr r0, r0, r6 @ set them -- cgit v1.2.2 From 85d6943af50537d3aec58b967ffbd3fec88453e9 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Sat, 30 May 2009 14:00:18 +0100 Subject: Fix the VFP handling on the Feroceon CPU This CPU generates synchronous VFP exceptions in a non-standard way - the FPEXC.EX bit set but without the FPSCR.IXE bit being set like in the VFP subarchitecture 1 or just the FPEXC.DEX bit like in VFP subarchitecture 2. The main problem is that the faulty instruction (which needs to be emulated in software) will be restarted several times (normally until a context switch disables the VFP). This patch ensures that the VFP exception is treated as synchronous. Signed-off-by: Catalin Marinas Cc: Nicolas Pitre --- arch/arm/vfp/vfphw.S | 4 ++++ arch/arm/vfp/vfpmodule.c | 2 ++ 2 files changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S index 83c4e384b16d..1aeae38725dd 100644 --- a/arch/arm/vfp/vfphw.S +++ b/arch/arm/vfp/vfphw.S @@ -100,6 +100,7 @@ ENTRY(vfp_support_entry) beq no_old_VFP_process VFPFSTMIA r4, r5 @ save the working registers VFPFMRX r5, FPSCR @ current status +#ifndef CONFIG_CPU_FEROCEON tst r1, #FPEXC_EX @ is there additional state to save? beq 1f VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set) @@ -107,6 +108,7 @@ ENTRY(vfp_support_entry) beq 1f VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present) 1: +#endif stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2 @ and point r4 at the word at the @ start of the register dump @@ -119,6 +121,7 @@ no_old_VFP_process: VFPFLDMIA r10, r5 @ reload the working registers while @ FPEXC is in a safe state ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2 +#ifndef CONFIG_CPU_FEROCEON tst r1, #FPEXC_EX @ is there additional state to restore? beq 1f VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set) @@ -126,6 +129,7 @@ no_old_VFP_process: beq 1f VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present) 1: +#endif VFPFMXR FPSCR, r5 @ restore status check_for_exception: diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index 01599c4ef726..2d7423af1197 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -253,12 +253,14 @@ void VFP_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs) } if (fpexc & FPEXC_EX) { +#ifndef CONFIG_CPU_FEROCEON /* * Asynchronous exception. The instruction is read from FPINST * and the interrupted instruction has to be restarted. */ trigger = fmrx(FPINST); regs->ARM_pc -= 4; +#endif } else if (!(fpexc & FPEXC_DEX)) { /* * Illegal combination of bits. It can be caused by an -- cgit v1.2.2