From 1ec42c0c97186fadc48810ccaf2dc573cd957ea1 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 26 Apr 2005 15:18:26 +0100 Subject: [PATCH] ARM: Remove argument for disable_irq/enable_irq Since we do not require a register for these operations, we can remove this unnecessary argument. Signed-off-by: Russell King --- arch/arm/kernel/entry-armv.S | 12 ++++++------ arch/arm/kernel/entry-common.S | 8 ++++---- arch/arm/kernel/entry-header.S | 16 ++++++---------- 3 files changed, 16 insertions(+), 20 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 37723bfb96a6..fc1428905472 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -118,7 +118,7 @@ __dabt_svc: @ @ IRQs off again before pulling preserved data off the stack @ - disable_irq r0 + disable_irq @ @ restore SPSR and restart the instruction @@ -198,7 +198,7 @@ __und_svc: @ @ IRQs off again before pulling preserved data off the stack @ -1: disable_irq r0 +1: disable_irq @ @ restore SPSR and restart the instruction @@ -232,7 +232,7 @@ __pabt_svc: @ @ IRQs off again before pulling preserved data off the stack @ - disable_irq r0 + disable_irq @ @ restore SPSR and restart the instruction @@ -316,7 +316,7 @@ __dabt_usr: @ @ IRQs on, then call the main handler @ - enable_irq r2 + enable_irq mov r2, sp adr lr, ret_from_exception b do_DataAbort @@ -418,7 +418,7 @@ call_fpe: movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) bcs iwmmxt_task_enable #endif - enable_irq r7 + enable_irq add pc, pc, r8, lsr #6 mov r0, r0 @@ -472,7 +472,7 @@ fpundefinstr: __pabt_usr: usr_entry abt - enable_irq r0 @ Enable interrupts + enable_irq @ Enable interrupts mov r0, r2 @ address (pc) mov r1, sp @ regs bl do_PrefetchAbort @ call abort handler diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 53a7e0dea44d..0cd9f7bcaad7 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -30,7 +30,7 @@ * stack. */ ret_fast_syscall: - disable_irq r1 @ disable interrupts + disable_irq @ disable interrupts ldr r1, [tsk, #TI_FLAGS] tst r1, #_TIF_WORK_MASK bne fast_work_pending @@ -49,7 +49,7 @@ work_pending: mov r0, sp @ 'regs' mov r2, why @ 'syscall' bl do_notify_resume - disable_irq r1 @ disable interrupts + disable_irq @ disable interrupts b no_work_pending work_resched: @@ -59,7 +59,7 @@ work_resched: */ ENTRY(ret_to_user) ret_slow_syscall: - disable_irq r1 @ disable interrupts + disable_irq @ disable interrupts ldr r1, [tsk, #TI_FLAGS] tst r1, #_TIF_WORK_MASK bne work_pending @@ -126,7 +126,7 @@ ENTRY(vector_swi) ldr ip, [ip] mcr p15, 0, ip, c1, c0 @ update control register #endif - enable_irq ip + enable_irq str r4, [sp, #-S_OFF]! @ push fifth arg diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S index 4039d8c120b5..109f4f10d314 100644 --- a/arch/arm/kernel/entry-header.S +++ b/arch/arm/kernel/entry-header.S @@ -63,25 +63,21 @@ #define S_R0 0 #define S_OFF 8 - .macro set_cpsr_c, reg, mode - msr cpsr_c, \mode - .endm - #if __LINUX_ARM_ARCH__ >= 6 - .macro disable_irq, temp + .macro disable_irq cpsid i .endm - .macro enable_irq, temp + .macro enable_irq cpsie i .endm #else - .macro disable_irq, temp - set_cpsr_c \temp, #PSR_I_BIT | MODE_SVC + .macro disable_irq + msr cpsr_c, #PSR_I_BIT | SVC_MODE .endm - .macro enable_irq, temp - set_cpsr_c \temp, #MODE_SVC + .macro enable_irq + msr cpsr_c, #SVC_MODE .endm #endif -- cgit v1.2.2