From a2c195fdde20772a90ee98ce3523dcfbda49eee6 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 3 Aug 2009 17:26:50 +0100 Subject: ARM: S3C24XX: Add SPI bus 1 on GPD8 through GPD10 Add configuration callback for SPI bus 1 on GPD[8..10] and ensure the correct GPIO configuration register definitions in regs-gpio.h Signed-off-by: Ben Dooks Signed-off-by: Ben Dooks --- arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c | 38 ++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c (limited to 'arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c') diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c new file mode 100644 index 000000000000..89fcf5308cf6 --- /dev/null +++ b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c @@ -0,0 +1,38 @@ +/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpd8_9_10.c + * + * Copyright (c) 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * S3C24XX SPI - gpio configuration for bus 1 on gpd8,9,10 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. +*/ + +#include +#include + +#include +#include + +void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi, + int enable) +{ + + printk(KERN_INFO "%s(%d)\n", __func__, enable); + if (enable) { + s3c2410_gpio_cfgpin(S3C2410_GPD(10), S3C2440_GPD10_SPICLK1); + s3c2410_gpio_cfgpin(S3C2410_GPD(9), S3C2440_GPD9_SPIMOSI1); + s3c2410_gpio_cfgpin(S3C2410_GPD(8), S3C2440_GPD8_SPIMISO1); + s3c2410_gpio_pullup(S3C2410_GPD(10), 0); + s3c2410_gpio_pullup(S3C2410_GPD(9), 0); + } else { + s3c2410_gpio_cfgpin(S3C2410_GPD(8), S3C2410_GPIO_INPUT); + s3c2410_gpio_cfgpin(S3C2410_GPD(9), S3C2410_GPIO_INPUT); + s3c2410_gpio_pullup(S3C2410_GPD(10), 1); + s3c2410_gpio_pullup(S3C2410_GPD(9), 1); + s3c2410_gpio_pullup(S3C2410_GPD(8), 1); + } +} -- cgit v1.2.2