From 838a2ae80a6ab52139fb1bf0a93ea8c5eff94488 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sat, 12 Jan 2013 11:50:05 +0000 Subject: ARM: use clockevents_config_and_register() where possible The clockevent core is able to figure out the best mult and shift, calculate min_delta_ns and max_delta_ns, with the necessary info passed into clockevents_config_and_register(). Use this combined configure and register function where possible to make the codes less error prone and gain some positive diff stat. Signed-off-by: Shawn Guo Cc: Nicolas Ferre Reviewed-by: Anton Vorontsov Acked-by: Kukjin Kim Cc: Russell King Cc: Sascha Hauer Cc: Jason Cooper Tested-by: Roland Stigge Acked-by: Eric Miao Cc: Haojian Zhuang Cc: David Brown Tested-by: Tony Lindgren Acked-by: Barry Song Tested-by: Stephen Warren Acked-by: Tony Prisk Cc: Lennert Buytenhek Cc: Wan ZongShun Acked-by: Viresh Kumar Acked-by: Arnd Bergmann Acked-by: Jason Cooper Reviewed-by: Thomas Gleixner Signed-off-by: Olof Johansson --- arch/arm/plat-orion/time.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'arch/arm/plat-orion') diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c index 0f4fa863dd55..5d5ac0f05422 100644 --- a/arch/arm/plat-orion/time.c +++ b/arch/arm/plat-orion/time.c @@ -156,7 +156,6 @@ orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) static struct clock_event_device orion_clkevt = { .name = "orion_tick", .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, - .shift = 32, .rating = 300, .set_next_event = orion_clkevt_next_event, .set_mode = orion_clkevt_mode, @@ -221,9 +220,6 @@ orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask, * Setup clockevent timer (interrupt-driven). */ setup_irq(irq, &orion_timer_irq); - orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift); - orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt); - orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt); orion_clkevt.cpumask = cpumask_of(0); - clockevents_register_device(&orion_clkevt); + clockevents_config_and_register(&orion_clkevt, tclk, 1, 0xfffffffe); } -- cgit v1.2.2 From 830f8b9105b2d88cd2b115994e14bfe992f9a000 Mon Sep 17 00:00:00 2001 From: Gerlando Falauto Date: Wed, 23 Jan 2013 14:50:59 +0100 Subject: arm: plat-orion: fix printing of "MPP config unavailable on this hardware" refactored printing of the kernel warning: "orion_mpp_conf: requested MPP%u config unavailable on this hardware\n" which is not to be printed in case of variant_mask = 0 (unknown variant). This check should be performed using a logical AND (&&) as opposed to a bitwise AND (&). Otherwise, test would fail (and message would not be printed) if variant_mask != 1 Signed-off-by: Gerlando Falauto Cc: Andrew Lunn Cc: Olof Johansson Cc: Nicolas Pitre Cc: Holger Brunck Acked-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/plat-orion/mpp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/plat-orion') diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c index e686fe76a96b..7310bcfb299f 100644 --- a/arch/arm/plat-orion/mpp.c +++ b/arch/arm/plat-orion/mpp.c @@ -49,7 +49,7 @@ void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask, "number (%u)\n", num); continue; } - if (variant_mask & !(*mpp_list & variant_mask)) { + if (variant_mask && !(*mpp_list & variant_mask)) { printk(KERN_WARNING "orion_mpp_conf: requested MPP%u config " "unavailable on this hardware\n", num); -- cgit v1.2.2 From 217bef3d37a9180bebd1953dffb6f9a3c77c557f Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Wed, 6 Mar 2013 11:23:34 +0100 Subject: arm: plat-orion: fix address decoding when > 4GB is used During the system initialization, the orion_setup_cpu_mbus_target() function reads the SDRAM address decoding registers to find out how many chip-selects of SDRAM have been enabled, and builds a small array with one entry per chip-select. This array is then used by device drivers (XOR, Ethernet, etc.) to configure their own address decoding windows to the SDRAM. However, devices can only access the first 32 bits of the physical memory. Even though LPAE is not supported for now, some Marvell boards are now showing up with 8 GB of RAM, configured using two SDRAM address decoding windows: the first covering the first 4 GB, the second covering the last 4 GB. The array built by orion_setup_cpu_mbus_target() has therefore two entries, and device drivers try to set up two address decoding windows to the SDRAM. However, in the device registers for the address decoding, the base address is only 32 bits, so those two windows overlap each other, and the devices do not work at all. This patch makes sure that the array built by orion_setup_cpu_mbus_target() only contains the SDRAM decoding windows that correspond to the first 4 GB of the memory. To do that, it ignores the SDRAM decoding windows for which the 4 low-order bits are not zero (the 4 low-order bits of the base register are used to store bits 32:35 of the base address, so they actually indicate whether the base address is above 4 GB). This patch allows the newly introduced armada-xp-gp board to properly operate when it is mounted with more than 4 GB of RAM. Without that, all devices doing DMA (for example XOR and Ethernet) do not work at all. Signed-off-by: Thomas Petazzoni Tested-by: Ezequiel Garcia Signed-off-by: Jason Cooper --- arch/arm/plat-orion/addr-map.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'arch/arm/plat-orion') diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c index febe3862873c..807ac8e5cbc0 100644 --- a/arch/arm/plat-orion/addr-map.c +++ b/arch/arm/plat-orion/addr-map.c @@ -157,9 +157,12 @@ void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i)); /* - * Chip select enabled? + * We only take care of entries for which the chip + * select is enabled, and that don't have high base + * address bits set (devices can only access the first + * 32 bits of the memory). */ - if (size & 1) { + if ((size & 1) && !(base & 0xF)) { struct mbus_dram_window *w; w = &orion_mbus_dram_info.cs[cs++]; -- cgit v1.2.2