From 2c20b9f19add2248dc867f1f78dcef1eb0944543 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 10 Nov 2010 21:27:55 +0100 Subject: ARM: mx25: dynamically allocate mxc-ehci devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the reference manual of the i.MX25 the host controller uses an offset of 0x200 not 0x400 as was specified in the resources for mxc_usbh2. Needs-Testing: yes Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/ehci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/plat-mxc/ehci.c') diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index 9915607683de..f699235fdf5d 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -71,7 +71,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) unsigned int v; #if defined(CONFIG_ARCH_MX25) if (cpu_is_mx25()) { - v = readl(MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR + + v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); switch (port) { @@ -108,7 +108,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) return -EINVAL; } - writel(v, MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR + + writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); return 0; } -- cgit v1.2.2 From 972cc48207450ce6aeed416ac176fe4d0482a4a3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 11 Nov 2010 18:35:01 +0100 Subject: ARM: imx: use SOC_IMX25 instead of ARCH_MX25 for multi-SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some usages of ARCH_MX25 are assuming that if it is defined the other SoCs are undefined. Use SOC_IMX25 for the save places. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/ehci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/plat-mxc/ehci.c') diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index f699235fdf5d..4bac3d5545d3 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -69,7 +69,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) { unsigned int v; -#if defined(CONFIG_ARCH_MX25) +#if defined(CONFIG_SOC_IMX25) if (cpu_is_mx25()) { v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); @@ -112,7 +112,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) USBCTRL_OTGBASE_OFFSET)); return 0; } -#endif /* CONFIG_ARCH_MX25 */ +#endif /* if defined(CONFIG_SOC_IMX25) */ #if defined(CONFIG_ARCH_MX3) if (cpu_is_mx31()) { v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + -- cgit v1.2.2 From 29bb6afcb077bd153c7738e73840dde808132fb5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20B=C3=A9nard?= Date: Sat, 27 Nov 2010 09:15:38 +0100 Subject: plat-mxc/ehci.c: fix compile breakage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commits 2eb42d5c287f5e883a4b3ebe668ba880caa351e5 and 9e1dde33876ba83ad586c336647fff133d0f5472 renamed some defines but didn't fix all the places where these defines are used leading to a compile failure for USB on i.MX31, 35 and 27. Signed-off-by: Eric Bénard Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/ehci.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm/plat-mxc/ehci.c') diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index 4bac3d5545d3..b79c8090197c 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -115,7 +115,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) #endif /* if defined(CONFIG_SOC_IMX25) */ #if defined(CONFIG_ARCH_MX3) if (cpu_is_mx31()) { - v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + + v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); switch (port) { @@ -153,13 +153,13 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) return -EINVAL; } - writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + + writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); return 0; } if (cpu_is_mx35()) { - v = readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + + v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); switch (port) { @@ -196,7 +196,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) return -EINVAL; } - writel(v, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + + writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); return 0; } @@ -206,7 +206,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) /* On i.MX27 we can use the i.MX31 USBCTRL bits, they * are identical */ - v = readl(MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + + v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); switch (port) { case 0: /* OTG port */ @@ -241,7 +241,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) default: return -EINVAL; } - writel(v, MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + + writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); return 0; } -- cgit v1.2.2 From d94ed1287e11f91e4f4096838179984b0206be5e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 26 Nov 2010 12:25:58 -0200 Subject: ARM: mx5: introduce SOC_IMX51 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce SOC_IMX51 to keep consistency with the other i.MX devices Signed-off-by: Fabio Estevam Acked-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/ehci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/plat-mxc/ehci.c') diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index b79c8090197c..c1a7146dad96 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -246,7 +246,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) return 0; } #endif /* CONFIG_MACH_MX27 */ -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 if (cpu_is_mx51()) { void __iomem *usb_base; void __iomem *usbotg_base; -- cgit v1.2.2 From 28a4f908acb342350b9ecbfcdf0a999cb83e05aa Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 13 Dec 2010 10:47:05 -0200 Subject: ARM: mx5: check for error in ioremap Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/ehci.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/plat-mxc/ehci.c') diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index c1a7146dad96..d59f5feb3c54 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -254,6 +254,10 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) int ret = 0; usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + if (!usb_base) { + printk(KERN_ERR "%s(): ioremap failed\n", __func__); + return -ENOMEM; + } switch (port) { case 0: /* OTG port */ -- cgit v1.2.2 From 08406f540c7ce4cfed96fb240906eee04b9e3eb7 Mon Sep 17 00:00:00 2001 From: "Arnaud Patard (Rtp)" Date: Mon, 20 Dec 2010 16:48:56 +0100 Subject: arch/arm/plat-mxc/ehci.c: fix errors/typos This patch is fixing some issues : - MXC_OTG_UCTRL_OPM_BIT is for USBCTRL register and not PHYCTRL register. - the MXC_EHCI_WAKEUP_ENABLED check was only clearing the bits so never allows to set them. Signed-off-by: Arnaud Patard Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/ehci.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) (limited to 'arch/arm/plat-mxc/ehci.c') diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index d59f5feb3c54..a45660301b08 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -278,10 +278,13 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) if (flags & MXC_EHCI_INTERNAL_PHY) { v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); - if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v |= (MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is not used */ - else - v &= ~(MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is used */ + if (flags & MXC_EHCI_POWER_PINS_ENABLED) { + /* OC/USBPWR is not used */ + v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; + } else { + /* OC/USBPWR is used */ + v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; + } __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); @@ -289,16 +292,23 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */ else v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */ + if (flags & MXC_EHCI_POWER_PINS_ENABLED) + v |= MXC_OTG_UCTRL_OPM_BIT; + else + v &= ~MXC_OTG_UCTRL_OPM_BIT; __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); } break; case 1: /* Host 1 */ /*Host ULPI */ v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); - if (flags & MXC_EHCI_WAKEUP_ENABLED) - v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */ - else - v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */ + if (flags & MXC_EHCI_WAKEUP_ENABLED) { + /* HOST1 wakeup/ULPI intr enable */ + v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT); + } else { + /* HOST1 wakeup/ULPI intr disable */ + v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT); + } if (flags & MXC_EHCI_POWER_PINS_ENABLED) v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ -- cgit v1.2.2 From 8305ed75d1418f02933a48bcabdbb5032d885628 Mon Sep 17 00:00:00 2001 From: "Arnaud Patard (Rtp)" Date: Mon, 20 Dec 2010 16:48:57 +0100 Subject: MX51: Add support for usb host 2 Signed-off-by: Arnaud Patard Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/ehci.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch/arm/plat-mxc/ehci.c') diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index a45660301b08..8772ce346a58 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -49,6 +49,7 @@ #define MXC_OTG_OFFSET 0 #define MXC_H1_OFFSET 0x200 +#define MXC_H2_OFFSET 0x400 /* USB_CTRL */ #define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */ @@ -61,6 +62,11 @@ #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ #define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ +/* USBH2CTRL */ +#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) +#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) +#define MXC_H2_UCTRL_H2PM_BIT (1 << 4) + #define MXC_USBCMD_OFFSET 0x140 /* USBCMD */ @@ -266,6 +272,9 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) case 1: /* Host 1 port */ usbotg_base = usb_base + MXC_H1_OFFSET; break; + case 2: /* Host 2 port */ + usbotg_base = usb_base + MXC_H2_OFFSET; + break; default: printk(KERN_ERR"%s no such port %d\n", __func__, port); ret = -ENOENT; @@ -329,6 +338,22 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK; __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET); break; + case 2: /* Host 2 ULPI */ + v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET); + if (flags & MXC_EHCI_WAKEUP_ENABLED) { + /* HOST1 wakeup/ULPI intr enable */ + v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT); + } else { + /* HOST1 wakeup/ULPI intr disable */ + v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT); + } + + if (flags & MXC_EHCI_POWER_PINS_ENABLED) + v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ + else + v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ + __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); + break; } error: -- cgit v1.2.2