From 991da17ec0b9f396154c8120ffd10e5d7d7aa361 Mon Sep 17 00:00:00 2001 From: Tim Abbott Date: Mon, 27 Apr 2009 14:02:22 -0400 Subject: arm: Use __INIT macro instead of .text.init. arm is placing some code in the .text.init section, but it does not reference that section in its linker scripts. This change moves this code from the .text.init section to the .init.text section, which is presumably where it belongs. Signed-off-by: Tim Abbott Acked-by: Russell King Acked-by: Sam Ravnborg Signed-off-by: Linus Torvalds --- arch/arm/mm/proc-v7.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/mm/proc-v7.S') diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index d1ebec42521d..c221e26ac1d3 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -9,6 +9,7 @@ * * This is the "shell" of the ARMv7 processor support. */ +#include #include #include #include @@ -153,7 +154,7 @@ cpu_v7_name: .ascii "ARMv7 Processor" .align - .section ".text.init", #alloc, #execinstr + __INIT /* * __v7_setup -- cgit v1.2.2 From 7ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Thu, 30 Apr 2009 17:06:09 +0100 Subject: [ARM] 5487/1: ARM errata: Stale prediction on replaced interworking branch This patch adds the workaround for the 430973 Cortex-A8 (r1p0..r1p2) erratum. The BTAC/BTB is now flushed at every context switch. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mm/proc-v7.S | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/mm/proc-v7.S') diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index d1ebec42521d..fc81159596fe 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -95,6 +95,9 @@ ENTRY(cpu_v7_switch_mm) mov r2, #0 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id orr r0, r0, #TTB_FLAGS +#ifdef CONFIG_ARM_ERRATA_430973 + mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB +#endif mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID isb 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 @@ -180,6 +183,11 @@ __v7_setup: stmia r12, {r0-r5, r7, r9, r11, lr} bl v7_flush_dcache_all ldmia r12, {r0-r5, r7, r9, r11, lr} +#ifdef CONFIG_ARM_ERRATA_430973 + mrc p15, 0, r10, c1, c0, 1 @ read aux control register + orr r10, r10, #(1 << 6) @ set IBE to 1 + mcr p15, 0, r10, c1, c0, 1 @ write aux control register +#endif mov r10, #0 #ifdef HARVARD_CACHE mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate -- cgit v1.2.2 From 855c551f5b8cc3815d58e1056c1f1e7c461e2d24 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Thu, 30 Apr 2009 17:06:15 +0100 Subject: [ARM] 5490/1: ARM errata: Processor deadlock when a false hazard is created This patch adds a workaround for the 458693 Cortex-A8 (r2p0) erratum. It sets the corresponding bits in the auxiliary control register so that the PLD instruction becomes a NOP. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mm/proc-v7.S | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/mm/proc-v7.S') diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index fc81159596fe..370baa7a0f08 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -187,6 +187,12 @@ __v7_setup: mrc p15, 0, r10, c1, c0, 1 @ read aux control register orr r10, r10, #(1 << 6) @ set IBE to 1 mcr p15, 0, r10, c1, c0, 1 @ write aux control register +#endif +#ifdef CONFIG_ARM_ERRATA_458693 + mrc p15, 0, r10, c1, c0, 1 @ read aux control register + orr r10, r10, #(1 << 5) @ set L1NEON to 1 + orr r10, r10, #(1 << 9) @ set PLDNOP to 1 + mcr p15, 0, r10, c1, c0, 1 @ write aux control register #endif mov r10, #0 #ifdef HARVARD_CACHE -- cgit v1.2.2 From 0516e4643cd22fc9f535aef02ad1de66c382c93b Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Thu, 30 Apr 2009 17:06:20 +0100 Subject: [ARM] 5489/1: ARM errata: Data written to the L2 cache can be overwritten with stale data This patch is a workaround for the 460075 Cortex-A8 (r2p0) erratum. It configures the L2 cache auxiliary control register so that the Write Allocate mode for the L2 cache is disabled. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mm/proc-v7.S | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/mm/proc-v7.S') diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 370baa7a0f08..f2305441e7d1 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -193,6 +193,11 @@ __v7_setup: orr r10, r10, #(1 << 5) @ set L1NEON to 1 orr r10, r10, #(1 << 9) @ set PLDNOP to 1 mcr p15, 0, r10, c1, c0, 1 @ write aux control register +#endif +#ifdef CONFIG_ARM_ERRATA_460075 + mrc p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register + orr r10, r10, #(1 << 22) @ set the Write Allocate disable bit + mcr p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register #endif mov r10, #0 #ifdef HARVARD_CACHE -- cgit v1.2.2