From 8970ef47d56fd3db28ee798b9d400caf08abd924 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Thu, 19 Mar 2009 15:02:34 +0000 Subject: [ARM] S3C24XX: Remove hardware specific registers from DMA calls The S3C24XX DMA API channel configuration registers are being passed values comprised of register values which makes it hard to move the API to cover both the S3C24XX and S3C64XX. These values can be calculated from knowing which device the channel is connected to, so remove them from the two calls s3c2410_dma_config and s3c2410_dma_devconfig. Signed-off-by: Ben Dooks Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/dma.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/mach-s3c2410/include') diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h index 13358ce2128c..acaef6784e95 100644 --- a/arch/arm/mach-s3c2410/include/mach/dma.h +++ b/arch/arm/mach-s3c2410/include/mach/dma.h @@ -206,10 +206,10 @@ struct s3c2410_dma_chan { /* channel configuration */ enum s3c2410_dmasrc source; + enum dma_ch req_ch; unsigned long dev_addr; unsigned long load_timeout; unsigned int flags; /* channel flags */ - unsigned int hw_cfg; /* last hw config */ struct s3c24xx_dma_map *map; /* channel hw maps */ @@ -290,7 +290,7 @@ extern int s3c2410_dma_enqueue(unsigned int channel, void *id, * configure the dma channel */ -extern int s3c2410_dma_config(unsigned int channel, int xferunit, int dcon); +extern int s3c2410_dma_config(unsigned int channel, int xferunit); /* s3c2410_dma_devconfig * @@ -298,7 +298,7 @@ extern int s3c2410_dma_config(unsigned int channel, int xferunit, int dcon); */ extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source, - int hwcfg, unsigned long devaddr); + unsigned long devaddr); /* s3c2410_dma_getposition * -- cgit v1.2.2 From 44dc94045f6ddbc07db3e0eb3448c2efc13ac2cf Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Thu, 19 Mar 2009 15:02:35 +0000 Subject: [ARM] S3C24XX: DMA: Split hardware regs out of The is for the driver API for the DMA system and should not have anything relying on the CPU specific registers. Remove the registers to for the code that really needs to know about them. Signed-off-by: Ben Dooks Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/dma.h | 137 +------------------------------ 1 file changed, 1 insertion(+), 136 deletions(-) (limited to 'arch/arm/mach-s3c2410/include') diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h index acaef6784e95..6cefa56e6a1f 100644 --- a/arch/arm/mach-s3c2410/include/mach/dma.h +++ b/arch/arm/mach-s3c2410/include/mach/dma.h @@ -3,7 +3,7 @@ * Copyright (C) 2003,2004,2006 Simtec Electronics * Ben Dooks * - * Samsung S3C241XX DMA support + * Samsung S3C24XX DMA support * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -68,7 +68,6 @@ enum s3c2410_dma_state { S3C2410_DMA_PAUSED }; - /* enum s3c2410_dma_loadst * * This represents the state of the DMA engine, wrt to the loaded / running @@ -311,138 +310,4 @@ extern int s3c2410_dma_getposition(unsigned int channel, extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn); extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn); -/* DMA Register definitions */ - -#define S3C2410_DMA_DISRC (0x00) -#define S3C2410_DMA_DISRCC (0x04) -#define S3C2410_DMA_DIDST (0x08) -#define S3C2410_DMA_DIDSTC (0x0C) -#define S3C2410_DMA_DCON (0x10) -#define S3C2410_DMA_DSTAT (0x14) -#define S3C2410_DMA_DCSRC (0x18) -#define S3C2410_DMA_DCDST (0x1C) -#define S3C2410_DMA_DMASKTRIG (0x20) -#define S3C2412_DMA_DMAREQSEL (0x24) -#define S3C2443_DMA_DMAREQSEL (0x24) - -#define S3C2410_DISRCC_INC (1<<0) -#define S3C2410_DISRCC_APB (1<<1) - -#define S3C2410_DMASKTRIG_STOP (1<<2) -#define S3C2410_DMASKTRIG_ON (1<<1) -#define S3C2410_DMASKTRIG_SWTRIG (1<<0) - -#define S3C2410_DCON_DEMAND (0<<31) -#define S3C2410_DCON_HANDSHAKE (1<<31) -#define S3C2410_DCON_SYNC_PCLK (0<<30) -#define S3C2410_DCON_SYNC_HCLK (1<<30) - -#define S3C2410_DCON_INTREQ (1<<29) - -#define S3C2410_DCON_CH0_XDREQ0 (0<<24) -#define S3C2410_DCON_CH0_UART0 (1<<24) -#define S3C2410_DCON_CH0_SDI (2<<24) -#define S3C2410_DCON_CH0_TIMER (3<<24) -#define S3C2410_DCON_CH0_USBEP1 (4<<24) - -#define S3C2410_DCON_CH1_XDREQ1 (0<<24) -#define S3C2410_DCON_CH1_UART1 (1<<24) -#define S3C2410_DCON_CH1_I2SSDI (2<<24) -#define S3C2410_DCON_CH1_SPI (3<<24) -#define S3C2410_DCON_CH1_USBEP2 (4<<24) - -#define S3C2410_DCON_CH2_I2SSDO (0<<24) -#define S3C2410_DCON_CH2_I2SSDI (1<<24) -#define S3C2410_DCON_CH2_SDI (2<<24) -#define S3C2410_DCON_CH2_TIMER (3<<24) -#define S3C2410_DCON_CH2_USBEP3 (4<<24) - -#define S3C2410_DCON_CH3_UART2 (0<<24) -#define S3C2410_DCON_CH3_SDI (1<<24) -#define S3C2410_DCON_CH3_SPI (2<<24) -#define S3C2410_DCON_CH3_TIMER (3<<24) -#define S3C2410_DCON_CH3_USBEP4 (4<<24) - -#define S3C2410_DCON_SRCSHIFT (24) -#define S3C2410_DCON_SRCMASK (7<<24) - -#define S3C2410_DCON_BYTE (0<<20) -#define S3C2410_DCON_HALFWORD (1<<20) -#define S3C2410_DCON_WORD (2<<20) - -#define S3C2410_DCON_AUTORELOAD (0<<22) -#define S3C2410_DCON_NORELOAD (1<<22) -#define S3C2410_DCON_HWTRIG (1<<23) - -#ifdef CONFIG_CPU_S3C2440 -#define S3C2440_DIDSTC_CHKINT (1<<2) - -#define S3C2440_DCON_CH0_I2SSDO (5<<24) -#define S3C2440_DCON_CH0_PCMIN (6<<24) - -#define S3C2440_DCON_CH1_PCMOUT (5<<24) -#define S3C2440_DCON_CH1_SDI (6<<24) - -#define S3C2440_DCON_CH2_PCMIN (5<<24) -#define S3C2440_DCON_CH2_MICIN (6<<24) - -#define S3C2440_DCON_CH3_MICIN (5<<24) -#define S3C2440_DCON_CH3_PCMOUT (6<<24) -#endif - -#ifdef CONFIG_CPU_S3C2412 - -#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1) - -#define S3C2412_DMAREQSEL_HW (1) - -#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0) -#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1) -#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2) -#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3) -#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4) -#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5) -#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9) -#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10) -#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13) -#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14) -#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15) -#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16) -#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17) -#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18) -#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19) -#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20) -#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21) -#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22) -#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23) -#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24) - -#endif - -#define S3C2443_DMAREQSEL_SRC(x) ((x)<<1) - -#define S3C2443_DMAREQSEL_HW (1) - -#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0) -#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1) -#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2) -#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3) -#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4) -#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5) -#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9) -#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10) -#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17) -#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18) -#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19) -#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20) -#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21) -#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22) -#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23) -#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24) -#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25) -#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26) -#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27) -#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28) -#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29) - #endif /* __ASM_ARCH_DMA_H */ -- cgit v1.2.2 From c133c290118bfc99cd7a23b5a00b5252d2be90c8 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Thu, 19 Mar 2009 15:02:37 +0000 Subject: [ARM] S3C: Make common header Move the common information from the header into a new shareable header for re-use on the s3c64xx. Signed-off-by: Ben Dooks Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/dma.h | 117 +------------------------------ 1 file changed, 3 insertions(+), 114 deletions(-) (limited to 'arch/arm/mach-s3c2410/include') diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h index 6cefa56e6a1f..2fbabecf4f6e 100644 --- a/arch/arm/mach-s3c2410/include/mach/dma.h +++ b/arch/arm/mach-s3c2410/include/mach/dma.h @@ -13,6 +13,7 @@ #ifndef __ASM_ARCH_DMA_H #define __ASM_ARCH_DMA_H __FILE__ +#include #include #include @@ -103,32 +104,6 @@ enum s3c2410_dma_loadst { S3C2410_DMALOAD_1LOADED_1RUNNING, }; -enum s3c2410_dma_buffresult { - S3C2410_RES_OK, - S3C2410_RES_ERR, - S3C2410_RES_ABORT -}; - -enum s3c2410_dmasrc { - S3C2410_DMASRC_HW, /* source is memory */ - S3C2410_DMASRC_MEM /* source is hardware */ -}; - -/* enum s3c2410_chan_op - * - * operation codes passed to the DMA code by the user, and also used - * to inform the current channel owner of any changes to the system state -*/ - -enum s3c2410_chan_op { - S3C2410_DMAOP_START, - S3C2410_DMAOP_STOP, - S3C2410_DMAOP_PAUSE, - S3C2410_DMAOP_RESUME, - S3C2410_DMAOP_FLUSH, - S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */ - S3C2410_DMAOP_STARTED, /* indicate channel started */ -}; /* flags */ @@ -138,17 +113,14 @@ enum s3c2410_chan_op { /* dma buffer */ -struct s3c2410_dma_client { - char *name; -}; +struct s3c2410_dma_buf; -/* s3c2410_dma_buf_s +/* s3c2410_dma_buf * * internally used buffer structure to describe a queued or running * buffer. */ -struct s3c2410_dma_buf; struct s3c2410_dma_buf { struct s3c2410_dma_buf *next; int magic; /* magic */ @@ -160,20 +132,6 @@ struct s3c2410_dma_buf { /* [1] is this updated for both recv/send modes? */ -struct s3c2410_dma_chan; - -/* s3c2410_dma_cbfn_t - * - * buffer callback routine type -*/ - -typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *, - void *buf, int size, - enum s3c2410_dma_buffresult result); - -typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *, - enum s3c2410_chan_op ); - struct s3c2410_dma_stats { unsigned long loads; unsigned long timeout_longest; @@ -241,73 +199,4 @@ extern struct s3c2410_dma_chan s3c2410_chans[]; /* note, we don't really use dma_device_t at the moment */ typedef unsigned long dma_device_t; -/* functions --------------------------------------------------------------- */ - -/* s3c2410_dma_request - * - * request a dma channel exclusivley -*/ - -extern int s3c2410_dma_request(unsigned int channel, - struct s3c2410_dma_client *, void *dev); - - -/* s3c2410_dma_ctrl - * - * change the state of the dma channel -*/ - -extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op); - -/* s3c2410_dma_setflags - * - * set the channel's flags to a given state -*/ - -extern int s3c2410_dma_setflags(unsigned int channel, - unsigned int flags); - -/* s3c2410_dma_free - * - * free the dma channel (will also abort any outstanding operations) -*/ - -extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *); - -/* s3c2410_dma_enqueue - * - * place the given buffer onto the queue of operations for the channel. - * The buffer must be allocated from dma coherent memory, or the Dcache/WB - * drained before the buffer is given to the DMA system. -*/ - -extern int s3c2410_dma_enqueue(unsigned int channel, void *id, - dma_addr_t data, int size); - -/* s3c2410_dma_config - * - * configure the dma channel -*/ - -extern int s3c2410_dma_config(unsigned int channel, int xferunit); - -/* s3c2410_dma_devconfig - * - * configure the device we're talking to -*/ - -extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source, - unsigned long devaddr); - -/* s3c2410_dma_getposition - * - * get the position that the dma transfer is currently at -*/ - -extern int s3c2410_dma_getposition(unsigned int channel, - dma_addr_t *src, dma_addr_t *dest); - -extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn); -extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn); - #endif /* __ASM_ARCH_DMA_H */ -- cgit v1.2.2 From 20934cdbaae9c26a31d7f593c6a747c687ae79a1 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Thu, 19 Mar 2009 15:02:38 +0000 Subject: [ARM] S3C24XX: dma.h should not include The dma.h header does not need to include as there is nothing it depends on. Remove the include and fixup the couple of places where was not explicitly included (dragged in via ) Note, we have to fix arch/arm/plat-s3c24xx/pm.c which seems to rely on having included by this method. Signed-off-by: Ben Dooks Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/dma.h | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/mach-s3c2410/include') diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h index 2fbabecf4f6e..1648311c7b47 100644 --- a/arch/arm/mach-s3c2410/include/mach/dma.h +++ b/arch/arm/mach-s3c2410/include/mach/dma.h @@ -15,7 +15,6 @@ #include #include -#include #define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ -- cgit v1.2.2 From 97c1b145231730e62dd71921ec653315a1da3aad Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Thu, 19 Mar 2009 15:02:39 +0000 Subject: [ARM] S3C: Move DMA channel management code to plat-s3c Change the name of S3C2410_DMA_CHANNELS to S3C_DMA_CHANNELS in the process. Signed-off-by: Ben Dooks Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/dma.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'arch/arm/mach-s3c2410/include') diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h index 1648311c7b47..c3a2629e0ded 100644 --- a/arch/arm/mach-s3c2410/include/mach/dma.h +++ b/arch/arm/mach-s3c2410/include/mach/dma.h @@ -55,9 +55,9 @@ enum dma_ch { /* we have 4 dma channels */ #ifndef CONFIG_CPU_S3C2443 -#define S3C2410_DMA_CHANNELS (4) +#define S3C_DMA_CHANNELS (4) #else -#define S3C2410_DMA_CHANNELS (6) +#define S3C_DMA_CHANNELS (6) #endif /* types */ @@ -192,10 +192,6 @@ struct s3c2410_dma_chan { struct sys_device dev; }; -/* the currently allocated channel information */ -extern struct s3c2410_dma_chan s3c2410_chans[]; - -/* note, we don't really use dma_device_t at the moment */ typedef unsigned long dma_device_t; #endif /* __ASM_ARCH_DMA_H */ -- cgit v1.2.2 From e6a2a9ce69400a8109e01030aec0d5e1e2bc73c2 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 6 Mar 2009 19:51:50 +0000 Subject: [ARM] S3C: Rename S3C24XX_PA_USBHOST to S3C_PA_USBHOST The USB host base address is available on both the S3C24XX and S3C64XX ranges. Signed-off-by: Ben Dooks Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/map.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-s3c2410/include') diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h index 255fdfeaf957..e99b212cb1ca 100644 --- a/arch/arm/mach-s3c2410/include/mach/map.h +++ b/arch/arm/mach-s3c2410/include/mach/map.h @@ -84,7 +84,6 @@ #define S3C24XX_PA_IRQ S3C2410_PA_IRQ #define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL -#define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST #define S3C24XX_PA_DMA S3C2410_PA_DMA #define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR #define S3C24XX_PA_LCD S3C2410_PA_LCD @@ -102,6 +101,7 @@ #define S3C_PA_IIC S3C2410_PA_IIC #define S3C_PA_UART S3C24XX_PA_UART +#define S3C_PA_USBHOST S3C2410_PA_USBHOST #define S3C_PA_HSMMC0 S3C2443_PA_HSMMC #endif /* __ASM_ARCH_MAP_H */ -- cgit v1.2.2 From ec7f4d5d67ef63c724ab6d4bdc7d2ffa8861071a Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 13 May 2009 22:20:35 +0100 Subject: [ARM] S3C24XX: GPIO: Remove s3c2410_gpio_irq2pin() call Remove the s3c2410_gpio_irq2pin() function as it is not being used in any in kernel driver and the function is probably not being used anywhere else. This is also part of the effort to remove any of the s3c24xx gpio specific code that cannot be recreated by using the gpiolib framework now in the kernel. Signed-off-by: Ben Dooks Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/hardware.h | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'arch/arm/mach-s3c2410/include') diff --git a/arch/arm/mach-s3c2410/include/mach/hardware.h b/arch/arm/mach-s3c2410/include/mach/hardware.h index 74d5a1a4024c..d7745d85392e 100644 --- a/arch/arm/mach-s3c2410/include/mach/hardware.h +++ b/arch/arm/mach-s3c2410/include/mach/hardware.h @@ -46,17 +46,6 @@ extern unsigned int s3c2410_gpio_getcfg(unsigned int pin); extern int s3c2410_gpio_getirq(unsigned int pin); -/* s3c2410_gpio_irq2pin - * - * turn the given irq number into the corresponding GPIO number - * - * returns: - * < 0 = no pin - * >=0 = gpio pin number -*/ - -extern int s3c2410_gpio_irq2pin(unsigned int irq); - #ifdef CONFIG_CPU_S3C2400 extern int s3c2400_gpio_getirq(unsigned int pin); -- cgit v1.2.2 From 3cba5ef862bc2c2a0cf2841d993bfb99b9a6c476 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sun, 17 May 2009 23:30:45 +0100 Subject: [ARM] S3C: Move watchdog system reset to own file. Move the watchdog reset code from to a new file as this code is needed by both s3c2410, s3c64xx and soon-to-be added s3c24a0. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/system-reset.h | 36 ++--------------------- 1 file changed, 2 insertions(+), 34 deletions(-) (limited to 'arch/arm/mach-s3c2410/include') diff --git a/arch/arm/mach-s3c2410/include/mach/system-reset.h b/arch/arm/mach-s3c2410/include/mach/system-reset.h index b8687f71c304..6faadcee7729 100644 --- a/arch/arm/mach-s3c2410/include/mach/system-reset.h +++ b/arch/arm/mach-s3c2410/include/mach/system-reset.h @@ -11,21 +11,13 @@ */ #include -#include - -#include -#include - -#include -#include +#include extern void (*s3c24xx_reset_hook)(void); static void arch_reset(char mode, const char *cmd) { - struct clk *wdtclk; - if (mode == 's') { cpu_reset(0); } @@ -33,31 +25,7 @@ arch_reset(char mode, const char *cmd) if (s3c24xx_reset_hook) s3c24xx_reset_hook(); - printk("arch_reset: attempting watchdog reset\n"); - - __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */ - - wdtclk = clk_get(NULL, "watchdog"); - if (!IS_ERR(wdtclk)) { - clk_enable(wdtclk); - } else - printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__); - - /* put initial values into count and data */ - __raw_writel(0x80, S3C2410_WTCNT); - __raw_writel(0x80, S3C2410_WTDAT); - - /* set the watchdog to go and reset... */ - __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN | - S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON); - - /* wait for reset to assert... */ - mdelay(500); - - printk(KERN_ERR "Watchdog reset failed to assert reset\n"); - - /* delay to allow the serial port to show the message */ - mdelay(50); + arch_wdt_reset(); /* we'll take a jump through zero as a poor second */ cpu_reset(0); -- cgit v1.2.2 From ec976d6eb021dc8f2994248c310a41540f4756bd Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 13 May 2009 22:52:24 +0100 Subject: [ARM] S3C24XX: GPIO: Move gpio functions out of Move all the gpio functions out of as this file is for defining the generic IO base addresses for the kernel IO calls. Make a new header to take this and include it via the chain from which is what most of these files should be using (and will be changed as soon as possible). Note, this does make minor changes to some drivers but should not mess up any pending merges. CC: Richard Purdie Acked-by: Mark Brown CC: David Brownell Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/gpio-fns.h | 103 ++++++++++++++++++++++++++ arch/arm/mach-s3c2410/include/mach/gpio.h | 1 + arch/arm/mach-s3c2410/include/mach/hardware.h | 84 --------------------- 3 files changed, 104 insertions(+), 84 deletions(-) create mode 100644 arch/arm/mach-s3c2410/include/mach/gpio-fns.h (limited to 'arch/arm/mach-s3c2410/include') diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h new file mode 100644 index 000000000000..b4f39558beda --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h @@ -0,0 +1,103 @@ +/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h + * + * Copyright (c) 2003,2009 Simtec Electronics + * Ben Dooks + * + * S3C2410 - hardware + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* These functions are in the to-be-removed category and it is strongly + * encouraged not to use these in new code. They will be marked deprecated + * very soon. + * + * Most of the functionality can be either replaced by the gpiocfg calls + * for the s3c platform or by the generic GPIOlib API. +*/ + +/* external functions for GPIO support + * + * These allow various different clients to access the same GPIO + * registers without conflicting. If your driver only owns the entire + * GPIO register, then it is safe to ioremap/__raw_{read|write} to it. +*/ + +/* s3c2410_gpio_cfgpin + * + * set the configuration of the given pin to the value passed. + * + * eg: + * s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0); + * s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1); +*/ + +extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function); + +extern unsigned int s3c2410_gpio_getcfg(unsigned int pin); + +/* s3c2410_gpio_getirq + * + * turn the given pin number into the corresponding IRQ number + * + * returns: + * < 0 = no interrupt for this pin + * >=0 = interrupt number for the pin +*/ + +extern int s3c2410_gpio_getirq(unsigned int pin); + +#ifdef CONFIG_CPU_S3C2400 + +extern int s3c2400_gpio_getirq(unsigned int pin); + +#endif /* CONFIG_CPU_S3C2400 */ + +/* s3c2410_gpio_irqfilter + * + * set the irq filtering on the given pin + * + * on = 0 => disable filtering + * 1 => enable filtering + * + * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with + * width of filter (0 through 63) + * + * +*/ + +extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on, + unsigned int config); + +/* s3c2410_gpio_pullup + * + * configure the pull-up control on the given pin + * + * to = 1 => disable the pull-up + * 0 => enable the pull-up + * + * eg; + * + * s3c2410_gpio_pullup(S3C2410_GPB0, 0); + * s3c2410_gpio_pullup(S3C2410_GPE8, 0); +*/ + +extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to); + +/* s3c2410_gpio_getpull + * + * Read the state of the pull-up on a given pin + * + * return: + * < 0 => error code + * 0 => enabled + * 1 => disabled +*/ + +extern int s3c2410_gpio_getpull(unsigned int pin); + +extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to); + +extern unsigned int s3c2410_gpio_getpin(unsigned int pin); diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h index 51a88cf9526b..15f0b3e7ce69 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio.h @@ -24,5 +24,6 @@ #include #include +#include #define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32) diff --git a/arch/arm/mach-s3c2410/include/mach/hardware.h b/arch/arm/mach-s3c2410/include/mach/hardware.h index d7745d85392e..aef5631eac58 100644 --- a/arch/arm/mach-s3c2410/include/mach/hardware.h +++ b/arch/arm/mach-s3c2410/include/mach/hardware.h @@ -15,90 +15,6 @@ #ifndef __ASSEMBLY__ -/* external functions for GPIO support - * - * These allow various different clients to access the same GPIO - * registers without conflicting. If your driver only owns the entire - * GPIO register, then it is safe to ioremap/__raw_{read|write} to it. -*/ - -/* s3c2410_gpio_cfgpin - * - * set the configuration of the given pin to the value passed. - * - * eg: - * s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0); - * s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1); -*/ - -extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function); - -extern unsigned int s3c2410_gpio_getcfg(unsigned int pin); - -/* s3c2410_gpio_getirq - * - * turn the given pin number into the corresponding IRQ number - * - * returns: - * < 0 = no interrupt for this pin - * >=0 = interrupt number for the pin -*/ - -extern int s3c2410_gpio_getirq(unsigned int pin); - -#ifdef CONFIG_CPU_S3C2400 - -extern int s3c2400_gpio_getirq(unsigned int pin); - -#endif /* CONFIG_CPU_S3C2400 */ - -/* s3c2410_gpio_irqfilter - * - * set the irq filtering on the given pin - * - * on = 0 => disable filtering - * 1 => enable filtering - * - * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with - * width of filter (0 through 63) - * - * -*/ - -extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on, - unsigned int config); - -/* s3c2410_gpio_pullup - * - * configure the pull-up control on the given pin - * - * to = 1 => disable the pull-up - * 0 => enable the pull-up - * - * eg; - * - * s3c2410_gpio_pullup(S3C2410_GPB0, 0); - * s3c2410_gpio_pullup(S3C2410_GPE8, 0); -*/ - -extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to); - -/* s3c2410_gpio_getpull - * - * Read the state of the pull-up on a given pin - * - * return: - * < 0 => error code - * 0 => enabled - * 1 => disabled -*/ - -extern int s3c2410_gpio_getpull(unsigned int pin); - -extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to); - -extern unsigned int s3c2410_gpio_getpin(unsigned int pin); - extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg); #ifdef CONFIG_CPU_S3C2440 -- cgit v1.2.2 From 9c7099ca7519268f6ec79782bc06faa27a714d95 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sun, 17 May 2009 22:08:32 +0100 Subject: [ARM] S3C24XX: GPIO: Clean out unused definitions in The really does not need the input and output pin configurations as these are standard and have a generic representation (plus the s3c24xx gpio specific code is going to be phased out soon). The following sed was applied to remove the lines: sed -i~ -e '/S3C2410_GP[A-Z][0-9]*_\INP/d' \ -e '/S3C2410_GP[A-Z][0-9]*_\OUTP/d' \ -e '/S3C2410_GPA[0-9]*_OUT/d' to remove these. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/regs-gpio.h | 211 ------------------------- 1 file changed, 211 deletions(-) (limited to 'arch/arm/mach-s3c2410/include') diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h index 35a03df473fc..90cefebd2937 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h @@ -70,103 +70,80 @@ #define S3C2400_GPADAT S3C2410_GPIOREG(0x04) #define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0) -#define S3C2410_GPA0_OUT (0<<0) #define S3C2410_GPA0_ADDR0 (1<<0) #define S3C2410_GPA1 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1) -#define S3C2410_GPA1_OUT (0<<1) #define S3C2410_GPA1_ADDR16 (1<<1) #define S3C2410_GPA2 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2) -#define S3C2410_GPA2_OUT (0<<2) #define S3C2410_GPA2_ADDR17 (1<<2) #define S3C2410_GPA3 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3) -#define S3C2410_GPA3_OUT (0<<3) #define S3C2410_GPA3_ADDR18 (1<<3) #define S3C2410_GPA4 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4) -#define S3C2410_GPA4_OUT (0<<4) #define S3C2410_GPA4_ADDR19 (1<<4) #define S3C2410_GPA5 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5) -#define S3C2410_GPA5_OUT (0<<5) #define S3C2410_GPA5_ADDR20 (1<<5) #define S3C2410_GPA6 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6) -#define S3C2410_GPA6_OUT (0<<6) #define S3C2410_GPA6_ADDR21 (1<<6) #define S3C2410_GPA7 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7) -#define S3C2410_GPA7_OUT (0<<7) #define S3C2410_GPA7_ADDR22 (1<<7) #define S3C2410_GPA8 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8) -#define S3C2410_GPA8_OUT (0<<8) #define S3C2410_GPA8_ADDR23 (1<<8) #define S3C2410_GPA9 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9) -#define S3C2410_GPA9_OUT (0<<9) #define S3C2410_GPA9_ADDR24 (1<<9) #define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10) -#define S3C2410_GPA10_OUT (0<<10) #define S3C2410_GPA10_ADDR25 (1<<10) #define S3C2400_GPA10_SCKE (1<<10) #define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11) -#define S3C2410_GPA11_OUT (0<<11) #define S3C2410_GPA11_ADDR26 (1<<11) #define S3C2400_GPA11_nCAS0 (1<<11) #define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12) -#define S3C2410_GPA12_OUT (0<<12) #define S3C2410_GPA12_nGCS1 (1<<12) #define S3C2400_GPA12_nCAS1 (1<<12) #define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13) -#define S3C2410_GPA13_OUT (0<<13) #define S3C2410_GPA13_nGCS2 (1<<13) #define S3C2400_GPA13_nGCS1 (1<<13) #define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14) -#define S3C2410_GPA14_OUT (0<<14) #define S3C2410_GPA14_nGCS3 (1<<14) #define S3C2400_GPA14_nGCS2 (1<<14) #define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15) -#define S3C2410_GPA15_OUT (0<<15) #define S3C2410_GPA15_nGCS4 (1<<15) #define S3C2400_GPA15_nGCS3 (1<<15) #define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16) -#define S3C2410_GPA16_OUT (0<<16) #define S3C2410_GPA16_nGCS5 (1<<16) #define S3C2400_GPA16_nGCS4 (1<<16) #define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17) -#define S3C2410_GPA17_OUT (0<<17) #define S3C2410_GPA17_CLE (1<<17) #define S3C2400_GPA17_nGCS5 (1<<17) #define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18) -#define S3C2410_GPA18_OUT (0<<18) #define S3C2410_GPA18_ALE (1<<18) #define S3C2410_GPA19 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19) -#define S3C2410_GPA19_OUT (0<<19) #define S3C2410_GPA19_nFWE (1<<19) #define S3C2410_GPA20 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20) -#define S3C2410_GPA20_OUT (0<<20) #define S3C2410_GPA20_nFRE (1<<20) #define S3C2410_GPA21 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21) -#define S3C2410_GPA21_OUT (0<<21) #define S3C2410_GPA21_nRSTOUT (1<<21) #define S3C2410_GPA22 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22) -#define S3C2410_GPA22_OUT (0<<22) #define S3C2410_GPA22_nFCE (1<<22) /* 0x08 and 0x0c are reserved on S3C2410 */ @@ -195,34 +172,24 @@ /* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ #define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0) -#define S3C2410_GPB0_INP (0x00 << 0) -#define S3C2410_GPB0_OUTP (0x01 << 0) #define S3C2410_GPB0_TOUT0 (0x02 << 0) #define S3C2400_GPB0_DATA16 (0x02 << 0) #define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1) -#define S3C2410_GPB1_INP (0x00 << 2) -#define S3C2410_GPB1_OUTP (0x01 << 2) #define S3C2410_GPB1_TOUT1 (0x02 << 2) #define S3C2400_GPB1_DATA17 (0x02 << 2) #define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2) -#define S3C2410_GPB2_INP (0x00 << 4) -#define S3C2410_GPB2_OUTP (0x01 << 4) #define S3C2410_GPB2_TOUT2 (0x02 << 4) #define S3C2400_GPB2_DATA18 (0x02 << 4) #define S3C2400_GPB2_TCLK1 (0x03 << 4) #define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3) -#define S3C2410_GPB3_INP (0x00 << 6) -#define S3C2410_GPB3_OUTP (0x01 << 6) #define S3C2410_GPB3_TOUT3 (0x02 << 6) #define S3C2400_GPB3_DATA19 (0x02 << 6) #define S3C2400_GPB3_TXD1 (0x03 << 6) #define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4) -#define S3C2410_GPB4_INP (0x00 << 8) -#define S3C2410_GPB4_OUTP (0x01 << 8) #define S3C2410_GPB4_TCLK0 (0x02 << 8) #define S3C2400_GPB4_DATA20 (0x02 << 8) #define S3C2410_GPB4_MASK (0x03 << 8) @@ -230,45 +197,33 @@ #define S3C2400_GPB4_MASK (0x03 << 8) #define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5) -#define S3C2410_GPB5_INP (0x00 << 10) -#define S3C2410_GPB5_OUTP (0x01 << 10) #define S3C2410_GPB5_nXBACK (0x02 << 10) #define S3C2443_GPB5_XBACK (0x03 << 10) #define S3C2400_GPB5_DATA21 (0x02 << 10) #define S3C2400_GPB5_nCTS1 (0x03 << 10) #define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6) -#define S3C2410_GPB6_INP (0x00 << 12) -#define S3C2410_GPB6_OUTP (0x01 << 12) #define S3C2410_GPB6_nXBREQ (0x02 << 12) #define S3C2443_GPB6_XBREQ (0x03 << 12) #define S3C2400_GPB6_DATA22 (0x02 << 12) #define S3C2400_GPB6_nRTS1 (0x03 << 12) #define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7) -#define S3C2410_GPB7_INP (0x00 << 14) -#define S3C2410_GPB7_OUTP (0x01 << 14) #define S3C2410_GPB7_nXDACK1 (0x02 << 14) #define S3C2443_GPB7_XDACK1 (0x03 << 14) #define S3C2400_GPB7_DATA23 (0x02 << 14) #define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8) -#define S3C2410_GPB8_INP (0x00 << 16) -#define S3C2410_GPB8_OUTP (0x01 << 16) #define S3C2410_GPB8_nXDREQ1 (0x02 << 16) #define S3C2400_GPB8_DATA24 (0x02 << 16) #define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9) -#define S3C2410_GPB9_INP (0x00 << 18) -#define S3C2410_GPB9_OUTP (0x01 << 18) #define S3C2410_GPB9_nXDACK0 (0x02 << 18) #define S3C2443_GPB9_XDACK0 (0x03 << 18) #define S3C2400_GPB9_DATA25 (0x02 << 18) #define S3C2400_GPB9_I2SSDI (0x03 << 18) #define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10) -#define S3C2410_GPB10_INP (0x00 << 20) -#define S3C2410_GPB10_OUTP (0x01 << 20) #define S3C2410_GPB10_nXDRE0 (0x02 << 20) #define S3C2443_GPB10_XDREQ0 (0x03 << 20) #define S3C2400_GPB10_DATA26 (0x02 << 20) @@ -316,98 +271,66 @@ #define S3C2400_GPCUP S3C2410_GPIOREG(0x1C) #define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0) -#define S3C2410_GPC0_INP (0x00 << 0) -#define S3C2410_GPC0_OUTP (0x01 << 0) #define S3C2410_GPC0_LEND (0x02 << 0) #define S3C2400_GPC0_VD0 (0x02 << 0) #define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1) -#define S3C2410_GPC1_INP (0x00 << 2) -#define S3C2410_GPC1_OUTP (0x01 << 2) #define S3C2410_GPC1_VCLK (0x02 << 2) #define S3C2400_GPC1_VD1 (0x02 << 2) #define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2) -#define S3C2410_GPC2_INP (0x00 << 4) -#define S3C2410_GPC2_OUTP (0x01 << 4) #define S3C2410_GPC2_VLINE (0x02 << 4) #define S3C2400_GPC2_VD2 (0x02 << 4) #define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3) -#define S3C2410_GPC3_INP (0x00 << 6) -#define S3C2410_GPC3_OUTP (0x01 << 6) #define S3C2410_GPC3_VFRAME (0x02 << 6) #define S3C2400_GPC3_VD3 (0x02 << 6) #define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4) -#define S3C2410_GPC4_INP (0x00 << 8) -#define S3C2410_GPC4_OUTP (0x01 << 8) #define S3C2410_GPC4_VM (0x02 << 8) #define S3C2400_GPC4_VD4 (0x02 << 8) #define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5) -#define S3C2410_GPC5_INP (0x00 << 10) -#define S3C2410_GPC5_OUTP (0x01 << 10) #define S3C2410_GPC5_LCDVF0 (0x02 << 10) #define S3C2400_GPC5_VD5 (0x02 << 10) #define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6) -#define S3C2410_GPC6_INP (0x00 << 12) -#define S3C2410_GPC6_OUTP (0x01 << 12) #define S3C2410_GPC6_LCDVF1 (0x02 << 12) #define S3C2400_GPC6_VD6 (0x02 << 12) #define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7) -#define S3C2410_GPC7_INP (0x00 << 14) -#define S3C2410_GPC7_OUTP (0x01 << 14) #define S3C2410_GPC7_LCDVF2 (0x02 << 14) #define S3C2400_GPC7_VD7 (0x02 << 14) #define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8) -#define S3C2410_GPC8_INP (0x00 << 16) -#define S3C2410_GPC8_OUTP (0x01 << 16) #define S3C2410_GPC8_VD0 (0x02 << 16) #define S3C2400_GPC8_VD8 (0x02 << 16) #define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9) -#define S3C2410_GPC9_INP (0x00 << 18) -#define S3C2410_GPC9_OUTP (0x01 << 18) #define S3C2410_GPC9_VD1 (0x02 << 18) #define S3C2400_GPC9_VD9 (0x02 << 18) #define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10) -#define S3C2410_GPC10_INP (0x00 << 20) -#define S3C2410_GPC10_OUTP (0x01 << 20) #define S3C2410_GPC10_VD2 (0x02 << 20) #define S3C2400_GPC10_VD10 (0x02 << 20) #define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11) -#define S3C2410_GPC11_INP (0x00 << 22) -#define S3C2410_GPC11_OUTP (0x01 << 22) #define S3C2410_GPC11_VD3 (0x02 << 22) #define S3C2400_GPC11_VD11 (0x02 << 22) #define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12) -#define S3C2410_GPC12_INP (0x00 << 24) -#define S3C2410_GPC12_OUTP (0x01 << 24) #define S3C2410_GPC12_VD4 (0x02 << 24) #define S3C2400_GPC12_VD12 (0x02 << 24) #define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13) -#define S3C2410_GPC13_INP (0x00 << 26) -#define S3C2410_GPC13_OUTP (0x01 << 26) #define S3C2410_GPC13_VD5 (0x02 << 26) #define S3C2400_GPC13_VD13 (0x02 << 26) #define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14) -#define S3C2410_GPC14_INP (0x00 << 28) -#define S3C2410_GPC14_OUTP (0x01 << 28) #define S3C2410_GPC14_VD6 (0x02 << 28) #define S3C2400_GPC14_VD14 (0x02 << 28) #define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15) -#define S3C2410_GPC15_INP (0x00 << 30) -#define S3C2410_GPC15_OUTP (0x01 << 30) #define S3C2410_GPC15_VD7 (0x02 << 30) #define S3C2400_GPC15_VD15 (0x02 << 30) @@ -433,98 +356,66 @@ #define S3C2400_GPDUP S3C2410_GPIOREG(0x28) #define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0) -#define S3C2410_GPD0_INP (0x00 << 0) -#define S3C2410_GPD0_OUTP (0x01 << 0) #define S3C2410_GPD0_VD8 (0x02 << 0) #define S3C2400_GPD0_VFRAME (0x02 << 0) #define S3C2442_GPD0_nSPICS1 (0x03 << 0) #define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1) -#define S3C2410_GPD1_INP (0x00 << 2) -#define S3C2410_GPD1_OUTP (0x01 << 2) #define S3C2410_GPD1_VD9 (0x02 << 2) #define S3C2400_GPD1_VM (0x02 << 2) #define S3C2442_GPD1_SPICLK1 (0x03 << 2) #define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2) -#define S3C2410_GPD2_INP (0x00 << 4) -#define S3C2410_GPD2_OUTP (0x01 << 4) #define S3C2410_GPD2_VD10 (0x02 << 4) #define S3C2400_GPD2_VLINE (0x02 << 4) #define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3) -#define S3C2410_GPD3_INP (0x00 << 6) -#define S3C2410_GPD3_OUTP (0x01 << 6) #define S3C2410_GPD3_VD11 (0x02 << 6) #define S3C2400_GPD3_VCLK (0x02 << 6) #define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4) -#define S3C2410_GPD4_INP (0x00 << 8) -#define S3C2410_GPD4_OUTP (0x01 << 8) #define S3C2410_GPD4_VD12 (0x02 << 8) #define S3C2400_GPD4_LEND (0x02 << 8) #define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5) -#define S3C2410_GPD5_INP (0x00 << 10) -#define S3C2410_GPD5_OUTP (0x01 << 10) #define S3C2410_GPD5_VD13 (0x02 << 10) #define S3C2400_GPD5_TOUT0 (0x02 << 10) #define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6) -#define S3C2410_GPD6_INP (0x00 << 12) -#define S3C2410_GPD6_OUTP (0x01 << 12) #define S3C2410_GPD6_VD14 (0x02 << 12) #define S3C2400_GPD6_TOUT1 (0x02 << 12) #define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7) -#define S3C2410_GPD7_INP (0x00 << 14) -#define S3C2410_GPD7_OUTP (0x01 << 14) #define S3C2410_GPD7_VD15 (0x02 << 14) #define S3C2400_GPD7_TOUT2 (0x02 << 14) #define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8) -#define S3C2410_GPD8_INP (0x00 << 16) -#define S3C2410_GPD8_OUTP (0x01 << 16) #define S3C2410_GPD8_VD16 (0x02 << 16) #define S3C2400_GPD8_TOUT3 (0x02 << 16) #define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9) -#define S3C2410_GPD9_INP (0x00 << 18) -#define S3C2410_GPD9_OUTP (0x01 << 18) #define S3C2410_GPD9_VD17 (0x02 << 18) #define S3C2400_GPD9_TCLK0 (0x02 << 18) #define S3C2410_GPD9_MASK (0x03 << 18) #define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10) -#define S3C2410_GPD10_INP (0x00 << 20) -#define S3C2410_GPD10_OUTP (0x01 << 20) #define S3C2410_GPD10_VD18 (0x02 << 20) #define S3C2400_GPD10_nWAIT (0x02 << 20) #define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11) -#define S3C2410_GPD11_INP (0x00 << 22) -#define S3C2410_GPD11_OUTP (0x01 << 22) #define S3C2410_GPD11_VD19 (0x02 << 22) #define S3C2410_GPD12 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12) -#define S3C2410_GPD12_INP (0x00 << 24) -#define S3C2410_GPD12_OUTP (0x01 << 24) #define S3C2410_GPD12_VD20 (0x02 << 24) #define S3C2410_GPD13 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13) -#define S3C2410_GPD13_INP (0x00 << 26) -#define S3C2410_GPD13_OUTP (0x01 << 26) #define S3C2410_GPD13_VD21 (0x02 << 26) #define S3C2410_GPD14 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14) -#define S3C2410_GPD14_INP (0x00 << 28) -#define S3C2410_GPD14_OUTP (0x01 << 28) #define S3C2410_GPD14_VD22 (0x02 << 28) #define S3C2410_GPD14_nSS1 (0x03 << 28) #define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15) -#define S3C2410_GPD15_INP (0x00 << 30) -#define S3C2410_GPD15_OUTP (0x01 << 30) #define S3C2410_GPD15_VD23 (0x02 << 30) #define S3C2410_GPD15_nSS0 (0x03 << 30) @@ -551,16 +442,12 @@ #define S3C2400_GPEUP S3C2410_GPIOREG(0x34) #define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0) -#define S3C2410_GPE0_INP (0x00 << 0) -#define S3C2410_GPE0_OUTP (0x01 << 0) #define S3C2410_GPE0_I2SLRCK (0x02 << 0) #define S3C2443_GPE0_AC_nRESET (0x03 << 0) #define S3C2400_GPE0_EINT0 (0x02 << 0) #define S3C2410_GPE0_MASK (0x03 << 0) #define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1) -#define S3C2410_GPE1_INP (0x00 << 2) -#define S3C2410_GPE1_OUTP (0x01 << 2) #define S3C2410_GPE1_I2SSCLK (0x02 << 2) #define S3C2443_GPE1_AC_SYNC (0x03 << 2) #define S3C2400_GPE1_EINT1 (0x02 << 2) @@ -568,16 +455,12 @@ #define S3C2410_GPE1_MASK (0x03 << 2) #define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2) -#define S3C2410_GPE2_INP (0x00 << 4) -#define S3C2410_GPE2_OUTP (0x01 << 4) #define S3C2410_GPE2_CDCLK (0x02 << 4) #define S3C2443_GPE2_AC_BITCLK (0x03 << 4) #define S3C2400_GPE2_EINT2 (0x02 << 4) #define S3C2400_GPE2_I2SSDI (0x03 << 4) #define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3) -#define S3C2410_GPE3_INP (0x00 << 6) -#define S3C2410_GPE3_OUTP (0x01 << 6) #define S3C2410_GPE3_I2SSDI (0x02 << 6) #define S3C2443_GPE3_AC_SDI (0x03 << 6) #define S3C2400_GPE3_EINT3 (0x02 << 6) @@ -586,8 +469,6 @@ #define S3C2410_GPE3_MASK (0x03 << 6) #define S3C2410_GPE4 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4) -#define S3C2410_GPE4_INP (0x00 << 8) -#define S3C2410_GPE4_OUTP (0x01 << 8) #define S3C2410_GPE4_I2SSDO (0x02 << 8) #define S3C2443_GPE4_AC_SDO (0x03 << 8) #define S3C2400_GPE4_EINT4 (0x02 << 8) @@ -596,40 +477,30 @@ #define S3C2410_GPE4_MASK (0x03 << 8) #define S3C2410_GPE5 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5) -#define S3C2410_GPE5_INP (0x00 << 10) -#define S3C2410_GPE5_OUTP (0x01 << 10) #define S3C2410_GPE5_SDCLK (0x02 << 10) #define S3C2443_GPE5_SD1_CLK (0x02 << 10) #define S3C2400_GPE5_EINT5 (0x02 << 10) #define S3C2400_GPE5_TCLK1 (0x03 << 10) #define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6) -#define S3C2410_GPE6_INP (0x00 << 12) -#define S3C2410_GPE6_OUTP (0x01 << 12) #define S3C2410_GPE6_SDCMD (0x02 << 12) #define S3C2443_GPE6_SD1_CMD (0x02 << 12) #define S3C2443_GPE6_AC_BITCLK (0x03 << 12) #define S3C2400_GPE6_EINT6 (0x02 << 12) #define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7) -#define S3C2410_GPE7_INP (0x00 << 14) -#define S3C2410_GPE7_OUTP (0x01 << 14) #define S3C2410_GPE7_SDDAT0 (0x02 << 14) #define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) #define S3C2443_GPE7_AC_SDI (0x03 << 14) #define S3C2400_GPE7_EINT7 (0x02 << 14) #define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8) -#define S3C2410_GPE8_INP (0x00 << 16) -#define S3C2410_GPE8_OUTP (0x01 << 16) #define S3C2410_GPE8_SDDAT1 (0x02 << 16) #define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) #define S3C2443_GPE8_AC_SDO (0x03 << 16) #define S3C2400_GPE8_nXDACK0 (0x02 << 16) #define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9) -#define S3C2410_GPE9_INP (0x00 << 18) -#define S3C2410_GPE9_OUTP (0x01 << 18) #define S3C2410_GPE9_SDDAT2 (0x02 << 18) #define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) #define S3C2443_GPE9_AC_SYNC (0x03 << 18) @@ -637,39 +508,27 @@ #define S3C2400_GPE9_nXBACK (0x03 << 18) #define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10) -#define S3C2410_GPE10_INP (0x00 << 20) -#define S3C2410_GPE10_OUTP (0x01 << 20) #define S3C2410_GPE10_SDDAT3 (0x02 << 20) #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) #define S3C2443_GPE10_AC_nRESET (0x03 << 20) #define S3C2400_GPE10_nXDREQ0 (0x02 << 20) #define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11) -#define S3C2410_GPE11_INP (0x00 << 22) -#define S3C2410_GPE11_OUTP (0x01 << 22) #define S3C2410_GPE11_SPIMISO0 (0x02 << 22) #define S3C2400_GPE11_nXDREQ1 (0x02 << 22) #define S3C2400_GPE11_nXBREQ (0x03 << 22) #define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12) -#define S3C2410_GPE12_INP (0x00 << 24) -#define S3C2410_GPE12_OUTP (0x01 << 24) #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) #define S3C2410_GPE13 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13) -#define S3C2410_GPE13_INP (0x00 << 26) -#define S3C2410_GPE13_OUTP (0x01 << 26) #define S3C2410_GPE13_SPICLK0 (0x02 << 26) #define S3C2410_GPE14 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14) -#define S3C2410_GPE14_INP (0x00 << 28) -#define S3C2410_GPE14_OUTP (0x01 << 28) #define S3C2410_GPE14_IICSCL (0x02 << 28) #define S3C2410_GPE14_MASK (0x03 << 28) #define S3C2410_GPE15 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15) -#define S3C2410_GPE15_INP (0x00 << 30) -#define S3C2410_GPE15_OUTP (0x01 << 30) #define S3C2410_GPE15_IICSDA (0x02 << 30) #define S3C2410_GPE15_MASK (0x03 << 30) @@ -706,54 +565,38 @@ #define S3C2400_GPFUP S3C2410_GPIOREG(0x40) #define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0) -#define S3C2410_GPF0_INP (0x00 << 0) -#define S3C2410_GPF0_OUTP (0x01 << 0) #define S3C2410_GPF0_EINT0 (0x02 << 0) #define S3C2400_GPF0_RXD0 (0x02 << 0) #define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1) -#define S3C2410_GPF1_INP (0x00 << 2) -#define S3C2410_GPF1_OUTP (0x01 << 2) #define S3C2410_GPF1_EINT1 (0x02 << 2) #define S3C2400_GPF1_RXD1 (0x02 << 2) #define S3C2400_GPF1_IICSDA (0x03 << 2) #define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2) -#define S3C2410_GPF2_INP (0x00 << 4) -#define S3C2410_GPF2_OUTP (0x01 << 4) #define S3C2410_GPF2_EINT2 (0x02 << 4) #define S3C2400_GPF2_TXD0 (0x02 << 4) #define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3) -#define S3C2410_GPF3_INP (0x00 << 6) -#define S3C2410_GPF3_OUTP (0x01 << 6) #define S3C2410_GPF3_EINT3 (0x02 << 6) #define S3C2400_GPF3_TXD1 (0x02 << 6) #define S3C2400_GPF3_IICSCL (0x03 << 6) #define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4) -#define S3C2410_GPF4_INP (0x00 << 8) -#define S3C2410_GPF4_OUTP (0x01 << 8) #define S3C2410_GPF4_EINT4 (0x02 << 8) #define S3C2400_GPF4_nRTS0 (0x02 << 8) #define S3C2400_GPF4_nXBACK (0x03 << 8) #define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5) -#define S3C2410_GPF5_INP (0x00 << 10) -#define S3C2410_GPF5_OUTP (0x01 << 10) #define S3C2410_GPF5_EINT5 (0x02 << 10) #define S3C2400_GPF5_nCTS0 (0x02 << 10) #define S3C2400_GPF5_nXBREQ (0x03 << 10) #define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6) -#define S3C2410_GPF6_INP (0x00 << 12) -#define S3C2410_GPF6_OUTP (0x01 << 12) #define S3C2410_GPF6_EINT6 (0x02 << 12) #define S3C2400_GPF6_CLKOUT (0x02 << 12) #define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7) -#define S3C2410_GPF7_INP (0x00 << 14) -#define S3C2410_GPF7_OUTP (0x01 << 14) #define S3C2410_GPF7_EINT7 (0x02 << 14) #define S3C2410_GPF_PUPDIS(x) (1<<(x)) @@ -779,35 +622,25 @@ #define S3C2400_GPGUP S3C2410_GPIOREG(0x4C) #define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0) -#define S3C2410_GPG0_INP (0x00 << 0) -#define S3C2410_GPG0_OUTP (0x01 << 0) #define S3C2410_GPG0_EINT8 (0x02 << 0) #define S3C2400_GPG0_I2SLRCK (0x02 << 0) #define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1) -#define S3C2410_GPG1_INP (0x00 << 2) -#define S3C2410_GPG1_OUTP (0x01 << 2) #define S3C2410_GPG1_EINT9 (0x02 << 2) #define S3C2400_GPG1_I2SSCLK (0x02 << 2) #define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2) -#define S3C2410_GPG2_INP (0x00 << 4) -#define S3C2410_GPG2_OUTP (0x01 << 4) #define S3C2410_GPG2_EINT10 (0x02 << 4) #define S3C2410_GPG2_nSS0 (0x03 << 4) #define S3C2400_GPG2_CDCLK (0x02 << 4) #define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3) -#define S3C2410_GPG3_INP (0x00 << 6) -#define S3C2410_GPG3_OUTP (0x01 << 6) #define S3C2410_GPG3_EINT11 (0x02 << 6) #define S3C2410_GPG3_nSS1 (0x03 << 6) #define S3C2400_GPG3_I2SSDO (0x02 << 6) #define S3C2400_GPG3_I2SSDI (0x03 << 6) #define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4) -#define S3C2410_GPG4_INP (0x00 << 8) -#define S3C2410_GPG4_OUTP (0x01 << 8) #define S3C2410_GPG4_EINT12 (0x02 << 8) #define S3C2400_GPG4_MMCCLK (0x02 << 8) #define S3C2400_GPG4_I2SSDI (0x03 << 8) @@ -815,80 +648,58 @@ #define S3C2443_GPG4_LCDPWRDN (0x03 << 8) #define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5) -#define S3C2410_GPG5_INP (0x00 << 10) -#define S3C2410_GPG5_OUTP (0x01 << 10) #define S3C2410_GPG5_EINT13 (0x02 << 10) #define S3C2400_GPG5_MMCCMD (0x02 << 10) #define S3C2400_GPG5_IICSDA (0x03 << 10) #define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ #define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6) -#define S3C2410_GPG6_INP (0x00 << 12) -#define S3C2410_GPG6_OUTP (0x01 << 12) #define S3C2410_GPG6_EINT14 (0x02 << 12) #define S3C2400_GPG6_MMCDAT (0x02 << 12) #define S3C2400_GPG6_IICSCL (0x03 << 12) #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) #define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7) -#define S3C2410_GPG7_INP (0x00 << 14) -#define S3C2410_GPG7_OUTP (0x01 << 14) #define S3C2410_GPG7_EINT15 (0x02 << 14) #define S3C2410_GPG7_SPICLK1 (0x03 << 14) #define S3C2400_GPG7_SPIMISO (0x02 << 14) #define S3C2400_GPG7_IICSDA (0x03 << 14) #define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8) -#define S3C2410_GPG8_INP (0x00 << 16) -#define S3C2410_GPG8_OUTP (0x01 << 16) #define S3C2410_GPG8_EINT16 (0x02 << 16) #define S3C2400_GPG8_SPIMOSI (0x02 << 16) #define S3C2400_GPG8_IICSCL (0x03 << 16) #define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9) -#define S3C2410_GPG9_INP (0x00 << 18) -#define S3C2410_GPG9_OUTP (0x01 << 18) #define S3C2410_GPG9_EINT17 (0x02 << 18) #define S3C2400_GPG9_SPICLK (0x02 << 18) #define S3C2400_GPG9_MMCCLK (0x03 << 18) #define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10) -#define S3C2410_GPG10_INP (0x00 << 20) -#define S3C2410_GPG10_OUTP (0x01 << 20) #define S3C2410_GPG10_EINT18 (0x02 << 20) #define S3C2410_GPG11 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11) -#define S3C2410_GPG11_INP (0x00 << 22) -#define S3C2410_GPG11_OUTP (0x01 << 22) #define S3C2410_GPG11_EINT19 (0x02 << 22) #define S3C2410_GPG11_TCLK1 (0x03 << 22) #define S3C2443_GPG11_CF_nIREQ (0x03 << 22) #define S3C2410_GPG12 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12) -#define S3C2410_GPG12_INP (0x00 << 24) -#define S3C2410_GPG12_OUTP (0x01 << 24) #define S3C2410_GPG12_EINT20 (0x02 << 24) #define S3C2410_GPG12_XMON (0x03 << 24) #define S3C2442_GPG12_nSPICS0 (0x03 << 24) #define S3C2443_GPG12_nINPACK (0x03 << 24) #define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13) -#define S3C2410_GPG13_INP (0x00 << 26) -#define S3C2410_GPG13_OUTP (0x01 << 26) #define S3C2410_GPG13_EINT21 (0x02 << 26) #define S3C2410_GPG13_nXPON (0x03 << 26) #define S3C2443_GPG13_CF_nREG (0x03 << 26) #define S3C2410_GPG14 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14) -#define S3C2410_GPG14_INP (0x00 << 28) -#define S3C2410_GPG14_OUTP (0x01 << 28) #define S3C2410_GPG14_EINT22 (0x02 << 28) #define S3C2410_GPG14_YMON (0x03 << 28) #define S3C2443_GPG14_CF_RESET (0x03 << 28) #define S3C2410_GPG15 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15) -#define S3C2410_GPG15_INP (0x00 << 30) -#define S3C2410_GPG15_OUTP (0x01 << 30) #define S3C2410_GPG15_EINT23 (0x02 << 30) #define S3C2410_GPG15_nYPON (0x03 << 30) #define S3C2443_GPG15_CF_PWR (0x03 << 30) @@ -908,61 +719,39 @@ #define S3C2410_GPHUP S3C2410_GPIOREG(0x78) #define S3C2410_GPH0 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0) -#define S3C2410_GPH0_INP (0x00 << 0) -#define S3C2410_GPH0_OUTP (0x01 << 0) #define S3C2410_GPH0_nCTS0 (0x02 << 0) #define S3C2410_GPH1 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1) -#define S3C2410_GPH1_INP (0x00 << 2) -#define S3C2410_GPH1_OUTP (0x01 << 2) #define S3C2410_GPH1_nRTS0 (0x02 << 2) #define S3C2410_GPH2 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2) -#define S3C2410_GPH2_INP (0x00 << 4) -#define S3C2410_GPH2_OUTP (0x01 << 4) #define S3C2410_GPH2_TXD0 (0x02 << 4) #define S3C2410_GPH3 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3) -#define S3C2410_GPH3_INP (0x00 << 6) -#define S3C2410_GPH3_OUTP (0x01 << 6) #define S3C2410_GPH3_RXD0 (0x02 << 6) #define S3C2410_GPH4 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4) -#define S3C2410_GPH4_INP (0x00 << 8) -#define S3C2410_GPH4_OUTP (0x01 << 8) #define S3C2410_GPH4_TXD1 (0x02 << 8) #define S3C2410_GPH5 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5) -#define S3C2410_GPH5_INP (0x00 << 10) -#define S3C2410_GPH5_OUTP (0x01 << 10) #define S3C2410_GPH5_RXD1 (0x02 << 10) #define S3C2410_GPH6 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6) -#define S3C2410_GPH6_INP (0x00 << 12) -#define S3C2410_GPH6_OUTP (0x01 << 12) #define S3C2410_GPH6_TXD2 (0x02 << 12) #define S3C2410_GPH6_nRTS1 (0x03 << 12) #define S3C2410_GPH7 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7) -#define S3C2410_GPH7_INP (0x00 << 14) -#define S3C2410_GPH7_OUTP (0x01 << 14) #define S3C2410_GPH7_RXD2 (0x02 << 14) #define S3C2410_GPH7_nCTS1 (0x03 << 14) #define S3C2410_GPH8 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8) -#define S3C2410_GPH8_INP (0x00 << 16) -#define S3C2410_GPH8_OUTP (0x01 << 16) #define S3C2410_GPH8_UCLK (0x02 << 16) #define S3C2410_GPH9 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9) -#define S3C2410_GPH9_INP (0x00 << 18) -#define S3C2410_GPH9_OUTP (0x01 << 18) #define S3C2410_GPH9_CLKOUT0 (0x02 << 18) #define S3C2442_GPH9_nSPICS0 (0x03 << 18) #define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10) -#define S3C2410_GPH10_INP (0x00 << 20) -#define S3C2410_GPH10_OUTP (0x01 << 20) #define S3C2410_GPH10_CLKOUT1 (0x02 << 20) /* The S3C2412 and S3C2413 move the GPJ register set to after -- cgit v1.2.2 From 75cbcff3729fe2568dff38d16d6494f8fb7f59fe Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sun, 17 May 2009 22:44:33 +0100 Subject: [ARM] S3C24XX: GPIO: Add S3C64XX style GPIO numbering Move the new style of GPIO numbering by using a single macro for each GPIO bank. This means S3C2410_GPA0 becomes S3C2410_GPA(0), and so on. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/gpio-nrs.h | 49 +++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) (limited to 'arch/arm/mach-s3c2410/include') diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h index ce1ec69806a1..5213e453df1c 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h @@ -11,6 +11,9 @@ * published by the Free Software Foundation. */ +#ifndef __MACH_GPIONRS_H +#define __MACH_GPIONRS_H + #define S3C2410_GPIONO(bank,offset) ((bank) + (offset)) #define S3C2410_GPIO_BANKA (32*0) @@ -21,3 +24,49 @@ #define S3C2410_GPIO_BANKF (32*5) #define S3C2410_GPIO_BANKG (32*6) #define S3C2410_GPIO_BANKH (32*7) + +/* GPIO bank sizes */ +#define S3C2410_GPIO_A_NR (32) +#define S3C2410_GPIO_B_NR (32) +#define S3C2410_GPIO_C_NR (32) +#define S3C2410_GPIO_D_NR (32) +#define S3C2410_GPIO_E_NR (32) +#define S3C2410_GPIO_F_NR (32) +#define S3C2410_GPIO_G_NR (32) +#define S3C2410_GPIO_H_NR (32) + +#if CONFIG_S3C_GPIO_SPACE != 0 +#error CONFIG_S3C_GPIO_SPACE cannot be zero at the moment +#endif + +#define S3C2410_GPIO_NEXT(__gpio) \ + ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0) + +#ifndef __ASSEMBLY__ + +enum s3c_gpio_number { + S3C2410_GPIO_A_START = 0, + S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A), + S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B), + S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C), + S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D), + S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E), + S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F), + S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G), +}; + +#endif /* __ASSEMBLY__ */ + +/* S3C2410 GPIO number definitions. */ + +#define S3C2410_GPA(_nr) (S3C2410_GPIO_A_START + (_nr)) +#define S3C2410_GPB(_nr) (S3C2410_GPIO_B_START + (_nr)) +#define S3C2410_GPC(_nr) (S3C2410_GPIO_C_START + (_nr)) +#define S3C2410_GPD(_nr) (S3C2410_GPIO_D_START + (_nr)) +#define S3C2410_GPE(_nr) (S3C2410_GPIO_E_START + (_nr)) +#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr)) +#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr)) +#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr)) + +#endif /* __MACH_GPIONRS_H */ + -- cgit v1.2.2 From 070276d5d049f385763dee19112bea08f56c9a0d Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sun, 17 May 2009 22:32:23 +0100 Subject: [ARM] S3C24XX: GPIO: Change to macros for GPIO numbering Prepare to remove the large number of S3C2410_GPxn defines by moving to S3C2410_GPx(n) in arch/arm. The following perl was used to change the files: perl -pi~ -e 's/S3C2410_GP([A-Z])([0-9]+)([^_^0-9])/S3C2410_GP\1\(\2\)\3/g' Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/gpio-core.h | 2 +- arch/arm/mach-s3c2410/include/mach/gpio-fns.h | 8 +- arch/arm/mach-s3c2410/include/mach/gpio-nrs.h | 21 +++++ arch/arm/mach-s3c2410/include/mach/regs-gpio.h | 122 ------------------------- 4 files changed, 26 insertions(+), 127 deletions(-) (limited to 'arch/arm/mach-s3c2410/include') diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-core.h b/arch/arm/mach-s3c2410/include/mach/gpio-core.h index 6c9fbb99ef14..8fe192081d3a 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio-core.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio-core.h @@ -24,7 +24,7 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin) { struct s3c_gpio_chip *chip; - if (pin > S3C2410_GPG10) + if (pin > S3C2410_GPG(10)) return NULL; chip = &s3c24xx_gpios[pin/32]; diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h index b4f39558beda..801dff13858d 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h @@ -30,8 +30,8 @@ * set the configuration of the given pin to the value passed. * * eg: - * s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0); - * s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1); + * s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0); + * s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1); */ extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function); @@ -80,8 +80,8 @@ extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on, * * eg; * - * s3c2410_gpio_pullup(S3C2410_GPB0, 0); - * s3c2410_gpio_pullup(S3C2410_GPE8, 0); + * s3c2410_gpio_pullup(S3C2410_GPB(0), 0); + * s3c2410_gpio_pullup(S3C2410_GPE(8), 0); */ extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to); diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h index 5213e453df1c..2edbb9c88ab3 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h @@ -68,5 +68,26 @@ enum s3c_gpio_number { #define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr)) #define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr)) +/* compatibility until drivers can be modified */ + +#define S3C2410_GPA0 S3C2410_GPA(0) +#define S3C2410_GPA1 S3C2410_GPA(1) +#define S3C2410_GPA3 S3C2410_GPA(3) +#define S3C2410_GPA7 S3C2410_GPA(7) + +#define S3C2410_GPE0 S3C2410_GPE(0) +#define S3C2410_GPE1 S3C2410_GPE(1) +#define S3C2410_GPE2 S3C2410_GPE(2) +#define S3C2410_GPE3 S3C2410_GPE(3) +#define S3C2410_GPE4 S3C2410_GPE(4) +#define S3C2410_GPE5 S3C2410_GPE(5) +#define S3C2410_GPE6 S3C2410_GPE(6) +#define S3C2410_GPE7 S3C2410_GPE(7) +#define S3C2410_GPE8 S3C2410_GPE(8) +#define S3C2410_GPE9 S3C2410_GPE(9) +#define S3C2410_GPE10 S3C2410_GPE(10) + +#define S3C2410_GPH10 S3C2410_GPH(10) + #endif /* __MACH_GPIONRS_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h index 90cefebd2937..b278d0c45ccf 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h @@ -69,81 +69,58 @@ #define S3C2400_GPACON S3C2410_GPIOREG(0x00) #define S3C2400_GPADAT S3C2410_GPIOREG(0x04) -#define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0) #define S3C2410_GPA0_ADDR0 (1<<0) -#define S3C2410_GPA1 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1) #define S3C2410_GPA1_ADDR16 (1<<1) -#define S3C2410_GPA2 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2) #define S3C2410_GPA2_ADDR17 (1<<2) -#define S3C2410_GPA3 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3) #define S3C2410_GPA3_ADDR18 (1<<3) -#define S3C2410_GPA4 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4) #define S3C2410_GPA4_ADDR19 (1<<4) -#define S3C2410_GPA5 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5) #define S3C2410_GPA5_ADDR20 (1<<5) -#define S3C2410_GPA6 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6) #define S3C2410_GPA6_ADDR21 (1<<6) -#define S3C2410_GPA7 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7) #define S3C2410_GPA7_ADDR22 (1<<7) -#define S3C2410_GPA8 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8) #define S3C2410_GPA8_ADDR23 (1<<8) -#define S3C2410_GPA9 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9) #define S3C2410_GPA9_ADDR24 (1<<9) -#define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10) #define S3C2410_GPA10_ADDR25 (1<<10) #define S3C2400_GPA10_SCKE (1<<10) -#define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11) #define S3C2410_GPA11_ADDR26 (1<<11) #define S3C2400_GPA11_nCAS0 (1<<11) -#define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12) #define S3C2410_GPA12_nGCS1 (1<<12) #define S3C2400_GPA12_nCAS1 (1<<12) -#define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13) #define S3C2410_GPA13_nGCS2 (1<<13) #define S3C2400_GPA13_nGCS1 (1<<13) -#define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14) #define S3C2410_GPA14_nGCS3 (1<<14) #define S3C2400_GPA14_nGCS2 (1<<14) -#define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15) #define S3C2410_GPA15_nGCS4 (1<<15) #define S3C2400_GPA15_nGCS3 (1<<15) -#define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16) #define S3C2410_GPA16_nGCS5 (1<<16) #define S3C2400_GPA16_nGCS4 (1<<16) -#define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17) #define S3C2410_GPA17_CLE (1<<17) #define S3C2400_GPA17_nGCS5 (1<<17) -#define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18) #define S3C2410_GPA18_ALE (1<<18) -#define S3C2410_GPA19 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19) #define S3C2410_GPA19_nFWE (1<<19) -#define S3C2410_GPA20 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20) #define S3C2410_GPA20_nFRE (1<<20) -#define S3C2410_GPA21 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21) #define S3C2410_GPA21_nRSTOUT (1<<21) -#define S3C2410_GPA22 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22) #define S3C2410_GPA22_nFCE (1<<22) /* 0x08 and 0x0c are reserved on S3C2410 */ @@ -171,85 +148,69 @@ /* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ -#define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0) #define S3C2410_GPB0_TOUT0 (0x02 << 0) #define S3C2400_GPB0_DATA16 (0x02 << 0) -#define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1) #define S3C2410_GPB1_TOUT1 (0x02 << 2) #define S3C2400_GPB1_DATA17 (0x02 << 2) -#define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2) #define S3C2410_GPB2_TOUT2 (0x02 << 4) #define S3C2400_GPB2_DATA18 (0x02 << 4) #define S3C2400_GPB2_TCLK1 (0x03 << 4) -#define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3) #define S3C2410_GPB3_TOUT3 (0x02 << 6) #define S3C2400_GPB3_DATA19 (0x02 << 6) #define S3C2400_GPB3_TXD1 (0x03 << 6) -#define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4) #define S3C2410_GPB4_TCLK0 (0x02 << 8) #define S3C2400_GPB4_DATA20 (0x02 << 8) #define S3C2410_GPB4_MASK (0x03 << 8) #define S3C2400_GPB4_RXD1 (0x03 << 8) #define S3C2400_GPB4_MASK (0x03 << 8) -#define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5) #define S3C2410_GPB5_nXBACK (0x02 << 10) #define S3C2443_GPB5_XBACK (0x03 << 10) #define S3C2400_GPB5_DATA21 (0x02 << 10) #define S3C2400_GPB5_nCTS1 (0x03 << 10) -#define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6) #define S3C2410_GPB6_nXBREQ (0x02 << 12) #define S3C2443_GPB6_XBREQ (0x03 << 12) #define S3C2400_GPB6_DATA22 (0x02 << 12) #define S3C2400_GPB6_nRTS1 (0x03 << 12) -#define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7) #define S3C2410_GPB7_nXDACK1 (0x02 << 14) #define S3C2443_GPB7_XDACK1 (0x03 << 14) #define S3C2400_GPB7_DATA23 (0x02 << 14) -#define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8) #define S3C2410_GPB8_nXDREQ1 (0x02 << 16) #define S3C2400_GPB8_DATA24 (0x02 << 16) -#define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9) #define S3C2410_GPB9_nXDACK0 (0x02 << 18) #define S3C2443_GPB9_XDACK0 (0x03 << 18) #define S3C2400_GPB9_DATA25 (0x02 << 18) #define S3C2400_GPB9_I2SSDI (0x03 << 18) -#define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10) #define S3C2410_GPB10_nXDRE0 (0x02 << 20) #define S3C2443_GPB10_XDREQ0 (0x03 << 20) #define S3C2400_GPB10_DATA26 (0x02 << 20) #define S3C2400_GPB10_nSS (0x03 << 20) -#define S3C2400_GPB11 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 11) #define S3C2400_GPB11_INP (0x00 << 22) #define S3C2400_GPB11_OUTP (0x01 << 22) #define S3C2400_GPB11_DATA27 (0x02 << 22) -#define S3C2400_GPB12 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 12) #define S3C2400_GPB12_INP (0x00 << 24) #define S3C2400_GPB12_OUTP (0x01 << 24) #define S3C2400_GPB12_DATA28 (0x02 << 24) -#define S3C2400_GPB13 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 13) #define S3C2400_GPB13_INP (0x00 << 26) #define S3C2400_GPB13_OUTP (0x01 << 26) #define S3C2400_GPB13_DATA29 (0x02 << 26) -#define S3C2400_GPB14 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 14) #define S3C2400_GPB14_INP (0x00 << 28) #define S3C2400_GPB14_OUTP (0x01 << 28) #define S3C2400_GPB14_DATA30 (0x02 << 28) -#define S3C2400_GPB15 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 15) #define S3C2400_GPB15_INP (0x00 << 30) #define S3C2400_GPB15_OUTP (0x01 << 30) #define S3C2400_GPB15_DATA31 (0x02 << 30) @@ -270,67 +231,51 @@ #define S3C2400_GPCDAT S3C2410_GPIOREG(0x18) #define S3C2400_GPCUP S3C2410_GPIOREG(0x1C) -#define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0) #define S3C2410_GPC0_LEND (0x02 << 0) #define S3C2400_GPC0_VD0 (0x02 << 0) -#define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1) #define S3C2410_GPC1_VCLK (0x02 << 2) #define S3C2400_GPC1_VD1 (0x02 << 2) -#define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2) #define S3C2410_GPC2_VLINE (0x02 << 4) #define S3C2400_GPC2_VD2 (0x02 << 4) -#define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3) #define S3C2410_GPC3_VFRAME (0x02 << 6) #define S3C2400_GPC3_VD3 (0x02 << 6) -#define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4) #define S3C2410_GPC4_VM (0x02 << 8) #define S3C2400_GPC4_VD4 (0x02 << 8) -#define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5) #define S3C2410_GPC5_LCDVF0 (0x02 << 10) #define S3C2400_GPC5_VD5 (0x02 << 10) -#define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6) #define S3C2410_GPC6_LCDVF1 (0x02 << 12) #define S3C2400_GPC6_VD6 (0x02 << 12) -#define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7) #define S3C2410_GPC7_LCDVF2 (0x02 << 14) #define S3C2400_GPC7_VD7 (0x02 << 14) -#define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8) #define S3C2410_GPC8_VD0 (0x02 << 16) #define S3C2400_GPC8_VD8 (0x02 << 16) -#define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9) #define S3C2410_GPC9_VD1 (0x02 << 18) #define S3C2400_GPC9_VD9 (0x02 << 18) -#define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10) #define S3C2410_GPC10_VD2 (0x02 << 20) #define S3C2400_GPC10_VD10 (0x02 << 20) -#define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11) #define S3C2410_GPC11_VD3 (0x02 << 22) #define S3C2400_GPC11_VD11 (0x02 << 22) -#define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12) #define S3C2410_GPC12_VD4 (0x02 << 24) #define S3C2400_GPC12_VD12 (0x02 << 24) -#define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13) #define S3C2410_GPC13_VD5 (0x02 << 26) #define S3C2400_GPC13_VD13 (0x02 << 26) -#define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14) #define S3C2410_GPC14_VD6 (0x02 << 28) #define S3C2400_GPC14_VD14 (0x02 << 28) -#define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15) #define S3C2410_GPC15_VD7 (0x02 << 30) #define S3C2400_GPC15_VD15 (0x02 << 30) @@ -355,67 +300,51 @@ #define S3C2400_GPDDAT S3C2410_GPIOREG(0x24) #define S3C2400_GPDUP S3C2410_GPIOREG(0x28) -#define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0) #define S3C2410_GPD0_VD8 (0x02 << 0) #define S3C2400_GPD0_VFRAME (0x02 << 0) #define S3C2442_GPD0_nSPICS1 (0x03 << 0) -#define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1) #define S3C2410_GPD1_VD9 (0x02 << 2) #define S3C2400_GPD1_VM (0x02 << 2) #define S3C2442_GPD1_SPICLK1 (0x03 << 2) -#define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2) #define S3C2410_GPD2_VD10 (0x02 << 4) #define S3C2400_GPD2_VLINE (0x02 << 4) -#define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3) #define S3C2410_GPD3_VD11 (0x02 << 6) #define S3C2400_GPD3_VCLK (0x02 << 6) -#define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4) #define S3C2410_GPD4_VD12 (0x02 << 8) #define S3C2400_GPD4_LEND (0x02 << 8) -#define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5) #define S3C2410_GPD5_VD13 (0x02 << 10) #define S3C2400_GPD5_TOUT0 (0x02 << 10) -#define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6) #define S3C2410_GPD6_VD14 (0x02 << 12) #define S3C2400_GPD6_TOUT1 (0x02 << 12) -#define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7) #define S3C2410_GPD7_VD15 (0x02 << 14) #define S3C2400_GPD7_TOUT2 (0x02 << 14) -#define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8) #define S3C2410_GPD8_VD16 (0x02 << 16) #define S3C2400_GPD8_TOUT3 (0x02 << 16) -#define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9) #define S3C2410_GPD9_VD17 (0x02 << 18) #define S3C2400_GPD9_TCLK0 (0x02 << 18) #define S3C2410_GPD9_MASK (0x03 << 18) -#define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10) #define S3C2410_GPD10_VD18 (0x02 << 20) #define S3C2400_GPD10_nWAIT (0x02 << 20) -#define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11) #define S3C2410_GPD11_VD19 (0x02 << 22) -#define S3C2410_GPD12 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12) #define S3C2410_GPD12_VD20 (0x02 << 24) -#define S3C2410_GPD13 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13) #define S3C2410_GPD13_VD21 (0x02 << 26) -#define S3C2410_GPD14 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14) #define S3C2410_GPD14_VD22 (0x02 << 28) #define S3C2410_GPD14_nSS1 (0x03 << 28) -#define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15) #define S3C2410_GPD15_VD23 (0x02 << 30) #define S3C2410_GPD15_nSS0 (0x03 << 30) @@ -441,26 +370,22 @@ #define S3C2400_GPEDAT S3C2410_GPIOREG(0x30) #define S3C2400_GPEUP S3C2410_GPIOREG(0x34) -#define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0) #define S3C2410_GPE0_I2SLRCK (0x02 << 0) #define S3C2443_GPE0_AC_nRESET (0x03 << 0) #define S3C2400_GPE0_EINT0 (0x02 << 0) #define S3C2410_GPE0_MASK (0x03 << 0) -#define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1) #define S3C2410_GPE1_I2SSCLK (0x02 << 2) #define S3C2443_GPE1_AC_SYNC (0x03 << 2) #define S3C2400_GPE1_EINT1 (0x02 << 2) #define S3C2400_GPE1_nSS (0x03 << 2) #define S3C2410_GPE1_MASK (0x03 << 2) -#define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2) #define S3C2410_GPE2_CDCLK (0x02 << 4) #define S3C2443_GPE2_AC_BITCLK (0x03 << 4) #define S3C2400_GPE2_EINT2 (0x02 << 4) #define S3C2400_GPE2_I2SSDI (0x03 << 4) -#define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3) #define S3C2410_GPE3_I2SSDI (0x02 << 6) #define S3C2443_GPE3_AC_SDI (0x03 << 6) #define S3C2400_GPE3_EINT3 (0x02 << 6) @@ -468,7 +393,6 @@ #define S3C2410_GPE3_nSS0 (0x03 << 6) #define S3C2410_GPE3_MASK (0x03 << 6) -#define S3C2410_GPE4 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4) #define S3C2410_GPE4_I2SSDO (0x02 << 8) #define S3C2443_GPE4_AC_SDO (0x03 << 8) #define S3C2400_GPE4_EINT4 (0x02 << 8) @@ -476,59 +400,48 @@ #define S3C2410_GPE4_I2SSDI (0x03 << 8) #define S3C2410_GPE4_MASK (0x03 << 8) -#define S3C2410_GPE5 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5) #define S3C2410_GPE5_SDCLK (0x02 << 10) #define S3C2443_GPE5_SD1_CLK (0x02 << 10) #define S3C2400_GPE5_EINT5 (0x02 << 10) #define S3C2400_GPE5_TCLK1 (0x03 << 10) -#define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6) #define S3C2410_GPE6_SDCMD (0x02 << 12) #define S3C2443_GPE6_SD1_CMD (0x02 << 12) #define S3C2443_GPE6_AC_BITCLK (0x03 << 12) #define S3C2400_GPE6_EINT6 (0x02 << 12) -#define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7) #define S3C2410_GPE7_SDDAT0 (0x02 << 14) #define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) #define S3C2443_GPE7_AC_SDI (0x03 << 14) #define S3C2400_GPE7_EINT7 (0x02 << 14) -#define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8) #define S3C2410_GPE8_SDDAT1 (0x02 << 16) #define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) #define S3C2443_GPE8_AC_SDO (0x03 << 16) #define S3C2400_GPE8_nXDACK0 (0x02 << 16) -#define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9) #define S3C2410_GPE9_SDDAT2 (0x02 << 18) #define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) #define S3C2443_GPE9_AC_SYNC (0x03 << 18) #define S3C2400_GPE9_nXDACK1 (0x02 << 18) #define S3C2400_GPE9_nXBACK (0x03 << 18) -#define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10) #define S3C2410_GPE10_SDDAT3 (0x02 << 20) #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) #define S3C2443_GPE10_AC_nRESET (0x03 << 20) #define S3C2400_GPE10_nXDREQ0 (0x02 << 20) -#define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11) #define S3C2410_GPE11_SPIMISO0 (0x02 << 22) #define S3C2400_GPE11_nXDREQ1 (0x02 << 22) #define S3C2400_GPE11_nXBREQ (0x03 << 22) -#define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12) #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) -#define S3C2410_GPE13 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13) #define S3C2410_GPE13_SPICLK0 (0x02 << 26) -#define S3C2410_GPE14 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14) #define S3C2410_GPE14_IICSCL (0x02 << 28) #define S3C2410_GPE14_MASK (0x03 << 28) -#define S3C2410_GPE15 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15) #define S3C2410_GPE15_IICSDA (0x02 << 30) #define S3C2410_GPE15_MASK (0x03 << 30) @@ -564,39 +477,31 @@ #define S3C2400_GPFDAT S3C2410_GPIOREG(0x3C) #define S3C2400_GPFUP S3C2410_GPIOREG(0x40) -#define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0) #define S3C2410_GPF0_EINT0 (0x02 << 0) #define S3C2400_GPF0_RXD0 (0x02 << 0) -#define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1) #define S3C2410_GPF1_EINT1 (0x02 << 2) #define S3C2400_GPF1_RXD1 (0x02 << 2) #define S3C2400_GPF1_IICSDA (0x03 << 2) -#define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2) #define S3C2410_GPF2_EINT2 (0x02 << 4) #define S3C2400_GPF2_TXD0 (0x02 << 4) -#define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3) #define S3C2410_GPF3_EINT3 (0x02 << 6) #define S3C2400_GPF3_TXD1 (0x02 << 6) #define S3C2400_GPF3_IICSCL (0x03 << 6) -#define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4) #define S3C2410_GPF4_EINT4 (0x02 << 8) #define S3C2400_GPF4_nRTS0 (0x02 << 8) #define S3C2400_GPF4_nXBACK (0x03 << 8) -#define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5) #define S3C2410_GPF5_EINT5 (0x02 << 10) #define S3C2400_GPF5_nCTS0 (0x02 << 10) #define S3C2400_GPF5_nXBREQ (0x03 << 10) -#define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6) #define S3C2410_GPF6_EINT6 (0x02 << 12) #define S3C2400_GPF6_CLKOUT (0x02 << 12) -#define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7) #define S3C2410_GPF7_EINT7 (0x02 << 14) #define S3C2410_GPF_PUPDIS(x) (1<<(x)) @@ -621,85 +526,69 @@ #define S3C2400_GPGDAT S3C2410_GPIOREG(0x48) #define S3C2400_GPGUP S3C2410_GPIOREG(0x4C) -#define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0) #define S3C2410_GPG0_EINT8 (0x02 << 0) #define S3C2400_GPG0_I2SLRCK (0x02 << 0) -#define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1) #define S3C2410_GPG1_EINT9 (0x02 << 2) #define S3C2400_GPG1_I2SSCLK (0x02 << 2) -#define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2) #define S3C2410_GPG2_EINT10 (0x02 << 4) #define S3C2410_GPG2_nSS0 (0x03 << 4) #define S3C2400_GPG2_CDCLK (0x02 << 4) -#define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3) #define S3C2410_GPG3_EINT11 (0x02 << 6) #define S3C2410_GPG3_nSS1 (0x03 << 6) #define S3C2400_GPG3_I2SSDO (0x02 << 6) #define S3C2400_GPG3_I2SSDI (0x03 << 6) -#define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4) #define S3C2410_GPG4_EINT12 (0x02 << 8) #define S3C2400_GPG4_MMCCLK (0x02 << 8) #define S3C2400_GPG4_I2SSDI (0x03 << 8) #define S3C2410_GPG4_LCDPWREN (0x03 << 8) #define S3C2443_GPG4_LCDPWRDN (0x03 << 8) -#define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5) #define S3C2410_GPG5_EINT13 (0x02 << 10) #define S3C2400_GPG5_MMCCMD (0x02 << 10) #define S3C2400_GPG5_IICSDA (0x03 << 10) #define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ -#define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6) #define S3C2410_GPG6_EINT14 (0x02 << 12) #define S3C2400_GPG6_MMCDAT (0x02 << 12) #define S3C2400_GPG6_IICSCL (0x03 << 12) #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) -#define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7) #define S3C2410_GPG7_EINT15 (0x02 << 14) #define S3C2410_GPG7_SPICLK1 (0x03 << 14) #define S3C2400_GPG7_SPIMISO (0x02 << 14) #define S3C2400_GPG7_IICSDA (0x03 << 14) -#define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8) #define S3C2410_GPG8_EINT16 (0x02 << 16) #define S3C2400_GPG8_SPIMOSI (0x02 << 16) #define S3C2400_GPG8_IICSCL (0x03 << 16) -#define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9) #define S3C2410_GPG9_EINT17 (0x02 << 18) #define S3C2400_GPG9_SPICLK (0x02 << 18) #define S3C2400_GPG9_MMCCLK (0x03 << 18) -#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10) #define S3C2410_GPG10_EINT18 (0x02 << 20) -#define S3C2410_GPG11 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11) #define S3C2410_GPG11_EINT19 (0x02 << 22) #define S3C2410_GPG11_TCLK1 (0x03 << 22) #define S3C2443_GPG11_CF_nIREQ (0x03 << 22) -#define S3C2410_GPG12 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12) #define S3C2410_GPG12_EINT20 (0x02 << 24) #define S3C2410_GPG12_XMON (0x03 << 24) #define S3C2442_GPG12_nSPICS0 (0x03 << 24) #define S3C2443_GPG12_nINPACK (0x03 << 24) -#define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13) #define S3C2410_GPG13_EINT21 (0x02 << 26) #define S3C2410_GPG13_nXPON (0x03 << 26) #define S3C2443_GPG13_CF_nREG (0x03 << 26) -#define S3C2410_GPG14 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14) #define S3C2410_GPG14_EINT22 (0x02 << 28) #define S3C2410_GPG14_YMON (0x03 << 28) #define S3C2443_GPG14_CF_RESET (0x03 << 28) -#define S3C2410_GPG15 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15) #define S3C2410_GPG15_EINT23 (0x02 << 30) #define S3C2410_GPG15_nYPON (0x03 << 30) #define S3C2443_GPG15_CF_PWR (0x03 << 30) @@ -718,40 +607,29 @@ #define S3C2410_GPHDAT S3C2410_GPIOREG(0x74) #define S3C2410_GPHUP S3C2410_GPIOREG(0x78) -#define S3C2410_GPH0 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0) #define S3C2410_GPH0_nCTS0 (0x02 << 0) -#define S3C2410_GPH1 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1) #define S3C2410_GPH1_nRTS0 (0x02 << 2) -#define S3C2410_GPH2 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2) #define S3C2410_GPH2_TXD0 (0x02 << 4) -#define S3C2410_GPH3 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3) #define S3C2410_GPH3_RXD0 (0x02 << 6) -#define S3C2410_GPH4 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4) #define S3C2410_GPH4_TXD1 (0x02 << 8) -#define S3C2410_GPH5 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5) #define S3C2410_GPH5_RXD1 (0x02 << 10) -#define S3C2410_GPH6 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6) #define S3C2410_GPH6_TXD2 (0x02 << 12) #define S3C2410_GPH6_nRTS1 (0x03 << 12) -#define S3C2410_GPH7 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7) #define S3C2410_GPH7_RXD2 (0x02 << 14) #define S3C2410_GPH7_nCTS1 (0x03 << 14) -#define S3C2410_GPH8 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8) #define S3C2410_GPH8_UCLK (0x02 << 16) -#define S3C2410_GPH9 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9) #define S3C2410_GPH9_CLKOUT0 (0x02 << 18) #define S3C2442_GPH9_nSPICS0 (0x03 << 18) -#define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10) #define S3C2410_GPH10_CLKOUT1 (0x02 << 20) /* The S3C2412 and S3C2413 move the GPJ register set to after -- cgit v1.2.2