From eebdb0c1e1d63532399f7cbb65ade5969d63df06 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 14 Mar 2013 20:31:38 -0700 Subject: ARM: msm: Rework timer binding to be more general The msm timer binding I wrote is bad. First off, the clock frequency in the binding for the dgt is wrong. Software divides down the input rate by 4 to achieve the rate listed in the binding. We also treat each individual timer as a separate hardware component, when in reality there is one timer block (that may be duplicated per cpu) with multiple timers within it. Depending on the version of the hardware there can be one or two general purpose timers, status and divider control registers, and an entirely different register layout. In the next patch we'll need to know about the different register layouts so that we can properly check the status register after clearing the count. The current binding makes this complicated because the general purpose timer's reg property doesn't indicate where that status register is, and in fact it is beyond the size of the reg property. Clean all this up by just having one node for the timer hardware, and describe all the interrupts and clock frequencies supported while having one reg property that covers the entire timer register region. We'll use the compatible field in the future to determine different register layouts and if we should read the status registers, etc. Signed-off-by: Stephen Boyd Signed-off-by: David Brown --- arch/arm/mach-msm/timer.c | 79 ++++++++++++++++++++--------------------------- 1 file changed, 33 insertions(+), 46 deletions(-) (limited to 'arch/arm/mach-msm') diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index 2969027f02fa..165e33b9b1ee 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -36,6 +36,7 @@ #define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1) #define TIMER_ENABLE_EN BIT(0) #define TIMER_CLEAR 0x000C +#define DGT_CLK_CTL 0x10 #define DGT_CLK_CTL_DIV_4 0x3 #define GPT_HZ 32768 @@ -214,13 +215,9 @@ err: } #ifdef CONFIG_OF -static const struct of_device_id msm_dgt_match[] __initconst = { - { .compatible = "qcom,msm-dgt" }, - { }, -}; - -static const struct of_device_id msm_gpt_match[] __initconst = { - { .compatible = "qcom,msm-gpt" }, +static const struct of_device_id msm_timer_match[] __initconst = { + { .compatible = "qcom,kpss-timer" }, + { .compatible = "qcom,scss-timer" }, { }, }; @@ -231,33 +228,29 @@ void __init msm_dt_timer_init(void) int irq; struct resource res; u32 percpu_offset; - void __iomem *dgt_clk_ctl; + void __iomem *base; + void __iomem *cpu0_base; - np = of_find_matching_node(NULL, msm_gpt_match); + np = of_find_matching_node(NULL, msm_timer_match); if (!np) { - pr_err("Can't find GPT DT node\n"); + pr_err("Can't find msm timer DT node\n"); return; } - event_base = of_iomap(np, 0); - if (!event_base) { + base = of_iomap(np, 0); + if (!base) { pr_err("Failed to map event base\n"); return; } - irq = irq_of_parse_and_map(np, 0); + /* We use GPT0 for the clockevent */ + irq = irq_of_parse_and_map(np, 1); if (irq <= 0) { pr_err("Can't get irq\n"); return; } - of_node_put(np); - - np = of_find_matching_node(NULL, msm_dgt_match); - if (!np) { - pr_err("Can't find DGT DT node\n"); - return; - } + /* We use CPU0's DGT for the clocksource */ if (of_property_read_u32(np, "cpu-offset", &percpu_offset)) percpu_offset = 0; @@ -266,45 +259,39 @@ void __init msm_dt_timer_init(void) return; } - source_base = ioremap(res.start + percpu_offset, resource_size(&res)); - if (!source_base) { + cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res)); + if (!cpu0_base) { pr_err("Failed to map source base\n"); return; } - if (!of_address_to_resource(np, 1, &res)) { - dgt_clk_ctl = ioremap(res.start + percpu_offset, - resource_size(&res)); - if (!dgt_clk_ctl) { - pr_err("Failed to map DGT control base\n"); - return; - } - writel_relaxed(DGT_CLK_CTL_DIV_4, dgt_clk_ctl); - iounmap(dgt_clk_ctl); - } - if (of_property_read_u32(np, "clock-frequency", &freq)) { pr_err("Unknown frequency\n"); return; } of_node_put(np); + event_base = base + 0x4; + source_base = cpu0_base + 0x24; + freq /= 4; + writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL); + msm_timer_init(freq, 32, irq, !!percpu_offset); } #endif -static int __init msm_timer_map(phys_addr_t event, phys_addr_t source) +static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source) { - event_base = ioremap(event, SZ_64); - if (!event_base) { - pr_err("Failed to map event base\n"); - return 1; - } - source_base = ioremap(source, SZ_64); - if (!source_base) { - pr_err("Failed to map source base\n"); - return 1; + void __iomem *base; + + base = ioremap(addr, SZ_256); + if (!base) { + pr_err("Failed to map timer base\n"); + return -ENOMEM; } + event_base = base + event; + source_base = base + source; + return 0; } @@ -312,7 +299,7 @@ void __init msm7x01_timer_init(void) { struct clocksource *cs = &msm_clocksource; - if (msm_timer_map(0xc0100000, 0xc0100010)) + if (msm_timer_map(0xc0100000, 0x0, 0x10)) return; cs->read = msm_read_timer_count_shift; cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)); @@ -323,14 +310,14 @@ void __init msm7x01_timer_init(void) void __init msm7x30_timer_init(void) { - if (msm_timer_map(0xc0100004, 0xc0100024)) + if (msm_timer_map(0xc0100000, 0x4, 0x24)) return; msm_timer_init(24576000 / 4, 32, 1, false); } void __init qsd8x50_timer_init(void) { - if (msm_timer_map(0xAC100000, 0xAC100010)) + if (msm_timer_map(0xAC100000, 0x0, 0x10)) return; msm_timer_init(19200000 / 4, 32, 7, false); } -- cgit v1.2.2 From e25e3d1fef2c57e49aef64535341c15fe2b29b4a Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 14 Mar 2013 20:31:39 -0700 Subject: ARM: msm: Wait for timer clear to complete Without looping on the status bit, there is no way to guarantee that a clear of the timer has actually completed. This can cause us to enable the timer before the count has cleared and miss a timer interrupt. To simplify this patch, remove the timer register setup done during timer init, since it's duplicate work that is eventually done in the set_next_event() callback. Signed-off-by: Stephen Boyd Signed-off-by: David Brown --- arch/arm/mach-msm/timer.c | 41 +++++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 18 deletions(-) (limited to 'arch/arm/mach-msm') diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index 165e33b9b1ee..b4b0d79476a8 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -30,20 +30,22 @@ #include "common.h" -#define TIMER_MATCH_VAL 0x0000 -#define TIMER_COUNT_VAL 0x0004 -#define TIMER_ENABLE 0x0008 -#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1) -#define TIMER_ENABLE_EN BIT(0) -#define TIMER_CLEAR 0x000C -#define DGT_CLK_CTL 0x10 -#define DGT_CLK_CTL_DIV_4 0x3 +#define TIMER_MATCH_VAL 0x0000 +#define TIMER_COUNT_VAL 0x0004 +#define TIMER_ENABLE 0x0008 +#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1) +#define TIMER_ENABLE_EN BIT(0) +#define TIMER_CLEAR 0x000C +#define DGT_CLK_CTL 0x10 +#define DGT_CLK_CTL_DIV_4 0x3 +#define TIMER_STS_GPT0_CLR_PEND BIT(10) #define GPT_HZ 32768 #define MSM_DGT_SHIFT 5 static void __iomem *event_base; +static void __iomem *sts_base; static irqreturn_t msm_timer_interrupt(int irq, void *dev_id) { @@ -65,6 +67,11 @@ static int msm_timer_set_next_event(unsigned long cycles, writel_relaxed(0, event_base + TIMER_CLEAR); writel_relaxed(cycles, event_base + TIMER_MATCH_VAL); + + if (sts_base) + while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND) + cpu_relax(); + writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE); return 0; } @@ -135,9 +142,6 @@ static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt) if (!smp_processor_id()) return 0; - writel_relaxed(0, event_base + TIMER_ENABLE); - writel_relaxed(0, event_base + TIMER_CLEAR); - writel_relaxed(~0, event_base + TIMER_MATCH_VAL); evt->irq = msm_clockevent.irq; evt->name = "local_timer"; evt->features = msm_clockevent.features; @@ -175,9 +179,6 @@ static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq, struct clocksource *cs = &msm_clocksource; int res; - writel_relaxed(0, event_base + TIMER_ENABLE); - writel_relaxed(0, event_base + TIMER_CLEAR); - writel_relaxed(~0, event_base + TIMER_MATCH_VAL); ce->cpumask = cpumask_of(0); ce->irq = irq; @@ -272,6 +273,7 @@ void __init msm_dt_timer_init(void) of_node_put(np); event_base = base + 0x4; + sts_base = base + 0x88; source_base = cpu0_base + 0x24; freq /= 4; writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL); @@ -280,7 +282,8 @@ void __init msm_dt_timer_init(void) } #endif -static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source) +static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source, + u32 sts) { void __iomem *base; @@ -291,6 +294,8 @@ static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source) } event_base = base + event; source_base = base + source; + if (sts) + sts_base = base + sts; return 0; } @@ -299,7 +304,7 @@ void __init msm7x01_timer_init(void) { struct clocksource *cs = &msm_clocksource; - if (msm_timer_map(0xc0100000, 0x0, 0x10)) + if (msm_timer_map(0xc0100000, 0x0, 0x10, 0x0)) return; cs->read = msm_read_timer_count_shift; cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)); @@ -310,14 +315,14 @@ void __init msm7x01_timer_init(void) void __init msm7x30_timer_init(void) { - if (msm_timer_map(0xc0100000, 0x4, 0x24)) + if (msm_timer_map(0xc0100000, 0x4, 0x24, 0x80)) return; msm_timer_init(24576000 / 4, 32, 1, false); } void __init qsd8x50_timer_init(void) { - if (msm_timer_map(0xAC100000, 0x0, 0x10)) + if (msm_timer_map(0xAC100000, 0x0, 0x10, 0x34)) return; msm_timer_init(19200000 / 4, 32, 7, false); } -- cgit v1.2.2