From ec336b284136610a43c9daac56d66b20d43ddf7b Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 17 Sep 2014 11:11:45 +0800 Subject: ARM: imx: replace cpu type check with ddr type check As the DDR/IO and MMDC setting are different on LPDDR2 and DDR3, we used cpu type to decide how to do these settings in suspend before which is NOT flexible, take i.MX6SL for example, although it has LPDDR2 on EVK board, but users can also use DDR3 on other boards, so it is better to read the DDR type from MMDC then decide how to do related settings. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/mach-imx/common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/mach-imx/common.h') diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 1dabf435c592..23c84e67a56d 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -116,6 +116,7 @@ void imx_anatop_post_resume(void); int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); void imx6q_set_int_mem_clk_lpm(bool enable); void imx6sl_set_wait_clk(bool enter); +int imx_mmdc_get_ddr_type(void); void imx_cpu_die(unsigned int cpu); int imx_cpu_kill(unsigned int cpu); -- cgit v1.2.2 From 4e3fea4a950e3ec22ec8f99a7438aa5ba584263a Mon Sep 17 00:00:00 2001 From: Jingchang Lu Date: Fri, 31 Oct 2014 17:01:13 +0800 Subject: ARM: imx: Add Freescale LS1021A SMP support Freescale LS1021A SoCs deploy two cortex-A7 processors, this adds bring-up support for the secondary core. Signed-off-by: Jingchang Lu Signed-off-by: Shawn Guo --- arch/arm/mach-imx/common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/mach-imx/common.h') diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 23c84e67a56d..fe9a908da3ed 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -158,5 +158,6 @@ static inline void imx_init_l2cache(void) {} #endif extern struct smp_operations imx_smp_ops; +extern struct smp_operations ls1021a_smp_ops; #endif -- cgit v1.2.2