From b756a50f7f47e1dee70921399dcb338e4d3bc183 Mon Sep 17 00:00:00 2001 From: Amit Daniel Kachhap Date: Thu, 8 Mar 2012 02:07:41 -0800 Subject: ARM: EXYNOS: save L2 settings during bootup This patch adds code to save L2 register configuration at boot, and later used to resume L2 before MMU is enabled in suspend and cpuidle resume paths. Signed-off-by: Lorenzo Pieralisi Signed-off-by: Amit Daniel Kachhap Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/common.c | 42 +++++++++++++++++++++++++++++++----------- 1 file changed, 31 insertions(+), 11 deletions(-) (limited to 'arch/arm/mach-exynos/common.c') diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index c59e18871006..9ff38aa08fd0 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -26,10 +26,12 @@ #include #include #include +#include #include #include #include +#include #include #include @@ -441,20 +443,38 @@ core_initcall(exynos4_core_init); #ifdef CONFIG_CACHE_L2X0 static int __init exynos4_l2x0_cache_init(void) { - /* TAG, Data Latency Control: 2cycle */ - __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); + if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) { + l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC; + /* TAG, Data Latency Control: 2 cycles */ + l2x0_saved_regs.tag_latency = 0x110; - if (soc_is_exynos4210()) - __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); - else if (soc_is_exynos4212() || soc_is_exynos4412()) - __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); + if (soc_is_exynos4212() || soc_is_exynos4412()) + l2x0_saved_regs.data_latency = 0x120; + else + l2x0_saved_regs.data_latency = 0x110; + + l2x0_saved_regs.prefetch_ctrl = 0x30000007; + l2x0_saved_regs.pwr_ctrl = + (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN); + + l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); - /* L2X0 Prefetch Control */ - __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL); + __raw_writel(l2x0_saved_regs.tag_latency, + S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); + __raw_writel(l2x0_saved_regs.data_latency, + S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); - /* L2X0 Power Control */ - __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, - S5P_VA_L2CC + L2X0_POWER_CTRL); + /* L2X0 Prefetch Control */ + __raw_writel(l2x0_saved_regs.prefetch_ctrl, + S5P_VA_L2CC + L2X0_PREFETCH_CTRL); + + /* L2X0 Power Control */ + __raw_writel(l2x0_saved_regs.pwr_ctrl, + S5P_VA_L2CC + L2X0_POWER_CTRL); + + clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); + clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs)); + } l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff); -- cgit v1.2.2 From 6cdeddcc8149672d4b888709d063825a80304d09 Mon Sep 17 00:00:00 2001 From: Amit Daniel Kachhap Date: Thu, 8 Mar 2012 02:09:12 -0800 Subject: ARM: EXYNOS: Enable l2 configuration through device tree This patch enables calling generic l2 setup functions if device tree is used. Signed-off-by: Amit Daniel Kachhap Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/common.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-exynos/common.c') diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 9ff38aa08fd0..cb5ad8c1fea8 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -47,6 +47,8 @@ #include #include "common.h" +#define L2_AUX_VAL 0x7C470001 +#define L2_AUX_MASK 0xC200ffff static const char name_exynos4210[] = "EXYNOS4210"; static const char name_exynos4212[] = "EXYNOS4212"; @@ -443,6 +445,14 @@ core_initcall(exynos4_core_init); #ifdef CONFIG_CACHE_L2X0 static int __init exynos4_l2x0_cache_init(void) { + int ret; + ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK); + if (!ret) { + l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); + clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); + return 0; + } + if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) { l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC; /* TAG, Data Latency Control: 2 cycles */ @@ -476,8 +486,7 @@ static int __init exynos4_l2x0_cache_init(void) clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs)); } - l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff); - + l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK); return 0; } -- cgit v1.2.2 From 2bde0b08cae739056d1c136839b67eec0ac0c3a4 Mon Sep 17 00:00:00 2001 From: MyungJoo Ham Date: Thu, 1 Dec 2011 15:12:30 +0900 Subject: ARM: EXYNOS: Add DMC1, allow PPMU access for DMC - Add DMC1 - Enlarge address space for DMC from 4k to 64k so that PPMU registers may be accessed. Signed-off-by: MyungJoo Ham Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/common.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-exynos/common.c') diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index cb5ad8c1fea8..02696ac143bd 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -177,7 +177,12 @@ static struct map_desc exynos4_iodesc[] __initdata = { }, { .virtual = (unsigned long)S5P_VA_DMC0, .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0), - .length = SZ_4K, + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_DMC1, + .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1), + .length = SZ_64K, .type = MT_DEVICE, }, { .virtual = (unsigned long)S3C_VA_USB_HSPHY, -- cgit v1.2.2