From edabd38e1a017e922e3e3b485ee3ddb4df433aa4 Mon Sep 17 00:00:00 2001 From: Saeed Bishara Date: Thu, 6 Aug 2009 15:12:43 +0300 Subject: ARM: add base support for Marvell Dove SoC The Marvell Dove (88AP510) is a high-performance, highly integrated, low power SoC with high-end ARM-compatible processor (known as PJ4), graphics processing unit, high-definition video decoding acceleration hardware, and a broad range of peripherals. Signed-off-by: Lennert Buytenhek Signed-off-by: Saeed Bishara Signed-off-by: Nicolas Pitre --- arch/arm/mach-dove/include/mach/bridge-regs.h | 58 +++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 arch/arm/mach-dove/include/mach/bridge-regs.h (limited to 'arch/arm/mach-dove/include/mach/bridge-regs.h') diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h new file mode 100644 index 000000000000..214a4c31f069 --- /dev/null +++ b/arch/arm/mach-dove/include/mach/bridge-regs.h @@ -0,0 +1,58 @@ +/* + * arch/arm/mach-dove/include/mach/bridge-regs.h + * + * Mbus-L to Mbus Bridge Registers + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_BRIDGE_REGS_H +#define __ASM_ARCH_BRIDGE_REGS_H + +#include + +#define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0000) + +#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) +#define CPU_CTRL_PCIE0_LINK 0x00000001 +#define CPU_RESET 0x00000002 +#define CPU_CTRL_PCIE1_LINK 0x00000008 + +#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) +#define SOFT_RESET_OUT_EN 0x00000004 + +#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) +#define SOFT_RESET 0x00000001 + +#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) +#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) +#define BRIDGE_INT_TIMER0 0x0002 +#define BRIDGE_INT_TIMER1 0x0004 +#define BRIDGE_INT_TIMER1_CLR (~0x0004) + +#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) +#define IRQ_CAUSE_LOW_OFF 0x0000 +#define IRQ_MASK_LOW_OFF 0x0004 +#define FIQ_MASK_LOW_OFF 0x0008 +#define ENDPOINT_MASK_LOW_OFF 0x000c +#define IRQ_CAUSE_HIGH_OFF 0x0010 +#define IRQ_MASK_HIGH_OFF 0x0014 +#define FIQ_MASK_HIGH_OFF 0x0018 +#define ENDPOINT_MASK_HIGH_OFF 0x001c +#define PCIE_INTERRUPT_MASK_OFF 0x0020 + +#define IRQ_MASK_LOW (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF) +#define FIQ_MASK_LOW (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF) +#define ENDPOINT_MASK_LOW (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF) +#define IRQ_MASK_HIGH (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF) +#define FIQ_MASK_HIGH (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF) +#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF) +#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF) + +#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE | 0x011c) + +#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) + +#endif -- cgit v1.2.2