From 60902a2cb12c3c1682ee7a04ad7448ec16dc0c29 Mon Sep 17 00:00:00 2001 From: Sudhakar Rajashekhara Date: Thu, 21 May 2009 07:41:35 -0400 Subject: davinci: EDMA: multiple CCs, channel mapping and API changes - restructure to support multiple channel controllers by using additional struct resources for each CC - interface changes visible to EDMA clients Introduce macros to build IDs from controller and channel number, and to extract them. Modify the edma_alloc_slot function to take an extra argument for the controller. Also update ASoC drivers to use API. ASoC changes Acked-by: Mark Brown - Move queue related mappings to dm.c EDMA in DM355 and DM644x has two transfer controllers while DM646x has four transfer controllers. Moving the queue to tc mapping and queue priority mapping to dm.c will be helpful to probe these mappings from platform device so that the machine_is_* testing will be avoided. - add channel mapping logic Channel mapping logic is introduced in dm646x EDMA. This implies that there is no fixed association for a channel number to a parameter entry number. In other words, using the DMA channel mapping registers (DCHMAPn), a PaRAM entry can be mapped to any channel. While in the case of dm644x and dm355 there is a fixed mapping between the EDMA channel and Param entry number. Signed-off-by: Naresh Medisetty Signed-off-by: Sudhakar Rajashekhara Reviewed-by: David Brownell Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/edma.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h index 24a379239d7f..ba2ebdd058a0 100644 --- a/arch/arm/mach-davinci/include/mach/edma.h +++ b/arch/arm/mach-davinci/include/mach/edma.h @@ -170,6 +170,10 @@ enum sync_dimension { ABSYNC = 1 }; +#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan)) +#define EDMA_CTLR(i) ((i) >> 16) +#define EDMA_CHAN_SLOT(i) ((i) & 0xffff) + #define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ #define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ @@ -180,7 +184,7 @@ int edma_alloc_channel(int channel, void edma_free_channel(unsigned channel); /* alloc/free parameter RAM slots */ -int edma_alloc_slot(int slot); +int edma_alloc_slot(unsigned ctlr, int slot); void edma_free_slot(unsigned slot); /* calls that operate on part of a parameter RAM slot */ @@ -216,9 +220,12 @@ struct edma_soc_info { unsigned n_region; unsigned n_slot; unsigned n_tc; + unsigned n_cc; /* list of channels with no even trigger; terminated by "-1" */ const s8 *noevent; + const s8 (*queue_tc_mapping)[2]; + const s8 (*queue_priority_mapping)[2]; }; #endif -- cgit v1.2.2 From 5fcd294df26e6160f32ea551ef074630b4df728d Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Wed, 3 Jun 2009 12:24:50 -0700 Subject: davinci: remove watchdog from soc_info watchdog info is not needed in soc_info, platform_device can be used directly in core code. Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h index a1f03b606d8f..b21393b24d65 100644 --- a/arch/arm/mach-davinci/include/mach/common.h +++ b/arch/arm/mach-davinci/include/mach/common.h @@ -60,7 +60,6 @@ struct davinci_soc_info { u8 *intc_irq_prios; unsigned long intc_irq_num; struct davinci_timer_info *timer_info; - void __iomem *wdt_base; void __iomem *gpio_base; unsigned gpio_num; unsigned gpio_irq; -- cgit v1.2.2 From fb8fcb891390639d6258c816abb537663495da0c Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Thu, 11 Jun 2009 09:41:05 -0400 Subject: davinci: Adding DM365 SOC Support The patch adds base support for new TI SOC DM365, which s similar to the dm355. Signed-off-by: Sandeep Paulraj Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/cputype.h | 8 +++ arch/arm/mach-davinci/include/mach/dm365.h | 29 ++++++++++ arch/arm/mach-davinci/include/mach/irqs.h | 36 +++++++++++++ arch/arm/mach-davinci/include/mach/mux.h | 81 ++++++++++++++++++++++++++++ arch/arm/mach-davinci/include/mach/psc.h | 18 +++++++ 5 files changed, 172 insertions(+) create mode 100644 arch/arm/mach-davinci/include/mach/dm365.h (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h index d12a5ed2959a..56b92d49e293 100644 --- a/arch/arm/mach-davinci/include/mach/cputype.h +++ b/arch/arm/mach-davinci/include/mach/cputype.h @@ -30,6 +30,7 @@ struct davinci_id { #define DAVINCI_CPU_ID_DM6446 0x64460000 #define DAVINCI_CPU_ID_DM6467 0x64670000 #define DAVINCI_CPU_ID_DM355 0x03550000 +#define DAVINCI_CPU_ID_DM365 0x03650000 #define IS_DAVINCI_CPU(type, id) \ static inline int is_davinci_ ##type(void) \ @@ -40,6 +41,7 @@ static inline int is_davinci_ ##type(void) \ IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446) IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467) IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355) +IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365) #ifdef CONFIG_ARCH_DAVINCI_DM644x #define cpu_is_davinci_dm644x() is_davinci_dm644x() @@ -59,4 +61,10 @@ IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355) #define cpu_is_davinci_dm355() 0 #endif +#ifdef CONFIG_ARCH_DAVINCI_DM365 +#define cpu_is_davinci_dm365() is_davinci_dm365() +#else +#define cpu_is_davinci_dm365() 0 +#endif + #endif diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h new file mode 100644 index 000000000000..09db4343bb4c --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/dm365.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2009 Texas Instruments Incorporated + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __ASM_ARCH_DM365_H +#define __ASM_ARCH_DM665_H + +#include +#include +#include + +#define DM365_EMAC_BASE (0x01D07000) +#define DM365_EMAC_CNTRL_OFFSET (0x0000) +#define DM365_EMAC_CNTRL_MOD_OFFSET (0x3000) +#define DM365_EMAC_CNTRL_RAM_OFFSET (0x1000) +#define DM365_EMAC_MDIO_OFFSET (0x4000) +#define DM365_EMAC_CNTRL_RAM_SIZE (0x2000) + +void __init dm365_init(void); + +#endif /* __ASM_ARCH_DM365_H */ diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h index bc5d6aaa69a3..0d34f2fb0993 100644 --- a/arch/arm/mach-davinci/include/mach/irqs.h +++ b/arch/arm/mach-davinci/include/mach/irqs.h @@ -206,4 +206,40 @@ #define IRQ_DM355_GPIOBNK5 59 #define IRQ_DM355_GPIOBNK6 60 +/* DaVinci DM365-specific Interrupts */ +#define IRQ_DM365_INSFINT 7 +#define IRQ_DM365_IMCOPINT 11 +#define IRQ_DM365_RTOINT 13 +#define IRQ_DM365_TINT5 14 +#define IRQ_DM365_TINT6 15 +#define IRQ_DM365_SPINT2_1 21 +#define IRQ_DM365_TINT7 22 +#define IRQ_DM365_SDIOINT0 23 +#define IRQ_DM365_MMCINT1 27 +#define IRQ_DM365_PWMINT3 28 +#define IRQ_DM365_SDIOINT1 31 +#define IRQ_DM365_SPIINT0_0 42 +#define IRQ_DM365_SPIINT3_0 43 +#define IRQ_DM365_GPIO0 44 +#define IRQ_DM365_GPIO1 45 +#define IRQ_DM365_GPIO2 46 +#define IRQ_DM365_GPIO3 47 +#define IRQ_DM365_GPIO4 48 +#define IRQ_DM365_GPIO5 49 +#define IRQ_DM365_GPIO6 50 +#define IRQ_DM365_GPIO7 51 +#define IRQ_DM365_EMAC_RXTHRESH 52 +#define IRQ_DM365_EMAC_RXPULSE 53 +#define IRQ_DM365_EMAC_TXPULSE 54 +#define IRQ_DM365_EMAC_MISCPULSE 55 +#define IRQ_DM365_GPIO12 56 +#define IRQ_DM365_GPIO13 57 +#define IRQ_DM365_GPIO14 58 +#define IRQ_DM365_GPIO15 59 +#define IRQ_DM365_ADCINT 59 +#define IRQ_DM365_KEYINT 60 +#define IRQ_DM365_TCERRINT2 61 +#define IRQ_DM365_TCERRINT3 62 +#define IRQ_DM365_EMUINT 63 + #endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index 27378458542f..c182bd458d73 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -156,6 +156,87 @@ enum davinci_dm355_index { DM355_EVT26_MMC0_RX, }; +enum davinci_dm365_index { + /* MMC/SD 0 */ + DM365_MMCSD0, + + /* MMC/SD 1 */ + DM365_SD1_CLK, + DM365_SD1_CMD, + DM365_SD1_DATA3, + DM365_SD1_DATA2, + DM365_SD1_DATA1, + DM365_SD1_DATA0, + + /* I2C */ + DM365_I2C_SDA, + DM365_I2C_SCL, + + /* AEMIF */ + DM365_AEMIF_AR, + DM365_AEMIF_A3, + DM365_AEMIF_A7, + DM365_AEMIF_D15_8, + DM365_AEMIF_CE0, + + /* ASP0 function */ + DM365_MCBSP0_BDX, + DM365_MCBSP0_X, + DM365_MCBSP0_BFSX, + DM365_MCBSP0_BDR, + DM365_MCBSP0_R, + DM365_MCBSP0_BFSR, + + /* SPI0 */ + DM365_SPI0_SCLK, + DM365_SPI0_SDI, + DM365_SPI0_SDO, + DM365_SPI0_SDENA0, + DM365_SPI0_SDENA1, + + /* UART */ + DM365_UART0_RXD, + DM365_UART0_TXD, + DM365_UART1_RXD, + DM365_UART1_TXD, + DM365_UART1_RTS, + DM365_UART1_CTS, + + /* EMAC */ + DM365_EMAC_TX_EN, + DM365_EMAC_TX_CLK, + DM365_EMAC_COL, + DM365_EMAC_TXD3, + DM365_EMAC_TXD2, + DM365_EMAC_TXD1, + DM365_EMAC_TXD0, + DM365_EMAC_RXD3, + DM365_EMAC_RXD2, + DM365_EMAC_RXD1, + DM365_EMAC_RXD0, + DM365_EMAC_RX_CLK, + DM365_EMAC_RX_DV, + DM365_EMAC_RX_ER, + DM365_EMAC_CRS, + DM365_EMAC_MDIO, + DM365_EMAC_MDCLK, + + /* IRQ muxing */ + DM365_INT_EDMA_CC, + DM365_INT_EDMA_TC0_ERR, + DM365_INT_EDMA_TC1_ERR, + DM365_INT_PRTCSS, + DM365_INT_EMAC_RXTHRESH, + DM365_INT_EMAC_RXPULSE, + DM365_INT_EMAC_TXPULSE, + DM365_INT_EMAC_MISCPULSE, + + /* EDMA event muxing */ + DM365_EVT2_ASP_TX, + DM365_EVT3_ASP_RX, + DM365_EVT26_MMC0_RX, +}; + #ifdef CONFIG_DAVINCI_MUX /* setup pin muxing */ extern int davinci_cfg_reg(unsigned long reg_cfg); diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h index ab8a2586d1cc..2bb414b14297 100644 --- a/arch/arm/mach-davinci/include/mach/psc.h +++ b/arch/arm/mach-davinci/include/mach/psc.h @@ -81,6 +81,24 @@ #define DM355_LPSC_RTO 12 #define DM355_LPSC_VPSS_DAC 41 +/* DM365 */ +#define DM365_LPSC_TIMER3 5 +#define DM365_LPSC_SPI1 6 +#define DM365_LPSC_MMC_SD1 7 +#define DM365_LPSC_McBSP1 8 +#define DM365_LPSC_PWM3 10 +#define DM365_LPSC_SPI2 11 +#define DM365_LPSC_RTO 12 +#define DM365_LPSC_TIMER4 17 +#define DM365_LPSC_SPI0 22 +#define DM365_LPSC_SPI3 38 +#define DM365_LPSC_SPI4 39 +#define DM365_LPSC_EMAC 40 +#define DM365_LPSC_VOICE_CODEC 44 +#define DM365_LPSC_DAC_CLK 46 +#define DM365_LPSC_VPSSMSTR 47 +#define DM365_LPSC_MJCP 50 + /* * LPSC Assignments */ -- cgit v1.2.2 From 9f5131538368b299aabcc790f1cece0439e65a5e Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Sat, 20 Jun 2009 12:11:09 -0400 Subject: davinci: dm365: add mux entries for EDMA, RTC, EMAC, keypad. Signed-off-by: Sandeep Paulraj Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/mux.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index c182bd458d73..55765e1fdb78 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -221,10 +221,15 @@ enum davinci_dm365_index { DM365_EMAC_MDIO, DM365_EMAC_MDCLK, + /* Keypad */ + DM365_KEYPAD, + /* IRQ muxing */ DM365_INT_EDMA_CC, DM365_INT_EDMA_TC0_ERR, DM365_INT_EDMA_TC1_ERR, + DM365_INT_EDMA_TC2_ERR, + DM365_INT_EDMA_TC3_ERR, DM365_INT_PRTCSS, DM365_INT_EMAC_RXTHRESH, DM365_INT_EMAC_RXPULSE, -- cgit v1.2.2 From 55c79a40e34566e9d198f6205b0cf06e3d89ac0a Mon Sep 17 00:00:00 2001 From: "Mark A. Greer" Date: Wed, 3 Jun 2009 18:36:54 -0700 Subject: davinci: da8xx: Add base DA830/OMAP-L137 SoC support The da830/omap l137 is a new SoC from TI that is similar to the davinci line. Since its so similar to davinci, put the support for the da830 in the same directory as the davinci code. There are differences, however. Some of those differences prevent support for davinci and da830 platforms to work in the same kernel binary. Those differences are: 1) Different physical address for RAM. This is relevant to Makefile.boot addresses and PHYS_OFFSET. The Makefile.boot issue isn't truly a kernel issue but it means u-boot won't work with a uImage including both architectures. The PHYS_OFFSET issue is addressed by the "Allow for runtime-determined PHYS_OFFSET" patch by Lennert Buytenhek but it hasn't been accepted yet. 2) Different uart addresses. This is only an issue for the 'addruart' assembly macro when CONFIG_DEBUG_LL is enabled. Since the code in that macro is called so early (e.g., by _error_p in kernel/head.S when the processor lookup fails), we can't determine what platform the kernel is running on at runtime to use the correct uart address. These areas have compile errors intentionally inserted to indicate to the builder they're doing something wrong. A new config variable, CONFIG_ARCH_DAVINCI_DMx, is added to distinguish between a true davinci architecture and the da830 architecture. Note that the da830 currently has an issue with writeback data cache so CONFIG_CPU_DCACHE_WRITETHROUGH should be enabled when building a da830 kernel. Additional generalizations for future SoCs in the da8xx family done by Sudhakar Rajashekhara and Sekhar Nori. Signed-off-by: Steve Chen Signed-off-by: Mikhail Cherkashin Signed-off-by: Mark A. Greer Cc: Sudhakar Rajashekhara Cc: Sekhar Nori Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/cputype.h | 8 + arch/arm/mach-davinci/include/mach/da8xx.h | 69 +++++ arch/arm/mach-davinci/include/mach/edma.h | 48 ++++ arch/arm/mach-davinci/include/mach/irqs.h | 109 +++++++- arch/arm/mach-davinci/include/mach/memory.h | 9 +- arch/arm/mach-davinci/include/mach/mux.h | 404 +++++++++++++++++++++++++++ arch/arm/mach-davinci/include/mach/psc.h | 41 +++ arch/arm/mach-davinci/include/mach/serial.h | 4 + 8 files changed, 688 insertions(+), 4 deletions(-) create mode 100644 arch/arm/mach-davinci/include/mach/da8xx.h (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h index 56b92d49e293..fd41189e5c62 100644 --- a/arch/arm/mach-davinci/include/mach/cputype.h +++ b/arch/arm/mach-davinci/include/mach/cputype.h @@ -31,6 +31,7 @@ struct davinci_id { #define DAVINCI_CPU_ID_DM6467 0x64670000 #define DAVINCI_CPU_ID_DM355 0x03550000 #define DAVINCI_CPU_ID_DM365 0x03650000 +#define DAVINCI_CPU_ID_DA830 0x08300000 #define IS_DAVINCI_CPU(type, id) \ static inline int is_davinci_ ##type(void) \ @@ -42,6 +43,7 @@ IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446) IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467) IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355) IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365) +IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830) #ifdef CONFIG_ARCH_DAVINCI_DM644x #define cpu_is_davinci_dm644x() is_davinci_dm644x() @@ -67,4 +69,10 @@ IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365) #define cpu_is_davinci_dm365() 0 #endif +#ifdef CONFIG_ARCH_DAVINCI_DA830 +#define cpu_is_davinci_da830() is_davinci_da830() +#else +#define cpu_is_davinci_da830() 0 +#endif + #endif diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h new file mode 100644 index 000000000000..084db271c7c4 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -0,0 +1,69 @@ +/* + * Chip specific defines for DA8XX/OMAP L1XX SoC + * + * Author: Mark A. Greer + * + * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_DAVINCI_DA8XX_H +#define __ASM_ARCH_DAVINCI_DA8XX_H + +#include +#include +#include +#include + +/* + * The cp_intc interrupt controller for the da8xx isn't in the same + * chunk of physical memory space as the other registers (like it is + * on the davincis) so it needs to be mapped separately. It will be + * mapped early on when the I/O space is mapped and we'll put it just + * before the I/O space in the processor's virtual memory space. + */ +#define DA8XX_CP_INTC_BASE 0xfffee000 +#define DA8XX_CP_INTC_SIZE SZ_8K +#define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K) + +#define DA8XX_BOOT_CFG_BASE (IO_PHYS + 0x14000) + +void __init da830_init(void); + +int da8xx_register_edma(void); +int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); +int da8xx_register_watchdog(void); +int da8xx_register_emac(void); + +extern struct platform_device da8xx_serial_device; +extern struct emac_platform_data da8xx_emac_pdata; + +extern const short da830_emif25_pins[]; +extern const short da830_spi0_pins[]; +extern const short da830_spi1_pins[]; +extern const short da830_mmc_sd_pins[]; +extern const short da830_uart0_pins[]; +extern const short da830_uart1_pins[]; +extern const short da830_uart2_pins[]; +extern const short da830_usb20_pins[]; +extern const short da830_usb11_pins[]; +extern const short da830_uhpi_pins[]; +extern const short da830_cpgmac_pins[]; +extern const short da830_emif3c_pins[]; +extern const short da830_mcasp0_pins[]; +extern const short da830_mcasp1_pins[]; +extern const short da830_mcasp2_pins[]; +extern const short da830_i2c0_pins[]; +extern const short da830_i2c1_pins[]; +extern const short da830_lcdcntl_pins[]; +extern const short da830_pwm_pins[]; +extern const short da830_ecap0_pins[]; +extern const short da830_ecap1_pins[]; +extern const short da830_ecap2_pins[]; +extern const short da830_eqep0_pins[]; +extern const short da830_eqep1_pins[]; + +int da830_pinmux_setup(const short pins[]); + +#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */ diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h index ba2ebdd058a0..a85cbedc9b0a 100644 --- a/arch/arm/mach-davinci/include/mach/edma.h +++ b/arch/arm/mach-davinci/include/mach/edma.h @@ -139,6 +139,54 @@ struct edmacc_param { #define DAVINCI_DMA_PWM1 53 #define DAVINCI_DMA_PWM2 54 +/* DA830 specific EDMA3 information */ +#define EDMA_DA830_NUM_DMACH 32 +#define EDMA_DA830_NUM_TCC 32 +#define EDMA_DA830_NUM_PARAMENTRY 128 +#define EDMA_DA830_NUM_EVQUE 2 +#define EDMA_DA830_NUM_TC 2 +#define EDMA_DA830_CHMAP_EXIST 0 +#define EDMA_DA830_NUM_REGIONS 4 +#define DA830_DMACH2EVENT_MAP0 0x000FC03Fu +#define DA830_DMACH2EVENT_MAP1 0x00000000u +#define DA830_EDMA_ARM_OWN 0x30FFCCFFu + +/* DA830 specific EDMA3 Events Information */ +enum DA830_edma_ch { + DA830_DMACH_MCASP0_RX, + DA830_DMACH_MCASP0_TX, + DA830_DMACH_MCASP1_RX, + DA830_DMACH_MCASP1_TX, + DA830_DMACH_MCASP2_RX, + DA830_DMACH_MCASP2_TX, + DA830_DMACH_GPIO_BNK0INT, + DA830_DMACH_GPIO_BNK1INT, + DA830_DMACH_UART0_RX, + DA830_DMACH_UART0_TX, + DA830_DMACH_TMR64P0_EVTOUT12, + DA830_DMACH_TMR64P0_EVTOUT34, + DA830_DMACH_UART1_RX, + DA830_DMACH_UART1_TX, + DA830_DMACH_SPI0_RX, + DA830_DMACH_SPI0_TX, + DA830_DMACH_MMCSD_RX, + DA830_DMACH_MMCSD_TX, + DA830_DMACH_SPI1_RX, + DA830_DMACH_SPI1_TX, + DA830_DMACH_DMAX_EVTOUT6, + DA830_DMACH_DMAX_EVTOUT7, + DA830_DMACH_GPIO_BNK2INT, + DA830_DMACH_GPIO_BNK3INT, + DA830_DMACH_I2C0_RX, + DA830_DMACH_I2C0_TX, + DA830_DMACH_I2C1_RX, + DA830_DMACH_I2C1_TX, + DA830_DMACH_GPIO_BNK4INT, + DA830_DMACH_GPIO_BNK5INT, + DA830_DMACH_UART2_RX, + DA830_DMACH_UART2_TX +}; + /*ch_status paramater of callback function possible values*/ #define DMA_COMPLETE 1 #define DMA_CC_ERROR 2 diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h index 0d34f2fb0993..735e378d27ee 100644 --- a/arch/arm/mach-davinci/include/mach/irqs.h +++ b/arch/arm/mach-davinci/include/mach/irqs.h @@ -99,9 +99,6 @@ #define IRQ_EMUINT 63 #define DAVINCI_N_AINTC_IRQ 64 -#define DAVINCI_N_GPIO 104 - -#define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO) #define ARCH_TIMER_IRQ IRQ_TINT1_TINT34 @@ -242,4 +239,110 @@ #define IRQ_DM365_TCERRINT3 62 #define IRQ_DM365_EMUINT 63 +/* DA8XX interrupts */ +#define IRQ_DA8XX_COMMTX 0 +#define IRQ_DA8XX_COMMRX 1 +#define IRQ_DA8XX_NINT 2 +#define IRQ_DA8XX_EVTOUT0 3 +#define IRQ_DA8XX_EVTOUT1 4 +#define IRQ_DA8XX_EVTOUT2 5 +#define IRQ_DA8XX_EVTOUT3 6 +#define IRQ_DA8XX_EVTOUT4 7 +#define IRQ_DA8XX_EVTOUT5 8 +#define IRQ_DA8XX_EVTOUT6 9 +#define IRQ_DA8XX_EVTOUT7 10 +#define IRQ_DA8XX_CCINT0 11 +#define IRQ_DA8XX_CCERRINT 12 +#define IRQ_DA8XX_TCERRINT0 13 +#define IRQ_DA8XX_AEMIFINT 14 +#define IRQ_DA8XX_I2CINT0 15 +#define IRQ_DA8XX_MMCSDINT0 16 +#define IRQ_DA8XX_MMCSDINT1 17 +#define IRQ_DA8XX_ALLINT0 18 +#define IRQ_DA8XX_RTC 19 +#define IRQ_DA8XX_SPINT0 20 +#define IRQ_DA8XX_TINT12_0 21 +#define IRQ_DA8XX_TINT34_0 22 +#define IRQ_DA8XX_TINT12_1 23 +#define IRQ_DA8XX_TINT34_1 24 +#define IRQ_DA8XX_UARTINT0 25 +#define IRQ_DA8XX_KEYMGRINT 26 +#define IRQ_DA8XX_SECINT 26 +#define IRQ_DA8XX_SECKEYERR 26 +#define IRQ_DA8XX_CHIPINT0 28 +#define IRQ_DA8XX_CHIPINT1 29 +#define IRQ_DA8XX_CHIPINT2 30 +#define IRQ_DA8XX_CHIPINT3 31 +#define IRQ_DA8XX_TCERRINT1 32 +#define IRQ_DA8XX_C0_RX_THRESH_PULSE 33 +#define IRQ_DA8XX_C0_RX_PULSE 34 +#define IRQ_DA8XX_C0_TX_PULSE 35 +#define IRQ_DA8XX_C0_MISC_PULSE 36 +#define IRQ_DA8XX_C1_RX_THRESH_PULSE 37 +#define IRQ_DA8XX_C1_RX_PULSE 38 +#define IRQ_DA8XX_C1_TX_PULSE 39 +#define IRQ_DA8XX_C1_MISC_PULSE 40 +#define IRQ_DA8XX_MEMERR 41 +#define IRQ_DA8XX_GPIO0 42 +#define IRQ_DA8XX_GPIO1 43 +#define IRQ_DA8XX_GPIO2 44 +#define IRQ_DA8XX_GPIO3 45 +#define IRQ_DA8XX_GPIO4 46 +#define IRQ_DA8XX_GPIO5 47 +#define IRQ_DA8XX_GPIO6 48 +#define IRQ_DA8XX_GPIO7 49 +#define IRQ_DA8XX_GPIO8 50 +#define IRQ_DA8XX_I2CINT1 51 +#define IRQ_DA8XX_LCDINT 52 +#define IRQ_DA8XX_UARTINT1 53 +#define IRQ_DA8XX_MCASPINT 54 +#define IRQ_DA8XX_ALLINT1 55 +#define IRQ_DA8XX_SPINT1 56 +#define IRQ_DA8XX_UHPI_INT1 57 +#define IRQ_DA8XX_USB_INT 58 +#define IRQ_DA8XX_IRQN 59 +#define IRQ_DA8XX_RWAKEUP 60 +#define IRQ_DA8XX_UARTINT2 61 +#define IRQ_DA8XX_DFTSSINT 62 +#define IRQ_DA8XX_EHRPWM0 63 +#define IRQ_DA8XX_EHRPWM0TZ 64 +#define IRQ_DA8XX_EHRPWM1 65 +#define IRQ_DA8XX_EHRPWM1TZ 66 +#define IRQ_DA8XX_ECAP0 69 +#define IRQ_DA8XX_ECAP1 70 +#define IRQ_DA8XX_ECAP2 71 +#define IRQ_DA8XX_ARMCLKSTOPREQ 90 + +/* DA830 specific interrupts */ +#define IRQ_DA830_MPUERR 27 +#define IRQ_DA830_IOPUERR 27 +#define IRQ_DA830_BOOTCFGERR 27 +#define IRQ_DA830_EHRPWM2 67 +#define IRQ_DA830_EHRPWM2TZ 68 +#define IRQ_DA830_EQEP0 72 +#define IRQ_DA830_EQEP1 73 +#define IRQ_DA830_T12CMPINT0_0 74 +#define IRQ_DA830_T12CMPINT1_0 75 +#define IRQ_DA830_T12CMPINT2_0 76 +#define IRQ_DA830_T12CMPINT3_0 77 +#define IRQ_DA830_T12CMPINT4_0 78 +#define IRQ_DA830_T12CMPINT5_0 79 +#define IRQ_DA830_T12CMPINT6_0 80 +#define IRQ_DA830_T12CMPINT7_0 81 +#define IRQ_DA830_T12CMPINT0_1 82 +#define IRQ_DA830_T12CMPINT1_1 83 +#define IRQ_DA830_T12CMPINT2_1 84 +#define IRQ_DA830_T12CMPINT3_1 85 +#define IRQ_DA830_T12CMPINT4_1 86 +#define IRQ_DA830_T12CMPINT5_1 87 +#define IRQ_DA830_T12CMPINT6_1 88 +#define IRQ_DA830_T12CMPINT7_1 89 + +#define DA830_N_CP_INTC_IRQ 96 + +/* da830 currently has the most gpio pins (128) */ +#define DAVINCI_N_GPIO 128 +/* da830 currently has the most irqs so use DA830_N_CP_INTC_IRQ */ +#define NR_IRQS (DA830_N_CP_INTC_IRQ + DAVINCI_N_GPIO) + #endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h index c712c7cdf38f..80309aed534a 100644 --- a/arch/arm/mach-davinci/include/mach/memory.h +++ b/arch/arm/mach-davinci/include/mach/memory.h @@ -20,9 +20,16 @@ /************************************************************************** * Definitions **************************************************************************/ -#define DAVINCI_DDR_BASE 0x80000000 +#define DAVINCI_DDR_BASE 0x80000000 +#define DA8XX_DDR_BASE 0xc0000000 +#if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx) +#error Cannot enable DaVinci and DA8XX platforms concurrently +#elif defined(CONFIG_ARCH_DAVINCI_DA8XX) +#define PHYS_OFFSET DA8XX_DDR_BASE +#else #define PHYS_OFFSET DAVINCI_DDR_BASE +#endif /* * Increase size of DMA-consistent memory region diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index 55765e1fdb78..ae4f6dd3623c 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -242,6 +242,410 @@ enum davinci_dm365_index { DM365_EVT26_MMC0_RX, }; +enum da830_index { + DA830_GPIO7_14, + DA830_RTCK, + DA830_GPIO7_15, + DA830_EMU_0, + DA830_EMB_SDCKE, + DA830_EMB_CLK_GLUE, + DA830_EMB_CLK, + DA830_NEMB_CS_0, + DA830_NEMB_CAS, + DA830_NEMB_RAS, + DA830_NEMB_WE, + DA830_EMB_BA_1, + DA830_EMB_BA_0, + DA830_EMB_A_0, + DA830_EMB_A_1, + DA830_EMB_A_2, + DA830_EMB_A_3, + DA830_EMB_A_4, + DA830_EMB_A_5, + DA830_GPIO7_0, + DA830_GPIO7_1, + DA830_GPIO7_2, + DA830_GPIO7_3, + DA830_GPIO7_4, + DA830_GPIO7_5, + DA830_GPIO7_6, + DA830_GPIO7_7, + DA830_EMB_A_6, + DA830_EMB_A_7, + DA830_EMB_A_8, + DA830_EMB_A_9, + DA830_EMB_A_10, + DA830_EMB_A_11, + DA830_EMB_A_12, + DA830_EMB_D_31, + DA830_GPIO7_8, + DA830_GPIO7_9, + DA830_GPIO7_10, + DA830_GPIO7_11, + DA830_GPIO7_12, + DA830_GPIO7_13, + DA830_GPIO3_13, + DA830_EMB_D_30, + DA830_EMB_D_29, + DA830_EMB_D_28, + DA830_EMB_D_27, + DA830_EMB_D_26, + DA830_EMB_D_25, + DA830_EMB_D_24, + DA830_EMB_D_23, + DA830_EMB_D_22, + DA830_EMB_D_21, + DA830_EMB_D_20, + DA830_EMB_D_19, + DA830_EMB_D_18, + DA830_EMB_D_17, + DA830_EMB_D_16, + DA830_NEMB_WE_DQM_3, + DA830_NEMB_WE_DQM_2, + DA830_EMB_D_0, + DA830_EMB_D_1, + DA830_EMB_D_2, + DA830_EMB_D_3, + DA830_EMB_D_4, + DA830_EMB_D_5, + DA830_EMB_D_6, + DA830_GPIO6_0, + DA830_GPIO6_1, + DA830_GPIO6_2, + DA830_GPIO6_3, + DA830_GPIO6_4, + DA830_GPIO6_5, + DA830_GPIO6_6, + DA830_EMB_D_7, + DA830_EMB_D_8, + DA830_EMB_D_9, + DA830_EMB_D_10, + DA830_EMB_D_11, + DA830_EMB_D_12, + DA830_EMB_D_13, + DA830_EMB_D_14, + DA830_GPIO6_7, + DA830_GPIO6_8, + DA830_GPIO6_9, + DA830_GPIO6_10, + DA830_GPIO6_11, + DA830_GPIO6_12, + DA830_GPIO6_13, + DA830_GPIO6_14, + DA830_EMB_D_15, + DA830_NEMB_WE_DQM_1, + DA830_NEMB_WE_DQM_0, + DA830_SPI0_SOMI_0, + DA830_SPI0_SIMO_0, + DA830_SPI0_CLK, + DA830_NSPI0_ENA, + DA830_NSPI0_SCS_0, + DA830_EQEP0I, + DA830_EQEP0S, + DA830_EQEP1I, + DA830_NUART0_CTS, + DA830_NUART0_RTS, + DA830_EQEP0A, + DA830_EQEP0B, + DA830_GPIO6_15, + DA830_GPIO5_14, + DA830_GPIO5_15, + DA830_GPIO5_0, + DA830_GPIO5_1, + DA830_GPIO5_2, + DA830_GPIO5_3, + DA830_GPIO5_4, + DA830_SPI1_SOMI_0, + DA830_SPI1_SIMO_0, + DA830_SPI1_CLK, + DA830_UART0_RXD, + DA830_UART0_TXD, + DA830_AXR1_10, + DA830_AXR1_11, + DA830_NSPI1_ENA, + DA830_I2C1_SCL, + DA830_I2C1_SDA, + DA830_EQEP1S, + DA830_I2C0_SDA, + DA830_I2C0_SCL, + DA830_UART2_RXD, + DA830_TM64P0_IN12, + DA830_TM64P0_OUT12, + DA830_GPIO5_5, + DA830_GPIO5_6, + DA830_GPIO5_7, + DA830_GPIO5_8, + DA830_GPIO5_9, + DA830_GPIO5_10, + DA830_GPIO5_11, + DA830_GPIO5_12, + DA830_NSPI1_SCS_0, + DA830_USB0_DRVVBUS, + DA830_AHCLKX0, + DA830_ACLKX0, + DA830_AFSX0, + DA830_AHCLKR0, + DA830_ACLKR0, + DA830_AFSR0, + DA830_UART2_TXD, + DA830_AHCLKX2, + DA830_ECAP0_APWM0, + DA830_RMII_MHZ_50_CLK, + DA830_ECAP1_APWM1, + DA830_USB_REFCLKIN, + DA830_GPIO5_13, + DA830_GPIO4_15, + DA830_GPIO2_11, + DA830_GPIO2_12, + DA830_GPIO2_13, + DA830_GPIO2_14, + DA830_GPIO2_15, + DA830_GPIO3_12, + DA830_AMUTE0, + DA830_AXR0_0, + DA830_AXR0_1, + DA830_AXR0_2, + DA830_AXR0_3, + DA830_AXR0_4, + DA830_AXR0_5, + DA830_AXR0_6, + DA830_RMII_TXD_0, + DA830_RMII_TXD_1, + DA830_RMII_TXEN, + DA830_RMII_CRS_DV, + DA830_RMII_RXD_0, + DA830_RMII_RXD_1, + DA830_RMII_RXER, + DA830_AFSR2, + DA830_ACLKX2, + DA830_AXR2_3, + DA830_AXR2_2, + DA830_AXR2_1, + DA830_AFSX2, + DA830_ACLKR2, + DA830_NRESETOUT, + DA830_GPIO3_0, + DA830_GPIO3_1, + DA830_GPIO3_2, + DA830_GPIO3_3, + DA830_GPIO3_4, + DA830_GPIO3_5, + DA830_GPIO3_6, + DA830_AXR0_7, + DA830_AXR0_8, + DA830_UART1_RXD, + DA830_UART1_TXD, + DA830_AXR0_11, + DA830_AHCLKX1, + DA830_ACLKX1, + DA830_AFSX1, + DA830_MDIO_CLK, + DA830_MDIO_D, + DA830_AXR0_9, + DA830_AXR0_10, + DA830_EPWM0B, + DA830_EPWM0A, + DA830_EPWMSYNCI, + DA830_AXR2_0, + DA830_EPWMSYNC0, + DA830_GPIO3_7, + DA830_GPIO3_8, + DA830_GPIO3_9, + DA830_GPIO3_10, + DA830_GPIO3_11, + DA830_GPIO3_14, + DA830_GPIO3_15, + DA830_GPIO4_10, + DA830_AHCLKR1, + DA830_ACLKR1, + DA830_AFSR1, + DA830_AMUTE1, + DA830_AXR1_0, + DA830_AXR1_1, + DA830_AXR1_2, + DA830_AXR1_3, + DA830_ECAP2_APWM2, + DA830_EHRPWMGLUETZ, + DA830_EQEP1A, + DA830_GPIO4_11, + DA830_GPIO4_12, + DA830_GPIO4_13, + DA830_GPIO4_14, + DA830_GPIO4_0, + DA830_GPIO4_1, + DA830_GPIO4_2, + DA830_GPIO4_3, + DA830_AXR1_4, + DA830_AXR1_5, + DA830_AXR1_6, + DA830_AXR1_7, + DA830_AXR1_8, + DA830_AXR1_9, + DA830_EMA_D_0, + DA830_EMA_D_1, + DA830_EQEP1B, + DA830_EPWM2B, + DA830_EPWM2A, + DA830_EPWM1B, + DA830_EPWM1A, + DA830_MMCSD_DAT_0, + DA830_MMCSD_DAT_1, + DA830_UHPI_HD_0, + DA830_UHPI_HD_1, + DA830_GPIO4_4, + DA830_GPIO4_5, + DA830_GPIO4_6, + DA830_GPIO4_7, + DA830_GPIO4_8, + DA830_GPIO4_9, + DA830_GPIO0_0, + DA830_GPIO0_1, + DA830_EMA_D_2, + DA830_EMA_D_3, + DA830_EMA_D_4, + DA830_EMA_D_5, + DA830_EMA_D_6, + DA830_EMA_D_7, + DA830_EMA_D_8, + DA830_EMA_D_9, + DA830_MMCSD_DAT_2, + DA830_MMCSD_DAT_3, + DA830_MMCSD_DAT_4, + DA830_MMCSD_DAT_5, + DA830_MMCSD_DAT_6, + DA830_MMCSD_DAT_7, + DA830_UHPI_HD_8, + DA830_UHPI_HD_9, + DA830_UHPI_HD_2, + DA830_UHPI_HD_3, + DA830_UHPI_HD_4, + DA830_UHPI_HD_5, + DA830_UHPI_HD_6, + DA830_UHPI_HD_7, + DA830_LCD_D_8, + DA830_LCD_D_9, + DA830_GPIO0_2, + DA830_GPIO0_3, + DA830_GPIO0_4, + DA830_GPIO0_5, + DA830_GPIO0_6, + DA830_GPIO0_7, + DA830_GPIO0_8, + DA830_GPIO0_9, + DA830_EMA_D_10, + DA830_EMA_D_11, + DA830_EMA_D_12, + DA830_EMA_D_13, + DA830_EMA_D_14, + DA830_EMA_D_15, + DA830_EMA_A_0, + DA830_EMA_A_1, + DA830_UHPI_HD_10, + DA830_UHPI_HD_11, + DA830_UHPI_HD_12, + DA830_UHPI_HD_13, + DA830_UHPI_HD_14, + DA830_UHPI_HD_15, + DA830_LCD_D_7, + DA830_MMCSD_CLK, + DA830_LCD_D_10, + DA830_LCD_D_11, + DA830_LCD_D_12, + DA830_LCD_D_13, + DA830_LCD_D_14, + DA830_LCD_D_15, + DA830_UHPI_HCNTL0, + DA830_GPIO0_10, + DA830_GPIO0_11, + DA830_GPIO0_12, + DA830_GPIO0_13, + DA830_GPIO0_14, + DA830_GPIO0_15, + DA830_GPIO1_0, + DA830_GPIO1_1, + DA830_EMA_A_2, + DA830_EMA_A_3, + DA830_EMA_A_4, + DA830_EMA_A_5, + DA830_EMA_A_6, + DA830_EMA_A_7, + DA830_EMA_A_8, + DA830_EMA_A_9, + DA830_MMCSD_CMD, + DA830_LCD_D_6, + DA830_LCD_D_3, + DA830_LCD_D_2, + DA830_LCD_D_1, + DA830_LCD_D_0, + DA830_LCD_PCLK, + DA830_LCD_HSYNC, + DA830_UHPI_HCNTL1, + DA830_GPIO1_2, + DA830_GPIO1_3, + DA830_GPIO1_4, + DA830_GPIO1_5, + DA830_GPIO1_6, + DA830_GPIO1_7, + DA830_GPIO1_8, + DA830_GPIO1_9, + DA830_EMA_A_10, + DA830_EMA_A_11, + DA830_EMA_A_12, + DA830_EMA_BA_1, + DA830_EMA_BA_0, + DA830_EMA_CLK, + DA830_EMA_SDCKE, + DA830_NEMA_CAS, + DA830_LCD_VSYNC, + DA830_NLCD_AC_ENB_CS, + DA830_LCD_MCLK, + DA830_LCD_D_5, + DA830_LCD_D_4, + DA830_OBSCLK, + DA830_NEMA_CS_4, + DA830_UHPI_HHWIL, + DA830_AHCLKR2, + DA830_GPIO1_10, + DA830_GPIO1_11, + DA830_GPIO1_12, + DA830_GPIO1_13, + DA830_GPIO1_14, + DA830_GPIO1_15, + DA830_GPIO2_0, + DA830_GPIO2_1, + DA830_NEMA_RAS, + DA830_NEMA_WE, + DA830_NEMA_CS_0, + DA830_NEMA_CS_2, + DA830_NEMA_CS_3, + DA830_NEMA_OE, + DA830_NEMA_WE_DQM_1, + DA830_NEMA_WE_DQM_0, + DA830_NEMA_CS_5, + DA830_UHPI_HRNW, + DA830_NUHPI_HAS, + DA830_NUHPI_HCS, + DA830_NUHPI_HDS1, + DA830_NUHPI_HDS2, + DA830_NUHPI_HINT, + DA830_AXR0_12, + DA830_AMUTE2, + DA830_AXR0_13, + DA830_AXR0_14, + DA830_AXR0_15, + DA830_GPIO2_2, + DA830_GPIO2_3, + DA830_GPIO2_4, + DA830_GPIO2_5, + DA830_GPIO2_6, + DA830_GPIO2_7, + DA830_GPIO2_8, + DA830_GPIO2_9, + DA830_EMA_WAIT_0, + DA830_NUHPI_HRDY, + DA830_GPIO2_10, +}; + #ifdef CONFIG_DAVINCI_MUX /* setup pin muxing */ extern int davinci_cfg_reg(unsigned long reg_cfg); diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h index 2bb414b14297..6b9621d88284 100644 --- a/arch/arm/mach-davinci/include/mach/psc.h +++ b/arch/arm/mach-davinci/include/mach/psc.h @@ -136,6 +136,47 @@ #define DM646X_LPSC_TIMER1 35 #define DM646X_LPSC_ARM_INTC 45 +/* PSC0 defines */ +#define DA8XX_LPSC0_TPCC 0 +#define DA8XX_LPSC0_TPTC0 1 +#define DA8XX_LPSC0_TPTC1 2 +#define DA8XX_LPSC0_EMIF25 3 +#define DA8XX_LPSC0_SPI0 4 +#define DA8XX_LPSC0_MMC_SD 5 +#define DA8XX_LPSC0_AINTC 6 +#define DA8XX_LPSC0_ARM_RAM_ROM 7 +#define DA8XX_LPSC0_SECU_MGR 8 +#define DA8XX_LPSC0_UART0 9 +#define DA8XX_LPSC0_SCR0_SS 10 +#define DA8XX_LPSC0_SCR1_SS 11 +#define DA8XX_LPSC0_SCR2_SS 12 +#define DA8XX_LPSC0_DMAX 13 +#define DA8XX_LPSC0_ARM 14 +#define DA8XX_LPSC0_GEM 15 + +/* PSC1 defines */ +#define DA8XX_LPSC1_USB20 1 +#define DA8XX_LPSC1_USB11 2 +#define DA8XX_LPSC1_GPIO 3 +#define DA8XX_LPSC1_UHPI 4 +#define DA8XX_LPSC1_CPGMAC 5 +#define DA8XX_LPSC1_EMIF3C 6 +#define DA8XX_LPSC1_McASP0 7 +#define DA830_LPSC1_McASP1 8 +#define DA830_LPSC1_McASP2 9 +#define DA8XX_LPSC1_SPI1 10 +#define DA8XX_LPSC1_I2C 11 +#define DA8XX_LPSC1_UART1 12 +#define DA8XX_LPSC1_UART2 13 +#define DA8XX_LPSC1_LCDC 16 +#define DA8XX_LPSC1_PWM 17 +#define DA8XX_LPSC1_ECAP 20 +#define DA830_LPSC1_EQEP 21 +#define DA8XX_LPSC1_SCR_P0_SS 24 +#define DA8XX_LPSC1_SCR_P1_SS 25 +#define DA8XX_LPSC1_CR_P3_SS 26 +#define DA8XX_LPSC1_L3_CBA_RAM 31 + extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id); extern void davinci_psc_config(unsigned int domain, unsigned int ctlr, unsigned int id, char enable); diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h index 794fa5cf93c1..57e68e610ee9 100644 --- a/arch/arm/mach-davinci/include/mach/serial.h +++ b/arch/arm/mach-davinci/include/mach/serial.h @@ -18,6 +18,10 @@ #define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) #define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) +#define DA8XX_UART0_BASE (IO_PHYS + 0x042000) +#define DA8XX_UART1_BASE (IO_PHYS + 0x10c000) +#define DA8XX_UART2_BASE (IO_PHYS + 0x10d000) + /* DaVinci UART register offsets */ #define UART_DAVINCI_PWREMU 0x0c #define UART_DM646X_SCR 0x10 -- cgit v1.2.2 From 8593790d604c29a717d5914159ce78c7bb9899fb Mon Sep 17 00:00:00 2001 From: "Mark A. Greer" Date: Wed, 3 Jun 2009 18:41:53 -0700 Subject: davinci: da8xx: Add support for DA830/OMAP-L137 EVM board Add support for the DA830/OMAP-L137 Evaluation Module (EVM) from TI. The EVM has User Interface (UI) and Audio cards that can be connected which contain various devices. Support for those devices and ones on the EVM will be added in subsequent patches. Additional generalizations for future SoCs in da8xx family done by Sudhakar Rajashekhara and Sekhar Nori. Signed-off-by: Steve Chen Signed-off-by: Mark A. Greer Cc: Sudhakar Rajashekhara Cc: Sekhar Nori Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/debug-macro.S | 7 +++++++ arch/arm/mach-davinci/include/mach/uncompress.h | 6 ++++-- 2 files changed, 11 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S index de3fc2182b47..69837a67d5f5 100644 --- a/arch/arm/mach-davinci/include/mach/debug-macro.S +++ b/arch/arm/mach-davinci/include/mach/debug-macro.S @@ -24,7 +24,14 @@ tst \rx, #1 @ MMU enabled? moveq \rx, #0x01000000 @ physical base address movne \rx, #0xfe000000 @ virtual base +#if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx) +#error Cannot enable DaVinci and DA8XX platforms concurrently +#elif defined(CONFIG_MACH_DAVINCI_DA8XX_EVM) + orr \rx, \rx, #0x00d00000 @ physical base address + orr \rx, \rx, #0x0000d000 @ of UART 2 +#else orr \rx, \rx, #0x00c20000 @ UART 0 +#endif .endm .macro senduart,rd,rx diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h index 1e27475f9a23..0f1f12b67875 100644 --- a/arch/arm/mach-davinci/include/mach/uncompress.h +++ b/arch/arm/mach-davinci/include/mach/uncompress.h @@ -21,8 +21,10 @@ static u32 *uart; static u32 *get_uart_base(void) { - /* Add logic here for new platforms, using __macine_arch_type */ - return (u32 *)DAVINCI_UART0_BASE; + if (__machine_arch_type == MACH_TYPE_DAVINCI_DA8XX_EVM) + return (u32 *)DA8XX_UART2_BASE; + else + return (u32 *)DAVINCI_UART0_BASE; } /* PORT_16C550A, in polled non-fifo mode */ -- cgit v1.2.2 From af5dbaef76cb01995639cef10ca6f5a2b08207e8 Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Wed, 24 Jun 2009 12:22:28 -0400 Subject: davinci: DM365 Updating PINMUX Entries Patch updates DM365 PINMUX by adding entries for Video, SPI 1 - 4, PWM 0 - 3. Signed-off-by: Sandeep Paulraj Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/mux.h | 58 ++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index ae4f6dd3623c..cce7509ea302 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -224,6 +224,64 @@ enum davinci_dm365_index { /* Keypad */ DM365_KEYPAD, + /* PWM */ + DM365_PWM0, + DM365_PWM0_G23, + DM365_PWM1, + DM365_PWM1_G25, + DM365_PWM2_G87, + DM365_PWM2_G88, + DM365_PWM2_G89, + DM365_PWM2_G90, + DM365_PWM3_G80, + DM365_PWM3_G81, + DM365_PWM3_G85, + DM365_PWM3_G86, + + /* SPI1 */ + DM365_SPI1_SCLK, + DM365_SPI1_SDO, + DM365_SPI1_SDI, + DM365_SPI1_SDENA0, + DM365_SPI1_SDENA1, + + /* SPI2 */ + DM365_SPI2_SCLK, + DM365_SPI2_SDO, + DM365_SPI2_SDI, + DM365_SPI2_SDENA0, + DM365_SPI2_SDENA1, + + /* SPI3 */ + DM365_SPI3_SCLK, + DM365_SPI3_SDO, + DM365_SPI3_SDI, + DM365_SPI3_SDENA0, + DM365_SPI3_SDENA1, + + /* SPI4 */ + DM365_SPI4_SCLK, + DM365_SPI4_SDO, + DM365_SPI4_SDI, + DM365_SPI4_SDENA0, + DM365_SPI4_SDENA1, + + /* GPIO */ + DM365_GPIO20, + DM365_GPIO33, + DM365_GPIO40, + + /* Video */ + DM365_VOUT_FIELD, + DM365_VOUT_FIELD_G81, + DM365_VOUT_HVSYNC, + DM365_VOUT_COUTL_EN, + DM365_VOUT_COUTH_EN, + DM365_VIN_CAM_WEN, + DM365_VIN_CAM_VD, + DM365_VIN_CAM_HD, + DM365_VIN_YIN_EN, + /* IRQ muxing */ DM365_INT_EDMA_CC, DM365_INT_EDMA_TC0_ERR, -- cgit v1.2.2 From 7a36071e7954836ba437987e5ca4ced174462b28 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Thu, 25 Jun 2009 17:01:31 -0700 Subject: davinci: dm365 gpio irq support Support DM365 GPIOs ... primarily by handling non-banked GPIO IRQs: - Flag DM365 chips as using non-banked GPIO interrupts, using a new soc_info field. - Replace the gpio_to_irq() mapping logic. This now uses some runtime infrastructure, keyed off that new soc_info field, which doesn't handle irq_to_gpio(). - Provide a new irq_chip ... GPIO IRQs handled directly by AINTC still need edge triggering managed by the GPIO controller. DM365 chips no longer falsely report 104 GPIO IRQs as they boot. Intelligence about IRQ muxing is missing, so for the moment this only exposes the first eight DM365 GPIOs, which are never muxed. The next eight are muxed, half with Ethernet (which uses most of those pins anyway). Tested on DM355 (10 unbanked IRQs _or_ 104 banked ones) and also on DM365 (16 unbanked ones, only 8 made available). Signed-off-by: David Brownell Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/common.h | 1 + arch/arm/mach-davinci/include/mach/gpio.h | 8 +++----- 2 files changed, 4 insertions(+), 5 deletions(-) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h index b21393b24d65..1fd3917cae4e 100644 --- a/arch/arm/mach-davinci/include/mach/common.h +++ b/arch/arm/mach-davinci/include/mach/common.h @@ -63,6 +63,7 @@ struct davinci_soc_info { void __iomem *gpio_base; unsigned gpio_num; unsigned gpio_irq; + unsigned gpio_unbanked; struct platform_device *serial_dev; struct emac_platform_data *emac_pdata; dma_addr_t sram_dma; diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h index ae0745568316..ebcc29babeae 100644 --- a/arch/arm/mach-davinci/include/mach/gpio.h +++ b/arch/arm/mach-davinci/include/mach/gpio.h @@ -142,15 +142,13 @@ static inline int gpio_cansleep(unsigned gpio) static inline int gpio_to_irq(unsigned gpio) { - if (gpio >= DAVINCI_N_GPIO) - return -EINVAL; - return davinci_soc_info.intc_irq_num + gpio; + return __gpio_to_irq(gpio); } static inline int irq_to_gpio(unsigned irq) { - /* caller guarantees gpio_to_irq() succeeded */ - return irq - davinci_soc_info.intc_irq_num; + /* don't support the reverse mapping */ + return -ENOSYS; } #endif /* __DAVINCI_GPIO_H */ -- cgit v1.2.2 From 25acf553aeed86f93f2cf39227b59fc6eb3e8c78 Mon Sep 17 00:00:00 2001 From: Chaithrika U S Date: Fri, 5 Jun 2009 06:28:08 -0400 Subject: davinci: ASoC: Add the platform devices for ASP 1) Registers the platform devices for ASP on dm355, dm644x and dm646x so that the machine driver can probe to get ASP related platform data. 2) Move towards definition of the asp clocks using physical name(for dm355 and dm644x) 3) Add platform data to board specific files. Signed-off-by: Naresh Medisetty Signed-off-by: Chaithrika U S Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/asp.h | 35 +++++++++++++++++++++++++++-- arch/arm/mach-davinci/include/mach/dm355.h | 5 +++++ arch/arm/mach-davinci/include/mach/dm644x.h | 2 ++ arch/arm/mach-davinci/include/mach/dm646x.h | 3 +++ 4 files changed, 43 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h index e0abc437d796..038ecb7c231b 100644 --- a/arch/arm/mach-davinci/include/mach/asp.h +++ b/arch/arm/mach-davinci/include/mach/asp.h @@ -5,21 +5,52 @@ #define __ASM_ARCH_DAVINCI_ASP_H #include +#include -/* Bases of register banks */ +/* Bases of dm644x and dm355 register banks */ #define DAVINCI_ASP0_BASE 0x01E02000 #define DAVINCI_ASP1_BASE 0x01E04000 -/* EDMA channels */ +/* Bases of dm646x register banks */ +#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000 +#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800 + +/* EDMA channels of dm644x and dm355 */ #define DAVINCI_DMA_ASP0_TX 2 #define DAVINCI_DMA_ASP0_RX 3 #define DAVINCI_DMA_ASP1_TX 8 #define DAVINCI_DMA_ASP1_RX 9 +/* EDMA channels of dm646x */ +#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6 +#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9 +#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12 + /* Interrupts */ #define DAVINCI_ASP0_RX_INT IRQ_MBRINT #define DAVINCI_ASP0_TX_INT IRQ_MBXINT #define DAVINCI_ASP1_RX_INT IRQ_MBRINT #define DAVINCI_ASP1_TX_INT IRQ_MBXINT +struct snd_platform_data { + char *clk_name; + u32 tx_dma_offset; + u32 rx_dma_offset; + enum dma_event_q eventq_no; /* event queue number */ + unsigned int codec_fmt; + + /* McASP specific fields */ + int tdm_slots; + u8 op_mode; + u8 num_serializer; + u8 *serial_dir; +}; + +#define INACTIVE_MODE 0 +#define TX_MODE 1 +#define RX_MODE 2 + +#define DAVINCI_MCASP_IIS_MODE 0 +#define DAVINCI_MCASP_DIT_MODE 1 + #endif /* __ASM_ARCH_DAVINCI_ASP_H */ diff --git a/arch/arm/mach-davinci/include/mach/dm355.h b/arch/arm/mach-davinci/include/mach/dm355.h index 54903b72438e..03faaef95a9a 100644 --- a/arch/arm/mach-davinci/include/mach/dm355.h +++ b/arch/arm/mach-davinci/include/mach/dm355.h @@ -12,11 +12,16 @@ #define __ASM_ARCH_DM355_H #include +#include + +#define ASP1_TX_EVT_EN 1 +#define ASP1_RX_EVT_EN 2 struct spi_board_info; void __init dm355_init(void); void dm355_init_spi0(unsigned chipselect_mask, struct spi_board_info *info, unsigned len); +void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata); #endif /* __ASM_ARCH_DM355_H */ diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h index 15d42b92a8c9..8b157ceec0ca 100644 --- a/arch/arm/mach-davinci/include/mach/dm644x.h +++ b/arch/arm/mach-davinci/include/mach/dm644x.h @@ -25,6 +25,7 @@ #include #include #include +#include #define DM644X_EMAC_BASE (0x01C80000) #define DM644X_EMAC_CNTRL_OFFSET (0x0000) @@ -34,5 +35,6 @@ #define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000) void __init dm644x_init(void); +void __init dm644x_init_asp(struct snd_platform_data *pdata); #endif /* __ASM_ARCH_DM644X_H */ diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h index 1fc764c8646e..05854846242a 100644 --- a/arch/arm/mach-davinci/include/mach/dm646x.h +++ b/arch/arm/mach-davinci/include/mach/dm646x.h @@ -13,6 +13,7 @@ #include #include +#include #define DM646X_EMAC_BASE (0x01C80000) #define DM646X_EMAC_CNTRL_OFFSET (0x0000) @@ -22,5 +23,7 @@ #define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000) void __init dm646x_init(void); +void __init dm646x_init_mcasp0(struct snd_platform_data *pdata); +void __init dm646x_init_mcasp1(struct snd_platform_data *pdata); #endif /* __ASM_ARCH_DM646X_H */ -- cgit v1.2.2 From 9eb7115bcc423ae022ebf1844820d58a77c2d435 Mon Sep 17 00:00:00 2001 From: Hemant Pedanekar Date: Wed, 24 Jun 2009 10:15:47 +0530 Subject: davinci: Move IO device mapping macros from io.h to hardware.h This patch takes out IO mapping macros from mach/io.h and puts them in mach/hardware.h avoiding need to include mach/io.h in various files such as serial.h, vmalloc.h etc. The main reason to avoid inclusion of mach/io.h is, when default in/out macros are overridden by machine specific functions (e.g., in case of PCI I/O), they result into linker error. An example snippet and error snapshot is listed below. Following code in mach/io.h: #define inl(p) my_inl() static inline unsigned int my_inl(unsigned int addr) { if (IS_PCI_IO(addr)) return pci_inl (); else return le32_to_cpu(__raw_readl(__typesafe_io(addr))); } leads to error: LD arch/arm/boot/compressed/vmlinux arch/arm/boot/compressed/misc.o: In function `my_inl': misc.c:(.text+0x2744): undefined reference to `pci_inl' make[2]: *** [arch/arm/boot/compressed/vmlinux] Error 1 This is because mach/io.h gets included in arch/arm/boot/compressed/misc.c through mach/serial.h but pci.c file, which defines 'pci_inl' doesn't get built into compressed vmlinux. Signed-off-by: Hemant Pedanekar Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/hardware.h | 17 +++++++++++++++++ arch/arm/mach-davinci/include/mach/io.h | 23 ++--------------------- arch/arm/mach-davinci/include/mach/serial.h | 2 +- arch/arm/mach-davinci/include/mach/vmalloc.h | 2 +- 4 files changed, 21 insertions(+), 23 deletions(-) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h index 48c77934d519..41c89386e39b 100644 --- a/arch/arm/mach-davinci/include/mach/hardware.h +++ b/arch/arm/mach-davinci/include/mach/hardware.h @@ -24,4 +24,21 @@ /* System control register offsets */ #define DM64XX_VDD3P3V_PWDN 0x48 +/* + * I/O mapping + */ +#define IO_PHYS 0x01c00000 +#define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */ +#define IO_SIZE 0x00400000 +#define IO_VIRT (IO_PHYS + IO_OFFSET) +#define io_v2p(va) ((va) - IO_OFFSET) +#define __IO_ADDRESS(x) ((x) + IO_OFFSET) +#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa)) + +#ifdef __ASSEMBLER__ +#define IOMEM(x) x +#else +#define IOMEM(x) ((void __force __iomem *)(x)) +#endif + #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h index 2479785405af..62b0a90309ad 100644 --- a/arch/arm/mach-davinci/include/mach/io.h +++ b/arch/arm/mach-davinci/include/mach/io.h @@ -13,18 +13,6 @@ #define IO_SPACE_LIMIT 0xffffffff -/* - * ---------------------------------------------------------------------------- - * I/O mapping - * ---------------------------------------------------------------------------- - */ -#define IO_PHYS 0x01c00000 -#define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */ -#define IO_SIZE 0x00400000 -#define IO_VIRT (IO_PHYS + IO_OFFSET) -#define io_v2p(va) ((va) - IO_OFFSET) -#define __IO_ADDRESS(x) ((x) + IO_OFFSET) - /* * We don't actually have real ISA nor PCI buses, but there is so many * drivers out there that might just work if we fake them... @@ -33,19 +21,12 @@ #define __mem_pci(a) (a) #define __mem_isa(a) (a) -#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa)) - -#ifdef __ASSEMBLER__ -#define IOMEM(x) x -#else -#define IOMEM(x) ((void __force __iomem *)(x)) - +#ifndef __ASSEMBLER__ #define __arch_ioremap(p, s, t) davinci_ioremap(p, s, t) #define __arch_iounmap(v) davinci_iounmap(v) void __iomem *davinci_ioremap(unsigned long phys, size_t size, unsigned int type); void davinci_iounmap(volatile void __iomem *addr); - -#endif /* __ASSEMBLER__ */ +#endif #endif /* __ASM_ARCH_IO_H */ diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h index 57e68e610ee9..a584697a9e70 100644 --- a/arch/arm/mach-davinci/include/mach/serial.h +++ b/arch/arm/mach-davinci/include/mach/serial.h @@ -11,7 +11,7 @@ #ifndef __ASM_ARCH_SERIAL_H #define __ASM_ARCH_SERIAL_H -#include +#include #define DAVINCI_MAX_NR_UARTS 3 #define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) diff --git a/arch/arm/mach-davinci/include/mach/vmalloc.h b/arch/arm/mach-davinci/include/mach/vmalloc.h index ad51625b6609..d49646a8e206 100644 --- a/arch/arm/mach-davinci/include/mach/vmalloc.h +++ b/arch/arm/mach-davinci/include/mach/vmalloc.h @@ -8,7 +8,7 @@ * is licensed "as is" without any warranty of any kind, whether express * or implied. */ -#include +#include /* Allow vmalloc range until the IO virtual range minus a 2M "hole" */ #define VMALLOC_END (IO_VIRT - (2<<20)) -- cgit v1.2.2 From baf09a4cd029c10fd46ef3d1505e2fe8cddcb48e Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Wed, 8 Jul 2009 08:32:27 -0700 Subject: davinci: da830: updates for mach-type name change Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/debug-macro.S | 2 +- arch/arm/mach-davinci/include/mach/uncompress.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S index 69837a67d5f5..9d16277b233f 100644 --- a/arch/arm/mach-davinci/include/mach/debug-macro.S +++ b/arch/arm/mach-davinci/include/mach/debug-macro.S @@ -26,7 +26,7 @@ movne \rx, #0xfe000000 @ virtual base #if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx) #error Cannot enable DaVinci and DA8XX platforms concurrently -#elif defined(CONFIG_MACH_DAVINCI_DA8XX_EVM) +#elif defined(CONFIG_MACH_DAVINCI_DA830_EVM) orr \rx, \rx, #0x00d00000 @ physical base address orr \rx, \rx, #0x0000d000 @ of UART 2 #else diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h index 0f1f12b67875..46a0c3171e35 100644 --- a/arch/arm/mach-davinci/include/mach/uncompress.h +++ b/arch/arm/mach-davinci/include/mach/uncompress.h @@ -21,7 +21,7 @@ static u32 *uart; static u32 *get_uart_base(void) { - if (__machine_arch_type == MACH_TYPE_DAVINCI_DA8XX_EVM) + if (__machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM) return (u32 *)DA8XX_UART2_BASE; else return (u32 *)DAVINCI_UART0_BASE; -- cgit v1.2.2 From 6077d265324f13a4b7db30eb70cabed07fd58936 Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Thu, 9 Jul 2009 20:26:38 +0530 Subject: davinci: make arch_idle and arch_reset as inline functions Make arch_idle and arch_reset inline as inline function. Not having them inline leads to a warning of this sort when only one of these functions is used: arch/arm/mach-davinci/include/mach/system.h:24: warning: 'arch_reset' \ defined but not used boot, re-boot tested on OMAP-L138 EVM Signed-off-by: Sekhar Nori Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/system.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h index b7e7036674fa..8e4f10fe1263 100644 --- a/arch/arm/mach-davinci/include/mach/system.h +++ b/arch/arm/mach-davinci/include/mach/system.h @@ -16,12 +16,12 @@ extern void davinci_watchdog_reset(void); -static void arch_idle(void) +static inline void arch_idle(void) { cpu_do_idle(); } -static void arch_reset(char mode, const char *cmd) +static inline void arch_reset(char mode, const char *cmd) { davinci_watchdog_reset(); } -- cgit v1.2.2 From 1c92a554fcad141f8c73eecdb1cc5ac0527a5c15 Mon Sep 17 00:00:00 2001 From: Hemant Pedanekar Date: Thu, 9 Jul 2009 19:43:20 +0530 Subject: davinci: dm646x: Add IDE setup This patch adds platform data and init function for IDE which could be called from board specific file to register IDE device. Note that for 594MHz device the transfer mode is limited to UDMA4 since ideclk rate is less than 100 MHz, which forces udma_mask in palm_bk3710.c to UDMA4, while for 729MHz device, it is UDMA5. Signed-off-by: Hemant Pedanekar Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/dm646x.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h index 05854846242a..feb1e02cdbd8 100644 --- a/arch/arm/mach-davinci/include/mach/dm646x.h +++ b/arch/arm/mach-davinci/include/mach/dm646x.h @@ -22,7 +22,10 @@ #define DM646X_EMAC_MDIO_OFFSET (0x4000) #define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000) +#define DM646X_ATA_REG_BASE (0x01C66000) + void __init dm646x_init(void); +void __init dm646x_init_ide(void); void __init dm646x_init_mcasp0(struct snd_platform_data *pdata); void __init dm646x_init_mcasp1(struct snd_platform_data *pdata); -- cgit v1.2.2 From bea238f65c81742a03662e4664d88a9b4de5ea83 Mon Sep 17 00:00:00 2001 From: "Rajashekhara, Sudhakar" Date: Fri, 10 Jul 2009 02:08:31 -0400 Subject: davinci: Move the da830/omap-l137 #defines to header file With the introduction of TI da850/omap-l138, some of the macros defined for da830/omap-l137 will be needed in da850 source file. So, move the common macros to da8xx.h header file. Also, modify the macro names from DA830_... to DA8XX_. Signed-off-by: Sudhakar Rajashekhara Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/da8xx.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 084db271c7c4..65b42431ddec 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -29,6 +29,14 @@ #define DA8XX_BOOT_CFG_BASE (IO_PHYS + 0x14000) +#define DA8XX_PSC0_BASE 0x01c10000 +#define DA8XX_PLL0_BASE 0x01c11000 +#define DA8XX_JTAG_ID_REG 0x01c14018 +#define DA8XX_TIMER64P0_BASE 0x01c20000 +#define DA8XX_TIMER64P1_BASE 0x01c21000 +#define DA8XX_GPIO_BASE 0x01e26000 +#define DA8XX_PSC1_BASE 0x01e27000 + void __init da830_init(void); int da8xx_register_edma(void); -- cgit v1.2.2 From c96b56c53fb76c540a1a8103c7594859db4351dd Mon Sep 17 00:00:00 2001 From: Sudhakar Rajashekhara Date: Thu, 16 Jul 2009 05:45:32 -0400 Subject: davinci: Rearrange the da830/omap-l137 macros and functions Rearrange the PINMUX macros and pinmux_setup function which are common between da830/omap-l137 and da850/omap-l138. Also, replace the da830 string in function names to da8xx. Signed-off-by: Sudhakar Rajashekhara Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/da8xx.h | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 65b42431ddec..8c8dc135472c 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -37,6 +37,27 @@ #define DA8XX_GPIO_BASE 0x01e26000 #define DA8XX_PSC1_BASE 0x01e27000 +#define PINMUX0 0x00 +#define PINMUX1 0x04 +#define PINMUX2 0x08 +#define PINMUX3 0x0c +#define PINMUX4 0x10 +#define PINMUX5 0x14 +#define PINMUX6 0x18 +#define PINMUX7 0x1c +#define PINMUX8 0x20 +#define PINMUX9 0x24 +#define PINMUX10 0x28 +#define PINMUX11 0x2c +#define PINMUX12 0x30 +#define PINMUX13 0x34 +#define PINMUX14 0x38 +#define PINMUX15 0x3c +#define PINMUX16 0x40 +#define PINMUX17 0x44 +#define PINMUX18 0x48 +#define PINMUX19 0x4c + void __init da830_init(void); int da8xx_register_edma(void); @@ -72,6 +93,6 @@ extern const short da830_ecap2_pins[]; extern const short da830_eqep0_pins[]; extern const short da830_eqep1_pins[]; -int da830_pinmux_setup(const short pins[]); +int da8xx_pinmux_setup(const short pins[]); #endif /* __ASM_ARCH_DAVINCI_DA8XX_H */ -- cgit v1.2.2 From e1a8d7e2ea7c971f750b1adf0e98c3c8ed002623 Mon Sep 17 00:00:00 2001 From: Sudhakar Rajashekhara Date: Thu, 16 Jul 2009 06:41:54 -0400 Subject: davinci: Add base DA850/OMAP-L138 SoC support The DA850/OMAP-L138 is a new SoC from TI in the same family as DA830/OMAP-L137. Major changes include better support for power management, support for SATA devices and McBSP (same IP as DM644x). DA850/OMAP-L138 documents are available at http://focus.ti.com/docs/prod/folders/print/omap-l138.html. Signed-off-by: Sudhakar Rajashekhara Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/cputype.h | 8 ++++ arch/arm/mach-davinci/include/mach/da8xx.h | 7 ++++ arch/arm/mach-davinci/include/mach/irqs.h | 63 ++++++++++++++++++++++++++-- arch/arm/mach-davinci/include/mach/mux.h | 28 +++++++++++++ arch/arm/mach-davinci/include/mach/psc.h | 3 ++ 5 files changed, 106 insertions(+), 3 deletions(-) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h index fd41189e5c62..189b1ff13642 100644 --- a/arch/arm/mach-davinci/include/mach/cputype.h +++ b/arch/arm/mach-davinci/include/mach/cputype.h @@ -32,6 +32,7 @@ struct davinci_id { #define DAVINCI_CPU_ID_DM355 0x03550000 #define DAVINCI_CPU_ID_DM365 0x03650000 #define DAVINCI_CPU_ID_DA830 0x08300000 +#define DAVINCI_CPU_ID_DA850 0x08500000 #define IS_DAVINCI_CPU(type, id) \ static inline int is_davinci_ ##type(void) \ @@ -44,6 +45,7 @@ IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467) IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355) IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365) IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830) +IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850) #ifdef CONFIG_ARCH_DAVINCI_DM644x #define cpu_is_davinci_dm644x() is_davinci_dm644x() @@ -75,4 +77,10 @@ IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830) #define cpu_is_davinci_da830() 0 #endif +#ifdef CONFIG_ARCH_DAVINCI_DA850 +#define cpu_is_davinci_da850() is_davinci_da850() +#else +#define cpu_is_davinci_da850() 0 +#endif + #endif diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 8c8dc135472c..594f9882e422 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -59,6 +59,7 @@ #define PINMUX19 0x4c void __init da830_init(void); +void __init da850_init(void); int da8xx_register_edma(void); int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); @@ -93,6 +94,12 @@ extern const short da830_ecap2_pins[]; extern const short da830_eqep0_pins[]; extern const short da830_eqep1_pins[]; +extern const short da850_uart0_pins[]; +extern const short da850_uart1_pins[]; +extern const short da850_uart2_pins[]; +extern const short da850_i2c0_pins[]; +extern const short da850_i2c1_pins[]; + int da8xx_pinmux_setup(const short pins[]); #endif /* __ASM_ARCH_DAVINCI_DA8XX_H */ diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h index 735e378d27ee..6047c2d9da33 100644 --- a/arch/arm/mach-davinci/include/mach/irqs.h +++ b/arch/arm/mach-davinci/include/mach/irqs.h @@ -340,9 +340,66 @@ #define DA830_N_CP_INTC_IRQ 96 -/* da830 currently has the most gpio pins (128) */ +/* DA850 speicific interrupts */ +#define IRQ_DA850_MPUADDRERR0 27 +#define IRQ_DA850_MPUPROTERR0 27 +#define IRQ_DA850_IOPUADDRERR0 27 +#define IRQ_DA850_IOPUPROTERR0 27 +#define IRQ_DA850_IOPUADDRERR1 27 +#define IRQ_DA850_IOPUPROTERR1 27 +#define IRQ_DA850_IOPUADDRERR2 27 +#define IRQ_DA850_IOPUPROTERR2 27 +#define IRQ_DA850_BOOTCFG_ADDR_ERR 27 +#define IRQ_DA850_BOOTCFG_PROT_ERR 27 +#define IRQ_DA850_MPUADDRERR1 27 +#define IRQ_DA850_MPUPROTERR1 27 +#define IRQ_DA850_IOPUADDRERR3 27 +#define IRQ_DA850_IOPUPROTERR3 27 +#define IRQ_DA850_IOPUADDRERR4 27 +#define IRQ_DA850_IOPUPROTERR4 27 +#define IRQ_DA850_IOPUADDRERR5 27 +#define IRQ_DA850_IOPUPROTERR5 27 +#define IRQ_DA850_MIOPU_BOOTCFG_ERR 27 +#define IRQ_DA850_SATAINT 67 +#define IRQ_DA850_TINT12_2 68 +#define IRQ_DA850_TINT34_2 68 +#define IRQ_DA850_TINTALL_2 68 +#define IRQ_DA850_MMCSDINT0_1 72 +#define IRQ_DA850_MMCSDINT1_1 73 +#define IRQ_DA850_T12CMPINT0_2 74 +#define IRQ_DA850_T12CMPINT1_2 75 +#define IRQ_DA850_T12CMPINT2_2 76 +#define IRQ_DA850_T12CMPINT3_2 77 +#define IRQ_DA850_T12CMPINT4_2 78 +#define IRQ_DA850_T12CMPINT5_2 79 +#define IRQ_DA850_T12CMPINT6_2 80 +#define IRQ_DA850_T12CMPINT7_2 81 +#define IRQ_DA850_T12CMPINT0_3 82 +#define IRQ_DA850_T12CMPINT1_3 83 +#define IRQ_DA850_T12CMPINT2_3 84 +#define IRQ_DA850_T12CMPINT3_3 85 +#define IRQ_DA850_T12CMPINT4_3 86 +#define IRQ_DA850_T12CMPINT5_3 87 +#define IRQ_DA850_T12CMPINT6_3 88 +#define IRQ_DA850_T12CMPINT7_3 89 +#define IRQ_DA850_RPIINT 91 +#define IRQ_DA850_VPIFINT 92 +#define IRQ_DA850_CCINT1 93 +#define IRQ_DA850_CCERRINT1 94 +#define IRQ_DA850_TCERRINT2 95 +#define IRQ_DA850_TINT12_3 96 +#define IRQ_DA850_TINT34_3 96 +#define IRQ_DA850_TINTALL_3 96 +#define IRQ_DA850_MCBSP0RINT 97 +#define IRQ_DA850_MCBSP0XINT 98 +#define IRQ_DA850_MCBSP1RINT 99 +#define IRQ_DA850_MCBSP1XINT 100 + +#define DA850_N_CP_INTC_IRQ 101 + +/* da830/da850 currently has the most gpio pins (128) */ #define DAVINCI_N_GPIO 128 -/* da830 currently has the most irqs so use DA830_N_CP_INTC_IRQ */ -#define NR_IRQS (DA830_N_CP_INTC_IRQ + DAVINCI_N_GPIO) +/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */ +#define NR_IRQS (DA850_N_CP_INTC_IRQ + DAVINCI_N_GPIO) #endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index cce7509ea302..3349fa5f82e1 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -704,6 +704,34 @@ enum da830_index { DA830_GPIO2_10, }; +enum davinci_da850_index { + /* UART0 function */ + DA850_NUART0_CTS, + DA850_NUART0_RTS, + DA850_UART0_RXD, + DA850_UART0_TXD, + + /* UART1 function */ + DA850_NUART1_CTS, + DA850_NUART1_RTS, + DA850_UART1_RXD, + DA850_UART1_TXD, + + /* UART2 function */ + DA850_NUART2_CTS, + DA850_NUART2_RTS, + DA850_UART2_RXD, + DA850_UART2_TXD, + + /* I2C1 function */ + DA850_I2C1_SCL, + DA850_I2C1_SDA, + + /* I2C0 function */ + DA850_I2C0_SDA, + DA850_I2C0_SCL, +}; + #ifdef CONFIG_DAVINCI_MUX /* setup pin muxing */ extern int davinci_cfg_reg(unsigned long reg_cfg); diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h index 6b9621d88284..171173c1dbad 100644 --- a/arch/arm/mach-davinci/include/mach/psc.h +++ b/arch/arm/mach-davinci/include/mach/psc.h @@ -155,6 +155,7 @@ #define DA8XX_LPSC0_GEM 15 /* PSC1 defines */ +#define DA850_LPSC1_TPCC1 0 #define DA8XX_LPSC1_USB20 1 #define DA8XX_LPSC1_USB11 2 #define DA8XX_LPSC1_GPIO 3 @@ -163,6 +164,7 @@ #define DA8XX_LPSC1_EMIF3C 6 #define DA8XX_LPSC1_McASP0 7 #define DA830_LPSC1_McASP1 8 +#define DA850_LPSC1_SATA 8 #define DA830_LPSC1_McASP2 9 #define DA8XX_LPSC1_SPI1 10 #define DA8XX_LPSC1_I2C 11 @@ -172,6 +174,7 @@ #define DA8XX_LPSC1_PWM 17 #define DA8XX_LPSC1_ECAP 20 #define DA830_LPSC1_EQEP 21 +#define DA850_LPSC1_TPTC2 21 #define DA8XX_LPSC1_SCR_P0_SS 24 #define DA8XX_LPSC1_SCR_P1_SS 25 #define DA8XX_LPSC1_CR_P3_SS 26 -- cgit v1.2.2 From 0fbc5592158db4e1ca2037178e1ea6733ccc6f61 Mon Sep 17 00:00:00 2001 From: Sudhakar Rajashekhara Date: Thu, 16 Jul 2009 06:42:18 -0400 Subject: davinci: Add support for DA850/OMAP-L138 EVM board Add support for the DA850/OMAP-L138 Evaluation Module (EVM) from TI. The EVM has User Interface (UI) card which contains various devices. This UI card can be connected to the base board. Support for all the devices on the UI card and ones on the EVM will be added in subsequent patches. The EVM schematics are not available publicly yet; but should be available soon. A new defconfig for this board has been added mainly because the DA830/OMAP-L137 defconfig forces writethrough cache mode which is not required on DA850/OMAP-L138. This patch has been boot tested on DA850/OMAP-L138 EVM using ramdisk as filesystem. Signed-off-by: Sudhakar Rajashekhara Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/debug-macro.S | 3 ++- arch/arm/mach-davinci/include/mach/uncompress.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S index 9d16277b233f..17ab5236da66 100644 --- a/arch/arm/mach-davinci/include/mach/debug-macro.S +++ b/arch/arm/mach-davinci/include/mach/debug-macro.S @@ -26,7 +26,8 @@ movne \rx, #0xfe000000 @ virtual base #if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx) #error Cannot enable DaVinci and DA8XX platforms concurrently -#elif defined(CONFIG_MACH_DAVINCI_DA830_EVM) +#elif defined(CONFIG_MACH_DAVINCI_DA830_EVM) || \ + defined(CONFIG_MACH_DAVINCI_DA850_EVM) orr \rx, \rx, #0x00d00000 @ physical base address orr \rx, \rx, #0x0000d000 @ of UART 2 #else diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h index 46a0c3171e35..33796b4db17f 100644 --- a/arch/arm/mach-davinci/include/mach/uncompress.h +++ b/arch/arm/mach-davinci/include/mach/uncompress.h @@ -21,7 +21,8 @@ static u32 *uart; static u32 *get_uart_base(void) { - if (__machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM) + if (__machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM || + __machine_arch_type == MACH_TYPE_DAVINCI_DA850_EVM) return (u32 *)DA8XX_UART2_BASE; else return (u32 *)DAVINCI_UART0_BASE; -- cgit v1.2.2 From 5a4b131508236c0a59b8680f486c49e31881fe4e Mon Sep 17 00:00:00 2001 From: Sudhakar Rajashekhara Date: Fri, 17 Jul 2009 04:47:10 -0400 Subject: davinci: Add EMAC support for da850/omap-l138 Ethernet Media Access Controller (EMAC) on da850/omap-l138 supports 10/100 Mbps operation. It also supports Media Independent Interface (MII) and Reduced Media Independent Interface (RMII) to physical layer (PHY). Phy which supports MII is present on the DA850/OMAP-L138 base board and Phy supporting RMII is present on the UI card. This patch adds support only for the MII Phy. Support for RMII Phy will be added later. Signed-off-by: Sudhakar Rajashekhara Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/da8xx.h | 1 + arch/arm/mach-davinci/include/mach/mux.h | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 594f9882e422..a8cb5709848d 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -99,6 +99,7 @@ extern const short da850_uart1_pins[]; extern const short da850_uart2_pins[]; extern const short da850_i2c0_pins[]; extern const short da850_i2c1_pins[]; +extern const short da850_cpgmac_pins[]; int da8xx_pinmux_setup(const short pins[]); diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index 3349fa5f82e1..368fca69197d 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -730,6 +730,23 @@ enum davinci_da850_index { /* I2C0 function */ DA850_I2C0_SDA, DA850_I2C0_SCL, + + /* EMAC function */ + DA850_MII_TXEN, + DA850_MII_TXCLK, + DA850_MII_COL, + DA850_MII_TXD_3, + DA850_MII_TXD_2, + DA850_MII_TXD_1, + DA850_MII_TXD_0, + DA850_MII_RXER, + DA850_MII_CRS, + DA850_MII_RXCLK, + DA850_MII_RXDV, + DA850_MII_RXD_3, + DA850_MII_RXD_2, + DA850_MII_RXD_1, + DA850_MII_RXD_0, }; #ifdef CONFIG_DAVINCI_MUX -- cgit v1.2.2 From 61aa07328d8e70d95a1e2325288df52a1e92a694 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Wed, 15 Jul 2009 08:47:48 -0700 Subject: davinci: audio clocks: use struct device instead of clock names There is no need to pass clock name strings in platform_data. Instead, setup clkdev nodes to have correct ASoC device names. Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/asp.h | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h index 038ecb7c231b..cdf1f4442330 100644 --- a/arch/arm/mach-davinci/include/mach/asp.h +++ b/arch/arm/mach-davinci/include/mach/asp.h @@ -33,7 +33,6 @@ #define DAVINCI_ASP1_TX_INT IRQ_MBXINT struct snd_platform_data { - char *clk_name; u32 tx_dma_offset; u32 rx_dma_offset; enum dma_event_q eventq_no; /* event queue number */ -- cgit v1.2.2 From 10eef5a8a08d8be455ae5f9599b214c33ad52340 Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Mon, 27 Jul 2009 08:50:16 -0400 Subject: DaVinci: EDMA: Add queue 2 and 3 for DM365 and DM6467 DM365 and DM6467 have 4 queues. The patch updates the 'dma_event_q' enum to reflect this. Signed-off-by: Sandeep Paulraj Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/edma.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h index a85cbedc9b0a..5d4896226460 100644 --- a/arch/arm/mach-davinci/include/mach/edma.h +++ b/arch/arm/mach-davinci/include/mach/edma.h @@ -210,6 +210,8 @@ enum fifo_width { enum dma_event_q { EVENTQ_0 = 0, EVENTQ_1 = 1, + EVENTQ_2 = 2, + EVENTQ_3 = 3, EVENTQ_DEFAULT = -1 }; -- cgit v1.2.2 From a0f0202e2a19d43d733e07cb435a3064324c2ba7 Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Mon, 27 Jul 2009 09:57:07 -0400 Subject: DaVinci: EDMA: Updating default queue handling EDMA queues in DM365 are a little different than those on other DaVinci's. On DM365 Q0 and Q1 have the larger FIFO size. We want Q0 and Q1 to be used by codecs and DVSDK demos. MMC driver is the only driver which uses the flag 'EVENTQ_DEFAULT'. So MMC driver should be using Q2 instead of Q1 on DM365. This patch allows us to declare a "default queue" from SOC specific code. If it is not declared then the EDMA driver assumes a default of queue 1. Signed-off-by: Sandeep Paulraj Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/edma.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h index 5d4896226460..3c7dc2db70e4 100644 --- a/arch/arm/mach-davinci/include/mach/edma.h +++ b/arch/arm/mach-davinci/include/mach/edma.h @@ -271,6 +271,7 @@ struct edma_soc_info { unsigned n_slot; unsigned n_tc; unsigned n_cc; + enum dma_event_q default_queue; /* list of channels with no even trigger; terminated by "-1" */ const s8 *noevent; -- cgit v1.2.2 From 866d286953c359e7b1fc0b8d04254d144a11be68 Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Mon, 3 Aug 2009 13:58:24 -0400 Subject: DaVinci: DM365: Fix Compilation issue due to PINMUX entry The mask can hold only 8 bit values. This gave a compilation warning. This patch rectifies the warning. Signed-off-by: Sandeep Paulraj Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/mux.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index 368fca69197d..a676b2f47aab 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -280,7 +280,8 @@ enum davinci_dm365_index { DM365_VIN_CAM_WEN, DM365_VIN_CAM_VD, DM365_VIN_CAM_HD, - DM365_VIN_YIN_EN, + DM365_VIN_YIN4_7_EN, + DM365_VIN_YIN0_3_EN, /* IRQ muxing */ DM365_INT_EDMA_CC, -- cgit v1.2.2 From 53ca5c916971f72262ef37287e17f0a7d980362c Mon Sep 17 00:00:00 2001 From: Sudhakar Rajashekhara Date: Tue, 11 Aug 2009 11:10:50 -0400 Subject: davinci: Configure MDIO pins for EMAC Earlier patch which adds EMAC support for da850/omap-l138 was not configuring the MDIO pins. Ethernet was working fine with the earlier patch, because the MDIO pins were configured from the boot loader. This patch removes that dependency. Also, this patch populates a member in the emac clk structure to say that EMAC LPSC sits on controller 1. Signed-off-by: Sudhakar Rajashekhara Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/mux.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index a676b2f47aab..8676680fc5b6 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -748,6 +748,8 @@ enum davinci_da850_index { DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, + DA850_MDIO_CLK, + DA850_MDIO_D, }; #ifdef CONFIG_DAVINCI_MUX -- cgit v1.2.2 From 5a8d5441f4aac3ef0478d5de723422304c611926 Mon Sep 17 00:00:00 2001 From: Sudhakar Rajashekhara Date: Tue, 11 Aug 2009 16:14:21 -0400 Subject: davinci: Correct the number of GPIO pins for da850/omap-l138 DA850/OMAP-L138 has 144 pins configurable as GPIO, but currently this has been configured as 128. This patch corrects it. Also, this patch adds the base address for GPIO pins greater than 128. Signed-off-by: Sudhakar Rajashekhara Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/gpio.h | 2 ++ arch/arm/mach-davinci/include/mach/irqs.h | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h index ebcc29babeae..4f032b38cd6e 100644 --- a/arch/arm/mach-davinci/include/mach/gpio.h +++ b/arch/arm/mach-davinci/include/mach/gpio.h @@ -78,6 +78,8 @@ __gpio_to_controller(unsigned gpio) ptr = base + 0x60; else if (gpio < 32 * 4) ptr = base + 0x88; + else if (gpio < 32 * 5) + ptr = base + 0xb0; else ptr = NULL; return ptr; diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h index 6047c2d9da33..7f755cc387e5 100644 --- a/arch/arm/mach-davinci/include/mach/irqs.h +++ b/arch/arm/mach-davinci/include/mach/irqs.h @@ -397,8 +397,8 @@ #define DA850_N_CP_INTC_IRQ 101 -/* da830/da850 currently has the most gpio pins (128) */ -#define DAVINCI_N_GPIO 128 +/* da850 currently has the most gpio pins (144) */ +#define DAVINCI_N_GPIO 144 /* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */ #define NR_IRQS (DA850_N_CP_INTC_IRQ + DAVINCI_N_GPIO) -- cgit v1.2.2 From e33ef5e3b368b31705d3024ee6a326f2a85a78fb Mon Sep 17 00:00:00 2001 From: Chaithrika U S Date: Tue, 11 Aug 2009 17:01:59 -0400 Subject: davinci: Audio support for DA830 EVM Define resources for McASP1 used on DA830/OMAP-L137 EVM, add platform device defintion, initialization function. Additionally, this patch also adds version and FIFO related members to platform data structure. Signed-off-by: Chaithrika U S Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/asp.h | 15 +++++++++++++++ arch/arm/mach-davinci/include/mach/da8xx.h | 3 +++ 2 files changed, 18 insertions(+) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h index cdf1f4442330..f3c97ac3425c 100644 --- a/arch/arm/mach-davinci/include/mach/asp.h +++ b/arch/arm/mach-davinci/include/mach/asp.h @@ -15,6 +15,9 @@ #define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000 #define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800 +/* Bases of da830 McASP1 register banks */ +#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000 + /* EDMA channels of dm644x and dm355 */ #define DAVINCI_DMA_ASP0_TX 2 #define DAVINCI_DMA_ASP0_RX 3 @@ -26,6 +29,10 @@ #define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9 #define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12 +/* EDMA channels of da830 McASP1 */ +#define DAVINCI_DA830_DMA_MCASP1_AREVT 2 +#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3 + /* Interrupts */ #define DAVINCI_ASP0_RX_INT IRQ_MBRINT #define DAVINCI_ASP0_TX_INT IRQ_MBXINT @@ -43,6 +50,14 @@ struct snd_platform_data { u8 op_mode; u8 num_serializer; u8 *serial_dir; + u8 version; + u8 txnumevt; + u8 rxnumevt; +}; + +enum { + MCASP_VERSION_1 = 0, /* DM646x */ + MCASP_VERSION_2, /* DA8xx/OMAPL1x */ }; #define INACTIVE_MODE 0 diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index a8cb5709848d..30c5c407ea85 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -15,6 +15,7 @@ #include #include #include +#include /* * The cp_intc interrupt controller for the da8xx isn't in the same @@ -65,6 +66,7 @@ int da8xx_register_edma(void); int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); int da8xx_register_watchdog(void); int da8xx_register_emac(void); +void __init da8xx_init_mcasp(int id, struct snd_platform_data *pdata); extern struct platform_device da8xx_serial_device; extern struct emac_platform_data da8xx_emac_pdata; @@ -100,6 +102,7 @@ extern const short da850_uart2_pins[]; extern const short da850_i2c0_pins[]; extern const short da850_i2c1_pins[]; extern const short da850_cpgmac_pins[]; +extern const short da850_mcasp_pins[]; int da8xx_pinmux_setup(const short pins[]); -- cgit v1.2.2 From 491214e1f8129844289869bb6c231dc4542b11e3 Mon Sep 17 00:00:00 2001 From: Chaithrika U S Date: Tue, 11 Aug 2009 17:03:25 -0400 Subject: davinci: Audio support for DA850/OMAP-L138 EVM Define resources for McASP used on DA850/OMAP-L138 EVM, add platform device defintion and Pin Mux configurations. Signed-off-by: Chaithrika U S Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/asp.h | 7 +++++++ arch/arm/mach-davinci/include/mach/mux.h | 25 +++++++++++++++++++++++++ 2 files changed, 32 insertions(+) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h index f3c97ac3425c..18e4ce34ece6 100644 --- a/arch/arm/mach-davinci/include/mach/asp.h +++ b/arch/arm/mach-davinci/include/mach/asp.h @@ -15,6 +15,9 @@ #define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000 #define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800 +/* Bases of da850/da830 McASP0 register banks */ +#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000 + /* Bases of da830 McASP1 register banks */ #define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000 @@ -29,6 +32,10 @@ #define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9 #define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12 +/* EDMA channels of da850/da830 McASP0 */ +#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0 +#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1 + /* EDMA channels of da830 McASP1 */ #define DAVINCI_DA830_DMA_MCASP1_AREVT 2 #define DAVINCI_DA830_DMA_MCASP1_AXEVT 3 diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index 8676680fc5b6..82d751461856 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -750,6 +750,31 @@ enum davinci_da850_index { DA850_MII_RXD_0, DA850_MDIO_CLK, DA850_MDIO_D, + + /* McASP function */ + DA850_ACLKR, + DA850_ACLKX, + DA850_AFSR, + DA850_AFSX, + DA850_AHCLKR, + DA850_AHCLKX, + DA850_AMUTE, + DA850_AXR_15, + DA850_AXR_14, + DA850_AXR_13, + DA850_AXR_12, + DA850_AXR_11, + DA850_AXR_10, + DA850_AXR_9, + DA850_AXR_8, + DA850_AXR_7, + DA850_AXR_6, + DA850_AXR_5, + DA850_AXR_4, + DA850_AXR_3, + DA850_AXR_2, + DA850_AXR_1, + DA850_AXR_0, }; #ifdef CONFIG_DAVINCI_MUX -- cgit v1.2.2 From b1466376b22e1ec6395ccda7580deb72d3a809ad Mon Sep 17 00:00:00 2001 From: Sudhakar Rajashekhara Date: Thu, 13 Aug 2009 12:11:56 -0400 Subject: davinci: Macro to convert GPIO signal to GPIO pin number Adds a macro to convert the GPIO signal passed as bank number and signal to GPIO pin number. Signed-off-by: Sudhakar Rajashekhara Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/gpio.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h index 4f032b38cd6e..f3b8ef878158 100644 --- a/arch/arm/mach-davinci/include/mach/gpio.h +++ b/arch/arm/mach-davinci/include/mach/gpio.h @@ -42,6 +42,9 @@ */ #define GPIO(X) (X) /* 0 <= X <= (DAVINCI_N_GPIO - 1) */ +/* Convert GPIO signal to GPIO pin number */ +#define GPIO_TO_PIN(bank, gpio) (16 * (bank) + (gpio)) + struct gpio_controller { u32 dir; u32 out_data; -- cgit v1.2.2 From 5cbdf276bd9d9cd3cb9616f8253390096c1a237f Mon Sep 17 00:00:00 2001 From: Sudhakar Rajashekhara Date: Thu, 13 Aug 2009 14:33:14 -0400 Subject: davinci: Add platform support for da850/omap-l138 GLCD This patch adds platform support for the graphic display (Sharp LK043T1DG01) found on DA850/OMAP-L138 based EVM. Signed-off-by: Sudhakar Rajashekhara Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/da8xx.h | 3 +++ arch/arm/mach-davinci/include/mach/mux.h | 26 ++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 30c5c407ea85..0af3fb6077a3 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -37,6 +37,7 @@ #define DA8XX_TIMER64P1_BASE 0x01c21000 #define DA8XX_GPIO_BASE 0x01e26000 #define DA8XX_PSC1_BASE 0x01e27000 +#define DA8XX_LCD_CNTRL_BASE 0x01e13000 #define PINMUX0 0x00 #define PINMUX1 0x04 @@ -66,6 +67,7 @@ int da8xx_register_edma(void); int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); int da8xx_register_watchdog(void); int da8xx_register_emac(void); +int da8xx_register_lcdc(void); void __init da8xx_init_mcasp(int id, struct snd_platform_data *pdata); extern struct platform_device da8xx_serial_device; @@ -103,6 +105,7 @@ extern const short da850_i2c0_pins[]; extern const short da850_i2c1_pins[]; extern const short da850_cpgmac_pins[]; extern const short da850_mcasp_pins[]; +extern const short da850_lcdcntl_pins[]; int da8xx_pinmux_setup(const short pins[]); diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index 82d751461856..30bf329d5373 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -775,6 +775,32 @@ enum davinci_da850_index { DA850_AXR_2, DA850_AXR_1, DA850_AXR_0, + + /* LCD function */ + DA850_LCD_D_7, + DA850_LCD_D_6, + DA850_LCD_D_5, + DA850_LCD_D_4, + DA850_LCD_D_3, + DA850_LCD_D_2, + DA850_LCD_D_1, + DA850_LCD_D_0, + DA850_LCD_D_15, + DA850_LCD_D_14, + DA850_LCD_D_13, + DA850_LCD_D_12, + DA850_LCD_D_11, + DA850_LCD_D_10, + DA850_LCD_D_9, + DA850_LCD_D_8, + DA850_LCD_PCLK, + DA850_LCD_HSYNC, + DA850_LCD_VSYNC, + DA850_NLCD_AC_ENB_CS, + + /* GPIO function */ + DA850_GPIO2_15, + DA850_GPIO8_10, }; #ifdef CONFIG_DAVINCI_MUX -- cgit v1.2.2 From 700691f27ed9b0891cece9032e4de8c0b482c625 Mon Sep 17 00:00:00 2001 From: Sudhakar Rajashekhara Date: Thu, 13 Aug 2009 15:16:23 -0400 Subject: davinci: Add MMC/SD support for da850/omap-l138 There are two instances of MMC/SD on da850/omap-l138. Connector for the first instance is available on the EVM. This patch adds support for this instance. This patch also adds support for card detect and write protect switches on da850/omap-l138 EVM. Signed-off-by: Sudhakar Rajashekhara Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/da8xx.h | 4 ++++ arch/arm/mach-davinci/include/mach/mux.h | 10 ++++++++++ 2 files changed, 14 insertions(+) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 0af3fb6077a3..0af141ffc3b4 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -16,6 +16,7 @@ #include #include #include +#include /* * The cp_intc interrupt controller for the da8xx isn't in the same @@ -38,6 +39,7 @@ #define DA8XX_GPIO_BASE 0x01e26000 #define DA8XX_PSC1_BASE 0x01e27000 #define DA8XX_LCD_CNTRL_BASE 0x01e13000 +#define DA8XX_MMCSD0_BASE 0x01c40000 #define PINMUX0 0x00 #define PINMUX1 0x04 @@ -68,6 +70,7 @@ int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); int da8xx_register_watchdog(void); int da8xx_register_emac(void); int da8xx_register_lcdc(void); +int da8xx_register_mmcsd0(struct davinci_mmc_config *config); void __init da8xx_init_mcasp(int id, struct snd_platform_data *pdata); extern struct platform_device da8xx_serial_device; @@ -106,6 +109,7 @@ extern const short da850_i2c1_pins[]; extern const short da850_cpgmac_pins[]; extern const short da850_mcasp_pins[]; extern const short da850_lcdcntl_pins[]; +extern const short da850_mmcsd0_pins[]; int da8xx_pinmux_setup(const short pins[]); diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index 30bf329d5373..b2335640c222 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -798,9 +798,19 @@ enum davinci_da850_index { DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS, + /* MMC/SD0 function */ + DA850_MMCSD0_DAT_0, + DA850_MMCSD0_DAT_1, + DA850_MMCSD0_DAT_2, + DA850_MMCSD0_DAT_3, + DA850_MMCSD0_CLK, + DA850_MMCSD0_CMD, + /* GPIO function */ DA850_GPIO2_15, DA850_GPIO8_10, + DA850_GPIO4_0, + DA850_GPIO4_1, }; #ifdef CONFIG_DAVINCI_MUX -- cgit v1.2.2 From 38beb929f2c33a37bf3af6103c064a9edfbe242b Mon Sep 17 00:00:00 2001 From: Sudhakar Rajashekhara Date: Thu, 13 Aug 2009 16:21:11 -0400 Subject: davinci: Add NAND flash support for DA850/OMAP-L138 This patch adds platform data for the 512MB NAND Flash found on DA850/OMAP-L138 EVM. Currently it supports only 1-bit ECC. Signed-off-by: Sudhakar Rajashekhara Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/da8xx.h | 3 +++ arch/arm/mach-davinci/include/mach/mux.h | 16 ++++++++++++++++ 2 files changed, 19 insertions(+) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 0af141ffc3b4..77e5d2398e21 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -40,6 +40,8 @@ #define DA8XX_PSC1_BASE 0x01e27000 #define DA8XX_LCD_CNTRL_BASE 0x01e13000 #define DA8XX_MMCSD0_BASE 0x01c40000 +#define DA8XX_AEMIF_CS3_BASE 0x62000000 +#define DA8XX_AEMIF_CTL_BASE 0x68000000 #define PINMUX0 0x00 #define PINMUX1 0x04 @@ -110,6 +112,7 @@ extern const short da850_cpgmac_pins[]; extern const short da850_mcasp_pins[]; extern const short da850_lcdcntl_pins[]; extern const short da850_mmcsd0_pins[]; +extern const short da850_nand_pins[]; int da8xx_pinmux_setup(const short pins[]); diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index b2335640c222..ee6f29db4452 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -806,6 +806,22 @@ enum davinci_da850_index { DA850_MMCSD0_CLK, DA850_MMCSD0_CMD, + /* EMIF2.5/EMIFA function */ + DA850_EMA_D_7, + DA850_EMA_D_6, + DA850_EMA_D_5, + DA850_EMA_D_4, + DA850_EMA_D_3, + DA850_EMA_D_2, + DA850_EMA_D_1, + DA850_EMA_D_0, + DA850_EMA_A_1, + DA850_EMA_A_2, + DA850_NEMA_CS_3, + DA850_NEMA_CS_4, + DA850_NEMA_WE, + DA850_NEMA_OE, + /* GPIO function */ DA850_GPIO2_15, DA850_GPIO8_10, -- cgit v1.2.2 From 7c5ec6095a7d29c89ee050281faa068a374a5ac6 Mon Sep 17 00:00:00 2001 From: Sudhakar Rajashekhara Date: Thu, 13 Aug 2009 17:36:25 -0400 Subject: davinci: Add NOR flash support for da850/omap-l138 This patch adds platform data for the 8MB NOR flash found on da850/omap-l138 EVM. Both NOR and NAND can co-exist on da850/omap-l138 as they are using different chip selects. Signed-off-by: Sudhakar Rajashekhara Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/da8xx.h | 2 ++ arch/arm/mach-davinci/include/mach/mux.h | 34 ++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 77e5d2398e21..d4095d0572c6 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -40,6 +40,7 @@ #define DA8XX_PSC1_BASE 0x01e27000 #define DA8XX_LCD_CNTRL_BASE 0x01e13000 #define DA8XX_MMCSD0_BASE 0x01c40000 +#define DA8XX_AEMIF_CS2_BASE 0x60000000 #define DA8XX_AEMIF_CS3_BASE 0x62000000 #define DA8XX_AEMIF_CTL_BASE 0x68000000 @@ -113,6 +114,7 @@ extern const short da850_mcasp_pins[]; extern const short da850_lcdcntl_pins[]; extern const short da850_mmcsd0_pins[]; extern const short da850_nand_pins[]; +extern const short da850_nor_pins[]; int da8xx_pinmux_setup(const short pins[]); diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index ee6f29db4452..88cd22af4946 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -821,6 +821,40 @@ enum davinci_da850_index { DA850_NEMA_CS_4, DA850_NEMA_WE, DA850_NEMA_OE, + DA850_EMA_D_15, + DA850_EMA_D_14, + DA850_EMA_D_13, + DA850_EMA_D_12, + DA850_EMA_D_11, + DA850_EMA_D_10, + DA850_EMA_D_9, + DA850_EMA_D_8, + DA850_EMA_A_0, + DA850_EMA_A_3, + DA850_EMA_A_4, + DA850_EMA_A_5, + DA850_EMA_A_6, + DA850_EMA_A_7, + DA850_EMA_A_8, + DA850_EMA_A_9, + DA850_EMA_A_10, + DA850_EMA_A_11, + DA850_EMA_A_12, + DA850_EMA_A_13, + DA850_EMA_A_14, + DA850_EMA_A_15, + DA850_EMA_A_16, + DA850_EMA_A_17, + DA850_EMA_A_18, + DA850_EMA_A_19, + DA850_EMA_A_20, + DA850_EMA_A_21, + DA850_EMA_A_22, + DA850_EMA_A_23, + DA850_EMA_BA_1, + DA850_EMA_CLK, + DA850_EMA_WAIT_1, + DA850_NEMA_CS_2, /* GPIO function */ DA850_GPIO2_15, -- cgit v1.2.2 From 1aebb50e06b8c184dcf1dde4314cb782f42f9e21 Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Fri, 21 Aug 2009 12:38:11 -0400 Subject: DaVinci: DM355: Adding PINMUX entries for DM355 Display This patch adds PINMUX entries for DM355 Display. These will be used by the DM355 display driver. Signed-off-by: Sandeep Paulraj Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/mux.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index 88cd22af4946..7fad9b1a106b 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -154,6 +154,13 @@ enum davinci_dm355_index { DM355_EVT8_ASP1_TX, DM355_EVT9_ASP1_RX, DM355_EVT26_MMC0_RX, + + /* Video Out */ + DM355_VOUT_FIELD, + DM355_VOUT_FIELD_G70, + DM355_VOUT_HVSYNC, + DM355_VOUT_COUTL_EN, + DM355_VOUT_COUTH_EN, }; enum davinci_dm365_index { -- cgit v1.2.2 From 0c30e0d31b57375b1decad4cc0e139e2f7758986 Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Tue, 18 Aug 2009 11:08:27 -0400 Subject: DaVinci: DM365: Adding entries for DM365 IRQ's This patch adds definitions for some DM365 IRQs that are used by the codecs. Codecs will also use the IRQs. Entries are being added to enable/disable IRQ's. There is no use as such for these entires in the kernel itself. Instead these will be used by the "linuxutils" package of the DVSDK. For further information on IRQ muxing refer to http://focus.ti.com/lit/ug/sprufg5a/sprufg5a.pdf Signed-off-by: Sandeep Paulraj Signed-off-by: Sneha Narnakaje Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/irqs.h | 3 +++ arch/arm/mach-davinci/include/mach/mux.h | 8 ++++++++ 2 files changed, 11 insertions(+) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h index 7f755cc387e5..3c918a772619 100644 --- a/arch/arm/mach-davinci/include/mach/irqs.h +++ b/arch/arm/mach-davinci/include/mach/irqs.h @@ -205,6 +205,9 @@ /* DaVinci DM365-specific Interrupts */ #define IRQ_DM365_INSFINT 7 +#define IRQ_DM365_IMXINT1 8 +#define IRQ_DM365_IMXINT0 10 +#define IRQ_DM365_KLD_ARMINT 10 #define IRQ_DM365_IMCOPINT 11 #define IRQ_DM365_RTOINT 13 #define IRQ_DM365_TINT5 14 diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index 7fad9b1a106b..773283281be8 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -301,6 +301,14 @@ enum davinci_dm365_index { DM365_INT_EMAC_RXPULSE, DM365_INT_EMAC_TXPULSE, DM365_INT_EMAC_MISCPULSE, + DM365_INT_IMX0_ENABLE, + DM365_INT_IMX0_DISABLE, + DM365_INT_HDVICP_ENABLE, + DM365_INT_HDVICP_DISABLE, + DM365_INT_IMX1_ENABLE, + DM365_INT_IMX1_DISABLE, + DM365_INT_NSF_ENABLE, + DM365_INT_NSF_DISABLE, /* EDMA event muxing */ DM365_EVT2_ASP_TX, -- cgit v1.2.2 From 213765d7b40a455ced8596edfa3cc51b5f69d515 Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Mon, 27 Jul 2009 15:10:36 -0400 Subject: DaVinci: EDMA: Adding 2 new APIs for allocating/freeing PARAMs For best performance, codecs often setup linked triggered transfers with a contiguous block of params, and that is when this API is used. Setup/configuration of these parameter RAMs is most efficient if they are contiguous. There is an API to allocate a set of contiguous parameter RAMs and a corresponding API to free a set of contiguous parameter RAMs Signed-off-by: Sandeep Paulraj Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/edma.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h index 3c7dc2db70e4..eb8bfd7925e7 100644 --- a/arch/arm/mach-davinci/include/mach/edma.h +++ b/arch/arm/mach-davinci/include/mach/edma.h @@ -226,6 +226,9 @@ enum sync_dimension { #define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ #define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ +#define EDMA_CONT_PARAMS_ANY 1001 +#define EDMA_CONT_PARAMS_FIXED_EXACT 1002 +#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003 /* alloc/free DMA channels and their dedicated parameter RAM slots */ int edma_alloc_channel(int channel, @@ -237,6 +240,10 @@ void edma_free_channel(unsigned channel); int edma_alloc_slot(unsigned ctlr, int slot); void edma_free_slot(unsigned slot); +/* alloc/free a set of contiguous parameter RAM slots */ +int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count); +int edma_free_cont_slots(unsigned slot, int count); + /* calls that operate on part of a parameter RAM slot */ void edma_set_src(unsigned slot, dma_addr_t src_port, enum address_mode mode, enum fifo_width); -- cgit v1.2.2 From ab8e8df87421574fe053bf1770353af5b24a2bbb Mon Sep 17 00:00:00 2001 From: Muralidharan Karicheri Date: Wed, 16 Sep 2009 11:53:18 -0400 Subject: davinci: DM644x platform changes for vpfe capture DM644x platform and board setup This adds platform and board setup changes required to support vpfe capture driver on DM644x Tested video capture on DM6446 with tvp514x driver Reviewed-by: Hans Verkuil Reviewed-by: Laurent Pinchart Reviewed-by: David Brownell Signed-off-by: Muralidharan Karicheri Signed-off-by: Denys Dmytriyenko Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/dm644x.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h index 8b157ceec0ca..0efb73852c2c 100644 --- a/arch/arm/mach-davinci/include/mach/dm644x.h +++ b/arch/arm/mach-davinci/include/mach/dm644x.h @@ -26,6 +26,7 @@ #include #include #include +#include #define DM644X_EMAC_BASE (0x01C80000) #define DM644X_EMAC_CNTRL_OFFSET (0x0000) @@ -36,5 +37,6 @@ void __init dm644x_init(void); void __init dm644x_init_asp(struct snd_platform_data *pdata); +void dm644x_set_vpfe_config(struct vpfe_config *cfg); #endif /* __ASM_ARCH_DM644X_H */ -- cgit v1.2.2 From 51e68e27d310034332b67a6762914af9589b3db5 Mon Sep 17 00:00:00 2001 From: Muralidharan Karicheri Date: Wed, 16 Sep 2009 12:02:50 -0400 Subject: davinci: DM355 - platform changes for vpfe capture DM355 platform and board setup This has platform and board setup changes to support vpfe capture driver for DM355 EVMs. Tested video capture on DM355 using tvp514x Reviewed-by: Hans Verkuil Reviewed-by: Laurent Pinchart Reviewed-by: David Brownell Signed-off-by: Muralidharan Karicheri Signed-off-by: Denys Dmytriyenko Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/dm355.h | 2 ++ arch/arm/mach-davinci/include/mach/mux.h | 9 +++++++++ 2 files changed, 11 insertions(+) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/dm355.h b/arch/arm/mach-davinci/include/mach/dm355.h index 03faaef95a9a..85536d8e8336 100644 --- a/arch/arm/mach-davinci/include/mach/dm355.h +++ b/arch/arm/mach-davinci/include/mach/dm355.h @@ -13,6 +13,7 @@ #include #include +#include #define ASP1_TX_EVT_EN 1 #define ASP1_RX_EVT_EN 2 @@ -23,5 +24,6 @@ void __init dm355_init(void); void dm355_init_spi0(unsigned chipselect_mask, struct spi_board_info *info, unsigned len); void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata); +void dm355_set_vpfe_config(struct vpfe_config *cfg); #endif /* __ASM_ARCH_DM355_H */ diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index 773283281be8..bb84893a4e83 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -161,6 +161,15 @@ enum davinci_dm355_index { DM355_VOUT_HVSYNC, DM355_VOUT_COUTL_EN, DM355_VOUT_COUTH_EN, + + /* Video In Pin Mux */ + DM355_VIN_PCLK, + DM355_VIN_CAM_WEN, + DM355_VIN_CAM_VD, + DM355_VIN_CAM_HD, + DM355_VIN_YIN_EN, + DM355_VIN_CINL_EN, + DM355_VIN_CINH_EN, }; enum davinci_dm365_index { -- cgit v1.2.2 From 85609c1ccda64af7d7c277469183f20e4f3b69c3 Mon Sep 17 00:00:00 2001 From: Muralidharan Karicheri Date: Wed, 16 Sep 2009 13:15:30 -0400 Subject: DaVinci: DM646x - platform changes for vpif capture and display drivers VPIF display changes (Chaithrika) Add platform device and resource structures. Also define a platform specific clock setup function that can be accessed by the driver to configure the clock and CPLD. VPIF caputure changes (Murali) 1) Modify vpif_subdev_info to add board_info, routing information and vpif interface configuration. Remove addr since it is part of board_info 2) Add code to setup channel mode and input decoder path for vpif capture driver Also incorporated comments against version v0 of the patch series and added a spinlock to protect writes to common registers Tested on DM6467 on channel 0 using TVP514x. Following bootargs used for drivers: vpif_capture.ch0_bufsize=829440 vpif_display.ch2_bufsize=829440 Signed-off-by: Manjunath Hadli Signed-off-by: Brijesh Jadav Signed-off-by: Chaithrika U S Reviewed-by: Hans Verkuil Signed-off-by: Muralidharan Karicheri Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/dm646x.h | 59 +++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) (limited to 'arch/arm/mach-davinci/include') diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h index feb1e02cdbd8..8cec746ae9d2 100644 --- a/arch/arm/mach-davinci/include/mach/dm646x.h +++ b/arch/arm/mach-davinci/include/mach/dm646x.h @@ -14,6 +14,8 @@ #include #include #include +#include +#include #define DM646X_EMAC_BASE (0x01C80000) #define DM646X_EMAC_CNTRL_OFFSET (0x0000) @@ -29,4 +31,61 @@ void __init dm646x_init_ide(void); void __init dm646x_init_mcasp0(struct snd_platform_data *pdata); void __init dm646x_init_mcasp1(struct snd_platform_data *pdata); +void dm646x_video_init(void); + +enum vpif_if_type { + VPIF_IF_BT656, + VPIF_IF_BT1120, + VPIF_IF_RAW_BAYER +}; + +struct vpif_interface { + enum vpif_if_type if_type; + unsigned hd_pol:1; + unsigned vd_pol:1; + unsigned fid_pol:1; +}; + +struct vpif_subdev_info { + const char *name; + struct i2c_board_info board_info; + u32 input; + u32 output; + unsigned can_route:1; + struct vpif_interface vpif_if; +}; + +struct vpif_display_config { + int (*set_clock)(int, int); + struct vpif_subdev_info *subdevinfo; + int subdev_count; + const char **output; + int output_count; + const char *card_name; +}; + +struct vpif_input { + struct v4l2_input input; + const char *subdev_name; +}; + +#define VPIF_CAPTURE_MAX_CHANNELS 2 + +struct vpif_capture_chan_config { + const struct vpif_input *inputs; + int input_count; +}; + +struct vpif_capture_config { + int (*setup_input_channel_mode)(int); + int (*setup_input_path)(int, const char *); + struct vpif_capture_chan_config chan_config[VPIF_CAPTURE_MAX_CHANNELS]; + struct vpif_subdev_info *subdev_info; + int subdev_count; + const char *card_name; +}; + +void dm646x_setup_vpif(struct vpif_display_config *, + struct vpif_capture_config *); + #endif /* __ASM_ARCH_DM646X_H */ -- cgit v1.2.2