From 38e64ba0f13918d11e50bbd5bb775781ccd6439d Mon Sep 17 00:00:00 2001 From: Mac Lin Date: Tue, 23 Nov 2010 00:32:43 +0800 Subject: ARM: cns3xxx: Add new and export the old power management functions This patch adds cns3xxx_pwr_clk_dis, and exports these power management functions that may be used by many other device drivers on CNS3XXX. Signed-off-by: Mac Lin Signed-off-by: Anton Vorontsov --- arch/arm/mach-cns3xxx/include/mach/pm.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 arch/arm/mach-cns3xxx/include/mach/pm.h (limited to 'arch/arm/mach-cns3xxx/include') diff --git a/arch/arm/mach-cns3xxx/include/mach/pm.h b/arch/arm/mach-cns3xxx/include/mach/pm.h new file mode 100644 index 000000000000..102617bdb45b --- /dev/null +++ b/arch/arm/mach-cns3xxx/include/mach/pm.h @@ -0,0 +1,19 @@ +/* + * Copyright 2000 Deep Blue Solutions Ltd + * Copyright 2004 ARM Limited + * Copyright 2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#ifndef __CNS3XXX_PM_H +#define __CNS3XXX_PM_H + +void cns3xxx_pwr_clk_en(unsigned int block); +void cns3xxx_pwr_clk_dis(unsigned int block); +void cns3xxx_pwr_power_up(unsigned int block); +void cns3xxx_pwr_power_down(unsigned int block); + +#endif /* __CNS3XXX_PM_H */ -- cgit v1.2.2 From cf36797f35676dafae9d44484391ac7f56b2485a Mon Sep 17 00:00:00 2001 From: Mac Lin Date: Tue, 23 Nov 2010 00:32:44 +0800 Subject: ARM: cns3xxx: Add architecture definition for EHCI/OHCI controller This patch add plateform_device for EHCI and OHCI controller on CNS3XXX. Power reference count (usb_pwr_ref) is used to control enabling and disabling the single clock control for both EHCI and OHCI controller. It also removes EHCI/OHCI unused virtual address definitions. Signed-off-by: Mac Lin Signed-off-by: Anton Vorontsov --- arch/arm/mach-cns3xxx/include/mach/cns3xxx.h | 2 -- arch/arm/mach-cns3xxx/include/mach/pm.h | 4 ++++ 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-cns3xxx/include') diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h index 6dbce13771ca..191c8e57f289 100644 --- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h +++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h @@ -165,7 +165,6 @@ #define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000 #define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */ -#define CNS3XXX_USB_BASE_VIRT 0xFFF16000 #define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */ #define CNS3XXX_SATA2_SIZE SZ_16M @@ -184,7 +183,6 @@ #define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000 #define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */ -#define CNS3XXX_USB_OHCI_BASE_VIRT 0xFFF1C000 #define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */ #define CNS3XXX_L2C_BASE_VIRT 0xFFF27000 diff --git a/arch/arm/mach-cns3xxx/include/mach/pm.h b/arch/arm/mach-cns3xxx/include/mach/pm.h index 102617bdb45b..6eae7f764d1d 100644 --- a/arch/arm/mach-cns3xxx/include/mach/pm.h +++ b/arch/arm/mach-cns3xxx/include/mach/pm.h @@ -11,9 +11,13 @@ #ifndef __CNS3XXX_PM_H #define __CNS3XXX_PM_H +#include + void cns3xxx_pwr_clk_en(unsigned int block); void cns3xxx_pwr_clk_dis(unsigned int block); void cns3xxx_pwr_power_up(unsigned int block); void cns3xxx_pwr_power_down(unsigned int block); +extern atomic_t usb_pwr_ref; + #endif /* __CNS3XXX_PM_H */ -- cgit v1.2.2 From 960351fb8e980f0aa6682f11630ff98d3a18e2c0 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 16 Nov 2010 00:54:55 +0100 Subject: ARM: 6476/1: Use shared GIC entry macros on CNS3XXX Use the GIC demux code in asm/hardware/entry-macro-gic.S on the CNS3XXX subarchitecture. Signed-off-by: Magnus Damm Signed-off-by: Russell King --- arch/arm/mach-cns3xxx/include/mach/entry-macro.S | 61 +----------------------- 1 file changed, 1 insertion(+), 60 deletions(-) (limited to 'arch/arm/mach-cns3xxx/include') diff --git a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S index 5e1c5545680f..e793c3376728 100644 --- a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S +++ b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S @@ -9,7 +9,7 @@ */ #include -#include +#include .macro disable_fiq .endm @@ -21,62 +21,3 @@ .macro arch_ret_to_user, tmp1, tmp2 .endm - - /* - * The interrupt numbering scheme is defined in the - * interrupt controller spec. To wit: - * - * Interrupts 0-15 are IPI - * 16-28 are reserved - * 29-31 are local. We allow 30 to be used for the watchdog. - * 32-1020 are global - * 1021-1022 are reserved - * 1023 is "spurious" (no interrupt) - * - * For now, we ignore all local interrupts so only return an interrupt if it's - * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs. - * - * A simple read from the controller will tell us the number of the highest - * priority enabled interrupt. We then just need to check whether it is in the - * valid range for an IRQ (30-1020 inclusive). - */ - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - - ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */ - - ldr \tmp, =1021 - - bic \irqnr, \irqstat, #0x1c00 - - cmp \irqnr, #29 - cmpcc \irqnr, \irqnr - cmpne \irqnr, \tmp - cmpcs \irqnr, \irqnr - - .endm - - /* We assume that irqstat (the raw value of the IRQ acknowledge - * register) is preserved from the macro above. - * If there is an IPI, we immediately signal end of interrupt on the - * controller, since this requires the original irqstat value which - * we won't easily be able to recreate later. - */ - - .macro test_for_ipi, irqnr, irqstat, base, tmp - bic \irqnr, \irqstat, #0x1c00 - cmp \irqnr, #16 - strcc \irqstat, [\base, #GIC_CPU_EOI] - cmpcs \irqnr, \irqnr - .endm - - /* As above, this assumes that irqstat and base are preserved.. */ - - .macro test_for_ltirq, irqnr, irqstat, base, tmp - bic \irqnr, \irqstat, #0x1c00 - mov \tmp, #0 - cmp \irqnr, #29 - moveq \tmp, #1 - streq \irqstat, [\base, #GIC_CPU_EOI] - cmp \tmp, #0 - .endm -- cgit v1.2.2 From 7627dc802a98aebebc6a34e5b6558ea4717c968c Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 5 Dec 2010 08:51:38 +0000 Subject: ARM: GIC: private a standard get_irqnr_preamble assembler macro Provide a standard get_irqnr_preamble assembler macro for platforms to use, which retrieves the base address of the GIC CPU interface from gic_cpu_base_addr. Allow platforms to override this by defining HAVE_GET_IRQNR_PREAMBLE. Reviewed-by: Catalin Marinas Tested-by: Abhijeet Dharmapurikar Signed-off-by: Russell King --- arch/arm/mach-cns3xxx/include/mach/entry-macro.S | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch/arm/mach-cns3xxx/include') diff --git a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S index e793c3376728..6bd83ed90afe 100644 --- a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S +++ b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S @@ -14,10 +14,5 @@ .macro disable_fiq .endm - .macro get_irqnr_preamble, base, tmp - ldr \base, =gic_cpu_base_addr - ldr \base, [\base] - .endm - .macro arch_ret_to_user, tmp1, tmp2 .endm -- cgit v1.2.2