From 90303b102353302e84758f245906368907e6a23b Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Thu, 12 Jan 2006 16:53:51 +0000 Subject: [ARM] 3256/1: Make the function-returning ldm's use sp as the base register Patch from Catalin Marinas If the low interrupt latency mode is enabled for the CPU (from ARMv6 onwards), the ldm/stm instructions are no longer atomic. An ldm instruction restoring the sp and pc registers can be interrupted immediately after sp was updated but before the pc. If this happens, the CPU restores the base register to the value before the ldm instruction but if the base register is not sp, the interrupt routine will corrupt the stack and the restarted ldm instruction will load garbage. Note that future ARM cores might always run in the low interrupt latency mode. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/lib/csumpartialcopygeneric.S | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch/arm/lib/csumpartialcopygeneric.S') diff --git a/arch/arm/lib/csumpartialcopygeneric.S b/arch/arm/lib/csumpartialcopygeneric.S index 4a4609c19095..c50e8f5285d1 100644 --- a/arch/arm/lib/csumpartialcopygeneric.S +++ b/arch/arm/lib/csumpartialcopygeneric.S @@ -23,7 +23,7 @@ len .req r2 sum .req r3 .Lzero: mov r0, sum - load_regs ea + load_regs /* * Align an unaligned destination pointer. We know that @@ -87,9 +87,7 @@ sum .req r3 b .Ldone FN_ENTRY - mov ip, sp save_regs - sub fp, ip, #4 cmp len, #8 @ Ensure that we have at least blo .Lless8 @ 8 bytes to copy. @@ -163,7 +161,7 @@ FN_ENTRY ldr sum, [sp, #0] @ dst tst sum, #1 movne r0, r0, ror #8 - load_regs ea + load_regs .Lsrc_not_aligned: adc sum, sum, #0 @ include C from dst alignment -- cgit v1.2.2