From c56009b2f6134e5943a03cf26e4d7fce9745d56b Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 11 Jul 2013 13:58:36 +0800 Subject: ARM: dts: imx: share pad macro names between imx6q and imx6dl The imx6q and imx6dl are two pin-to-pin compatible SoCs. The same board design can work with either chip plugged into the socket, e.g. sabresd and sabreauto boards. We currently define pin groups in imx6q.dtsi and imx6dl.dtsi respectively because the pad macro names are different between two chips. This brings a maintenance burden on having the same label point to the same pin group defined in two places. The patch replaces prefix MX6Q_ and MX6DL_ with MX6QDL_ for both SoCs pad macro names. Then the pin groups becomes completely common between imx6q and imx6dl and can just be moved into imx6qdl.dtsi, so that the long term maintenance of imx6q/dt pin settings becomes easier. Unfortunately, the change brings some dramatic diff stat, but it's all about DTS file, and the ultimate net diff stat is good. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-sabresd.dts | 19 ------------------- 1 file changed, 19 deletions(-) (limited to 'arch/arm/boot/dts/imx6q-sabresd.dts') diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts index 0038228c508c..5e62c2427b07 100644 --- a/arch/arm/boot/dts/imx6q-sabresd.dts +++ b/arch/arm/boot/dts/imx6q-sabresd.dts @@ -19,22 +19,3 @@ model = "Freescale i.MX6 Quad SABRE Smart Device Board"; compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; }; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - hog { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6Q_PAD_GPIO_4__GPIO1_IO04 0x80000000 - MX6Q_PAD_GPIO_5__GPIO1_IO05 0x80000000 - MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x80000000 - MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x80000000 - MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x80000000 - MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x80000000 - MX6Q_PAD_GPIO_0__CCM_CLKO1 0x130b0 - >; - }; - }; -}; -- cgit v1.2.2