From 23bdf86aa06ebe71bcbf6b7d25de9958c6ab33fa Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Tue, 28 Mar 2006 21:00:40 +0100 Subject: [ARM] 3377/2: add support for intel xsc3 core Patch from Lennert Buytenhek This patch adds support for the new XScale v3 core. This is an ARMv5 ISA core with the following additions: - L2 cache - I/O coherency support (on select chipsets) - Low-Locality Reference cache attributes (replaces mini-cache) - Supersections (v6 compatible) - 36-bit addressing (v6 compatible) - Single instruction cache line clean/invalidate - LRU cache replacement (vs round-robin) I attempted to merge the XSC3 support into proc-xscale.S, but XSC3 cores have separate errata and have to handle things like L2, so it is simpler to keep it separate. L2 cache support is currently a build option because the L2 enable bit must be set before we enable the MMU and there is no easy way to capture command line parameters at this point. There are still optimizations that can be done such as using LLR for copypage (in theory using the exisiting mini-cache code) but those can be addressed down the road. Signed-off-by: Deepak Saxena Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/Makefile') diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 99c0d323719a..0f571d3d2fa4 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -57,6 +57,7 @@ tune-$(CONFIG_CPU_ARM926T) :=-mtune=arm9tdmi tune-$(CONFIG_CPU_SA110) :=-mtune=strongarm110 tune-$(CONFIG_CPU_SA1100) :=-mtune=strongarm1100 tune-$(CONFIG_CPU_XSCALE) :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale +tune-$(CONFIG_CPU_XSC3) :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale tune-$(CONFIG_CPU_V6) :=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm) ifeq ($(CONFIG_AEABI),y) -- cgit v1.2.2 From c4713074375c61f939310b04e92090afe29810dc Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Tue, 28 Mar 2006 21:18:54 +0100 Subject: [ARM] 3388/1: ixp23xx: add core ixp23xx support Patch from Lennert Buytenhek This patch adds support for the Intel ixp23xx series of CPUs. The ixp23xx is an XSC3 based CPU with 512K of L2 cache, a 64bit 66MHz PCI interface, two DDR RAM interfaces, QDR RAM interfaces, two gigabit MACs, two 10/100 MACs, expansion bus, four microengines, a Media and Switch Fabric unit almost identical to the one on the ixp2400, two xscale (8250ish) UARTs and a bunch of other stuff. This patch adds the core ixp23xx support code, and support for the ADI Engineering Roadrunner, Intel IXDP2351, and IP Fabrics Double Espresso platforms. Signed-off-by: Deepak Saxena Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/Makefile') diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 0f571d3d2fa4..ce3e804ea0f3 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -98,6 +98,7 @@ endif machine-$(CONFIG_ARCH_IOP3XX) := iop3xx machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx machine-$(CONFIG_ARCH_IXP2000) := ixp2000 + machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx machine-$(CONFIG_ARCH_OMAP1) := omap1 machine-$(CONFIG_ARCH_OMAP2) := omap2 incdir-$(CONFIG_ARCH_OMAP) := omap -- cgit v1.2.2