From 9025d563cd9bd141a7b7f2095b6a760cd9d83a4e Mon Sep 17 00:00:00 2001 From: Naveen Krishna Chatradhi Date: Thu, 19 Dec 2013 11:36:08 +0530 Subject: thermal: samsung: change base_common to more meaningful base_second On Exynos5440 and Exynos5420 there are registers common across the TMU channels. To support that, we introduced a ADDRESS_MULTIPLE flag in the driver and the 2nd set of register base and size are provided in the "reg" property of the node. As per Amit's suggestion, this patch changes the base_common to base_second and SHARED_MEMORY to ADDRESS_MULTIPLE. Signed-off-by: Naveen Krishna Chatradhi Acked-by: Amit Daniel Kachhap Reviewed-by: Bartlomiej Zolnierkiewicz Reviewed-by: Tomasz Figa Signed-off-by: Eduardo Valentin --- Documentation/devicetree/bindings/thermal/exynos-thermal.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt index 284f5300fd8b..a1aa6023d248 100644 --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt @@ -11,8 +11,8 @@ - reg : Address range of the thermal registers. For soc's which has multiple instances of TMU and some registers are shared across all TMU's like interrupt related then 2 set of register has to supplied. First set - belongs to each instance of TMU and second set belongs to common TMU - registers. + belongs to register set of TMU instance and second set belongs to + registers shared with the TMU instance. - interrupts : Should contain interrupt for thermal system - clocks : The main clock for TMU device - clock-names : Thermal system clock name -- cgit v1.2.2 From 14a11dc7e0dbf4acdd9c7b703ebd088f14def739 Mon Sep 17 00:00:00 2001 From: Naveen Krishna Chatradhi Date: Thu, 19 Dec 2013 11:36:31 +0530 Subject: thermal: samsung: Add TMU support for Exynos5420 SoCs Exynos5420 has 5 TMU channels, the TRIMINFO register is misplaced for TMU channels 2, 3 and 4 TRIMINFO at 0x1006c000 contains data for TMU channel 3 TRIMINFO at 0x100a0000 contains data for TMU channel 4 TRIMINFO at 0x10068000 contains data for TMU channel 2 This patch 1 Adds the neccessary register changes and arch information to support Exynos5420 SoCs. 2. Handles the gate clock for misplaced TRIMINFO register 3. Updates the Documentation at Documentation/devicetree/bindings/thermal/exynos-thermal.txt Signed-off-by: Naveen Krishna Chatradhi Signed-off-by: Andrew Bresticker Acked-by: Amit Daniel Kachhap Reviewed-by: Bartlomiej Zolnierkiewicz Reviewed-by: Tomasz Figa Signed-off-by: Eduardo Valentin --- .../devicetree/bindings/thermal/exynos-thermal.txt | 45 +++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt index a1aa6023d248..79c4055a190d 100644 --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt @@ -6,6 +6,9 @@ "samsung,exynos4412-tmu" "samsung,exynos4210-tmu" "samsung,exynos5250-tmu" + "samsung,exynos5420-tmu" for TMU channel 0, 1 on Exynos5420 + "samsung,exynos5420-tmu-ext-triminfo" for TMU channels 2, 3 and 4 + Exynos5420 (Must pass triminfo base and triminfo clock) "samsung,exynos5440-tmu" - interrupt-parent : The phandle for the interrupt controller - reg : Address range of the thermal registers. For soc's which has multiple @@ -13,9 +16,24 @@ interrupt related then 2 set of register has to supplied. First set belongs to register set of TMU instance and second set belongs to registers shared with the TMU instance. + + NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU + channels 2, 3 and 4 + Use "samsung,exynos5420-tmu-ext-triminfo" in cases, there is a misplaced + register, also provide clock to access that base. + + TRIMINFO at 0x1006c000 contains data for TMU channel 3 + TRIMINFO at 0x100a0000 contains data for TMU channel 4 + TRIMINFO at 0x10068000 contains data for TMU channel 2 + - interrupts : Should contain interrupt for thermal system -- clocks : The main clock for TMU device +- clocks : The main clocks for TMU device + -- 1. operational clock for TMU channel + -- 2. optional clock to access the shared registers of TMU channel - clock-names : Thermal system clock name + -- "tmu_apbif" operational clock for current TMU channel + -- "tmu_triminfo_apbif" clock to access the shared triminfo register + for current TMU channel - vtmu-supply: This entry is optional and provides the regulator node supplying voltage to TMU. If needed this entry can be placed inside board/platform specific dts file. @@ -43,6 +61,31 @@ Example 2): clock-names = "tmu_apbif"; }; +Example 3): (In case of Exynos5420 "with misplaced TRIMINFO register") + tmu_cpu2: tmu@10068000 { + compatible = "samsung,exynos5420-tmu-ext-triminfo"; + reg = <0x10068000 0x100>, <0x1006c000 0x4>; + interrupts = <0 184 0>; + clocks = <&clock 318>, <&clock 318>; + clock-names = "tmu_apbif", "tmu_triminfo_apbif"; + }; + + tmu_cpu3: tmu@1006c000 { + compatible = "samsung,exynos5420-tmu-ext-triminfo"; + reg = <0x1006c000 0x100>, <0x100a0000 0x4>; + interrupts = <0 185 0>; + clocks = <&clock 318>, <&clock 319>; + clock-names = "tmu_apbif", "tmu_triminfo_apbif"; + }; + + tmu_gpu: tmu@100a0000 { + compatible = "samsung,exynos5420-tmu-ext-triminfo"; + reg = <0x100a0000 0x100>, <0x10068000 0x4>; + interrupts = <0 215 0>; + clocks = <&clock 319>, <&clock 318>; + clock-names = "tmu_apbif", "tmu_triminfo_apbif"; + }; + Note: For multi-instance tmu each instance should have an alias correctly numbered in "aliases" node. -- cgit v1.2.2 From 923488a53e7890566f298c2f67416af84ba2a21c Mon Sep 17 00:00:00 2001 From: Naveen Krishna Chatradhi Date: Fri, 20 Dec 2013 17:49:10 +0530 Subject: thermal: samsung: Add TMU support for Exynos5260 SoCs This patch adds the registers, bit fields and compatible strings required to support for the 5 TMU channels on Exynos5260. Signed-off-by: Naveen Krishna Chatradhi Signed-off-by: Eduardo Valentin --- Documentation/devicetree/bindings/thermal/exynos-thermal.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt index 79c4055a190d..c94909215c07 100644 --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt @@ -6,6 +6,7 @@ "samsung,exynos4412-tmu" "samsung,exynos4210-tmu" "samsung,exynos5250-tmu" + "samsung,exynos5260-tmu" "samsung,exynos5420-tmu" for TMU channel 0, 1 on Exynos5420 "samsung,exynos5420-tmu-ext-triminfo" for TMU channels 2, 3 and 4 Exynos5420 (Must pass triminfo base and triminfo clock) -- cgit v1.2.2 From e2d5f05b745d19bc889c79977325b14853f3fc38 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Tue, 6 May 2014 13:59:50 -0300 Subject: thermal: armada: Support Armada 375 SoC Now that a generic infrastructure is in place, it's possible to support the new Armada 375 SoC thermal sensor. This sensor is similar to the one available in the already supported SoCs, with its specific temperature formula and specific sensor initialization. In addition, we also add support for the Z1 SoC stepping, which needs an initialization-quirk to work properly. Acked-by: Jason Cooper Signed-off-by: Ezequiel Garcia Signed-off-by: Zhang Rui --- Documentation/devicetree/bindings/thermal/armada-thermal.txt | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/thermal/armada-thermal.txt b/Documentation/devicetree/bindings/thermal/armada-thermal.txt index fff93d5f92de..2a67e5135835 100644 --- a/Documentation/devicetree/bindings/thermal/armada-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/armada-thermal.txt @@ -1,11 +1,20 @@ -* Marvell Armada 370/XP thermal management +* Marvell Armada 370/375/XP thermal management Required properties: - compatible: Should be set to one of the following: marvell,armada370-thermal + marvell,armada375-thermal + marvell,armada375-z1-thermal marvell,armadaxp-thermal + Note: As the name suggests, "marvell,armada375-z1-thermal" + applies for the SoC Z1 stepping only. On such stepping + some quirks need to be done and the register offset differs + from the one in the A0 stepping. + The operating system may auto-detect the SoC stepping and + update the compatible and register offsets at runtime. + - reg: Device's register space. Two entries are expected, see the examples below. The first one is required for the sensor register; -- cgit v1.2.2 From e6e0a68c6cd585773fa1fbbd1ca71272afe15203 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Tue, 6 May 2014 13:59:51 -0300 Subject: thermal: armada: Support Armada 380 SoC Now that a generic infrastructure is in place, it's possible to support the Armada 380 SoC thermal sensor. This sensor is similar to the one available in the already supported SoCs, with its specific temperature formula and specific sensor initialization. Acked-by: Jason Cooper Signed-off-by: Ezequiel Garcia Signed-off-by: Zhang Rui --- Documentation/devicetree/bindings/thermal/armada-thermal.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/thermal/armada-thermal.txt b/Documentation/devicetree/bindings/thermal/armada-thermal.txt index 2a67e5135835..4cf024929a3f 100644 --- a/Documentation/devicetree/bindings/thermal/armada-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/armada-thermal.txt @@ -1,4 +1,4 @@ -* Marvell Armada 370/375/XP thermal management +* Marvell Armada 370/375/380/XP thermal management Required properties: @@ -6,6 +6,7 @@ Required properties: marvell,armada370-thermal marvell,armada375-thermal marvell,armada375-z1-thermal + marvell,armada380-thermal marvell,armadaxp-thermal Note: As the name suggests, "marvell,armada375-z1-thermal" -- cgit v1.2.2