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/*****************************************************************************
* *
* File: suni1x10gexp_regs.h *
* $Revision: 1.9 $ *
* $Date: 2005/06/22 00:17:04 $ *
* Description: *
* PMC/SIERRA (pm3393) MAC-PHY functionality. *
* part of the Chelsio 10Gb Ethernet Driver. *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License, version 2, as *
* published by the Free Software Foundation. *
* *
* You should have received a copy of the GNU General Public License along *
* with this program; if not, write to the Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
* *
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
* *
* http://www.chelsio.com *
* *
* Maintainers: maintainers@chelsio.com *
* *
* Authors: PMC/SIERRA *
* *
* History: *
* *
****************************************************************************/
#ifndef _CXGB_SUNI1x10GEXP_REGS_H_
#define _CXGB_SUNI1x10GEXP_REGS_H_
/*
** Space allocated for each Exact Match Filter
** There are 8 filter configurations
*/
#define SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER 0x0003
#define mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId) ( (filterId) * SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER )
/*
** Space allocated for VLAN-Id Filter
** There are 8 filter configurations
*/
#define SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER 0x0001
#define mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId) ( (filterId) * SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER )
/*
** Space allocated for each MSTAT Counter
*/
#define SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT 0x0004
#define mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId) ( (countId) * SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT )
/******************************************************************************/
/** S/UNI-1x10GE-XP REGISTER ADDRESS MAP **/
/******************************************************************************/
/* Refer to the Register Bit Masks bellow for the naming of each register and */
/* to the S/UNI-1x10GE-XP Data Sheet for the signification of each bit */
/******************************************************************************/
#define SUNI1x10GEXP_REG_IDENTIFICATION 0x0000
#define SUNI1x10GEXP_REG_PRODUCT_REVISION 0x0001
#define SUNI1x10GEXP_REG_CONFIG_AND_RESET_CONTROL 0x0002
#define SUNI1x10GEXP_REG_LOOPBACK_MISC_CTRL 0x0003
#define SUNI1x10GEXP_REG_DEVICE_STATUS 0x0004
#define SUNI1x10GEXP_REG_GLOBAL_PERFORMANCE_MONITOR_UPDATE 0x0005
#define SUNI1x10GEXP_REG_MDIO_COMMAND 0x0006
#define SUNI1x10GEXP_REG_MDIO_INTERRUPT_ENABLE 0x0007
#define SUNI1x10GEXP_REG_MDIO_INTERRUPT_STATUS 0x0008
#define SUNI1x10GEXP_REG_MMD_PHY_ADDRESS 0x0009
#define SUNI1x10GEXP_REG_MMD_CONTROL_ADDRESS_DATA 0x000A
#define SUNI1x10GEXP_REG_MDIO_READ_STATUS_DATA 0x000B
#define SUNI1x10GEXP_REG_OAM_INTF_CTRL 0x000C
#define SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS 0x000D
#define SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE 0x000E
#define SUNI1x10GEXP_REG_FREE 0x000F
#define SUNI1x10GEXP_REG_XTEF_MISC_CTRL 0x0010
#define SUNI1x10GEXP_REG_XRF_MISC_CTRL 0x0011
#define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_1 0x0100
#define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_2 0x0101
#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE 0x0102
#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_VISIBLE 0x0103
#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS 0x0104
#define SUNI1x10GEXP_REG_SERDES_3125_TEST_CONFIG 0x0107
#define SUNI1x10GEXP_REG_RXXG_CONFIG_1 0x2040
#define SUNI1x10GEXP_REG_RXXG_CONFIG_2 0x2041
#define SUNI1x10GEXP_REG_RXXG_CONFIG_3 0x2042
#define SUNI1x10GEXP_REG_RXXG_INTERRUPT 0x2043
#define SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH 0x2045
#define SUNI1x10GEXP_REG_RXXG_SA_15_0 0x2046
#define SUNI1x10GEXP_REG_RXXG_SA_31_16 0x2047
#define SUNI1x10GEXP_REG_RXXG_SA_47_32 0x2048
#define SUNI1x10GEXP_REG_RXXG_RECEIVE_FIFO_THRESHOLD 0x2049
#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_LOW(filterId) (0x204A + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))
#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_MID(filterId) (0x204B + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))
#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_HIGH(filterId)(0x204C + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))
#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID(filterId) (0x2062 + mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId))
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_LOW 0x204A
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_MID 0x204B
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_HIGH 0x204C
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW 0x204D
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID 0x204E
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH 0x204F
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_LOW 0x2050
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_MID 0x2051
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_HIGH 0x2052
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_LOW 0x2053
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_MID 0x2054
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_HIGH 0x2055
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_LOW 0x2056
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_MID 0x2057
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_HIGH 0x2058
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_LOW 0x2059
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_MID 0x205A
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_HIGH 0x205B
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_LOW 0x205C
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_MID 0x205D
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_HIGH 0x205E
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_LOW 0x205F
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_MID 0x2060
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_HIGH 0x2061
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_0 0x2062
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_1 0x2063
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_2 0x2064
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_3 0x2065
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_4 0x2066
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_5 0x2067
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_6 0x2068
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_7 0x2069
#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW 0x206A
#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW 0x206B
#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH 0x206C
#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH 0x206D
#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0 0x206E
#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_1 0x206F
#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2 0x2070
#define SUNI1x10GEXP_REG_XRF_PATTERN_GEN_CTRL 0x2081
#define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_0 0x2084
#define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_1 0x2085
#define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_2 0x2086
#define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_3 0x2087
#define SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE 0x2088
#define SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS 0x2089
#define SUNI1x10GEXP_REG_XRF_ERR_STATUS 0x208A
#define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE 0x208B
#define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS 0x208C
#define SUNI1x10GEXP_REG_XRF_CODE_ERR_THRES 0x2092
#define SUNI1x10GEXP_REG_RXOAM_CONFIG 0x20C0
#define SUNI1x10GEXP_REG_RXOAM_FILTER_1_CONFIG 0x20C1
#define SUNI1x10GEXP_REG_RXOAM_FILTER_2_CONFIG 0x20C2
#define SUNI1x10GEXP_REG_RXOAM_CONFIG_2 0x20C3
#define SUNI1x10GEXP_REG_RXOAM_HEC_CONFIG 0x20C4
#define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_THRES 0x20C5
#define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE 0x20C7
#define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS 0x20C8
#define SUNI1x10GEXP_REG_RXOAM_STATUS 0x20C9
#define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_COUNT 0x20CA
#define SUNI1x10GEXP_REG_RXOAM_FIFO_OVERFLOW_COUNT 0x20CB
#define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_LSB 0x20CC
#define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_MSB 0x20CD
#define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_LSB 0x20CE
#define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_MSB 0x20CF
#define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_LSB 0x20D0
#define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_MSB 0x20D1
#define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_LSB 0x20D2
#define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_MSB 0x20D3
#define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_LSB 0x20D4
#define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_MSB 0x20D5
#define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_LSB 0x20D6
#define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_MSB 0x20D7
#define SUNI1x10GEXP_REG_MSTAT_CONTROL 0x2100
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0 0x2101
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1 0x2102
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_2 0x2103
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_3 0x2104
#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0 0x2105
#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1 0x2106
#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2 0x2107
#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3 0x2108
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_ADDRESS 0x2109
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_LOW 0x210A
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_MIDDLE 0x210B
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_HIGH 0x210C
#define mSUNI1x10GEXP_REG_MSTAT_COUNTER_LOW(countId) (0x2110 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))
#define mSUNI1x10GEXP_REG_MSTAT_COUNTER_MID(countId) (0x2111 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))
#define mSUNI1x10GEXP_REG_MSTAT_COUNTER_HIGH(countId) (0x2112 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW 0x2110
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_MID 0x2111
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_HIGH 0x2112
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_RESVD 0x2113
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW 0x2114
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_MID 0x2115
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_HIGH 0x2116
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_RESVD 0x2117
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_LOW 0x2118
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_MID 0x2119
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_HIGH 0x211A
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_RESVD 0x211B
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_LOW 0x211C
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_MID 0x211D
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_HIGH 0x211E
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_RESVD 0x211F
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW 0x2120
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_MID 0x2121
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_HIGH 0x2122
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_RESVD 0x2123
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW 0x2124
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_MID 0x2125
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_HIGH 0x2126
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_RESVD 0x2127
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW 0x2128
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_MID 0x2129
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_HIGH 0x212A
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_RESVD 0x212B
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_LOW 0x212C
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_MID 0x212D
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_HIGH 0x212E
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_RESVD 0x212F
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW 0x2130
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_MID 0x2131
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_HIGH 0x2132
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_RESVD 0x2133
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_LOW 0x2134
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_MID 0x2135
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_HIGH 0x2136
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_RESVD 0x2137
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW 0x2138
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_MID 0x2139
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_HIGH 0x213A
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_RESVD 0x213B
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW 0x213C
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_MID 0x213D
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_HIGH 0x213E
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_RESVD 0x213F
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW 0x2140
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_MID 0x2141
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_HIGH 0x2142
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_RESVD 0x2143
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW 0x2144
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_MID 0x2145
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_HIGH 0x2146
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_RESVD 0x2147
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_LOW 0x2148
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_MID 0x2149
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_HIGH 0x214A
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_RESVD 0x214B
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW 0x214C
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_MID 0x214D
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_HIGH 0x214E
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_RESVD 0x214F
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW 0x2150
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_MID 0x2151
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_HIGH 0x2152
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_RESVD 0x2153
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW 0x2154
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_MID 0x2155
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_HIGH 0x2156
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_RESVD 0x2157
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW 0x2158
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_MID 0x2159
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_HIGH 0x215A
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_RESVD 0x215B
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_LOW 0x215C
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_MID 0x215D
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_HIGH 0x215E
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_RESVD 0x215F
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_LOW 0x2160
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_MID 0x2161
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_HIGH 0x2162
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_RESVD 0x2163
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_LOW 0x2164
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_MID 0x2165
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_HIGH 0x2166
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_RESVD 0x2167
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_LOW 0x2168
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_MID 0x2169
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_HIGH 0x216A
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_RESVD 0x216B
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_LOW 0x216C
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_MID 0x216D
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_HIGH 0x216E
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_RESVD 0x216F
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_LOW 0x2170
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_MID 0x2171
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_HIGH 0x2172
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_RESVD 0x2173
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_LOW 0x2174
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_MID 0x2175
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_HIGH 0x2176
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_RESVD 0x2177
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_LOW 0x2178
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_MID 0x2179
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_HIGH 0x217a
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_RESVD 0x217b
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_LOW 0x217c
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_MID 0x217d
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_HIGH 0x217e
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_RESVD 0x217f
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_LOW 0x2180
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_MID 0x2181
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_HIGH 0x2182
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_RESVD 0x2183
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_LOW 0x2184
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_MID 0x2185
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_HIGH 0x2186
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_RESVD 0x2187
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_LOW 0x2188
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_MID 0x2189
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_HIGH 0x218A
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_RESVD 0x218B
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_LOW 0x218C
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_MID 0x218D
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_HIGH 0x218E
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_RESVD 0x218F
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_LOW 0x2190
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_MID 0x2191
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_HIGH 0x2192
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_RESVD 0x2193
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW 0x2194
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_MID 0x2195
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_HIGH 0x2196
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_RESVD 0x2197
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_LOW 0x2198
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_MID 0x2199
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_HIGH 0x219A
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_RESVD 0x219B
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW 0x219C
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_MID 0x219D
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_HIGH 0x219E
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_RESVD 0x219F
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW 0x21A0
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_MID 0x21A1
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_HIGH 0x21A2
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_RESVD 0x21A3
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_LOW 0x21A4
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_MID 0x21A5
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_HIGH 0x21A6
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_RESVD 0x21A7
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW 0x21A8
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_MID 0x21A9
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_HIGH 0x21AA
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_RESVD 0x21AB
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_LOW 0x21AC
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_MID 0x21AD
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_HIGH 0x21AE
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_RESVD 0x21AF
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW 0x21B0
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_MID 0x21B1
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_HIGH 0x21B2
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_RESVD 0x21B3
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_LOW 0x21B4
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_MID 0x21B5
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_HIGH 0x21B6
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_RESVD 0x21B7
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW 0x21B8
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_MID 0x21B9
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_HIGH 0x21BA
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_RESVD 0x21BB
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW 0x21BC
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_MID 0x21BD
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_HIGH 0x21BE
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_RESVD 0x21BF
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_LOW 0x21C0
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_MID 0x21C1
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_HIGH 0x21C2
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_RESVD 0x21C3
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_LOW 0x21C4
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_MID 0x21C5
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_HIGH 0x21C6
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_RESVD 0x21C7
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_LOW 0x21C8
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_MID 0x21C9
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_HIGH 0x21CA
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_RESVD 0x21CB
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_LOW 0x21CC
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_MID 0x21CD
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_HIGH 0x21CE
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_RESVD 0x21CF
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_LOW 0x21D0
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_MID 0x21D1
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_HIGH 0x21D2
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_RESVD 0x21D3
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_LOW 0x21D4
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_MID 0x21D5
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_HIGH 0x21D6
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_RESVD 0x21D7
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_LOW 0x21D8
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_MID 0x21D9
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_HIGH 0x21DA
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_RESVD 0x21DB
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_LOW 0x21DC
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_MID 0x21DD
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_HIGH 0x21DE
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_RESVD 0x21DF
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_LOW 0x21E0
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_MID 0x21E1
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_HIGH 0x21E2
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_RESVD 0x21E3
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_LOW 0x21E4
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_MID 0x21E5
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_HIGH 0x21E6
#define SUNI1x10GEXP_CNTR_MAC_ETHERNET_NUM 51
#define SUNI1x10GEXP_REG_IFLX_GLOBAL_CONFIG 0x2200
#define SUNI1x10GEXP_REG_IFLX_CHANNEL_PROVISION 0x2201
#define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE 0x2209
#define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT 0x220A
#define SUNI1x10GEXP_REG_IFLX_INDIR_CHANNEL_ADDRESS 0x220D
#define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_LOW_LIMIT_PROVISION 0x220E
#define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_HIGH_LIMIT 0x220F
#define SUNI1x10GEXP_REG_IFLX_INDIR_FULL_ALMOST_FULL_STATUS_LIMIT 0x2210
#define SUNI1x10GEXP_REG_IFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_LIMIT 0x2211
#define SUNI1x10GEXP_REG_PL4MOS_CONFIG 0x2240
#define SUNI1x10GEXP_REG_PL4MOS_MASK 0x2241
#define SUNI1x10GEXP_REG_PL4MOS_FAIRNESS_MASKING 0x2242
#define SUNI1x10GEXP_REG_PL4MOS_MAXBURST1 0x2243
#define SUNI1x10GEXP_REG_PL4MOS_MAXBURST2 0x2244
#define SUNI1x10GEXP_REG_PL4MOS_TRANSFER_SIZE 0x2245
#define SUNI1x10GEXP_REG_PL4ODP_CONFIG 0x2280
#define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK 0x2282
#define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT 0x2283
#define SUNI1x10GEXP_REG_PL4ODP_CONFIG_MAX_T 0x2284
#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS 0x2300
#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE 0x2301
#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK 0x2302
#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_LIMITS 0x2303
#define SUNI1x10GEXP_REG_PL4IO_CALENDAR_REPETITIONS 0x2304
#define SUNI1x10GEXP_REG_PL4IO_CONFIG 0x2305
#define SUNI1x10GEXP_REG_TXXG_CONFIG_1 0x3040
#define SUNI1x10GEXP_REG_TXXG_CONFIG_2 0x3041
#define SUNI1x10GEXP_REG_TXXG_CONFIG_3 0x3042
#define SUNI1x10GEXP_REG_TXXG_INTERRUPT 0x3043
#define SUNI1x10GEXP_REG_TXXG_STATUS 0x3044
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