From a81cbd2da48eacc860acf4f40ea05db790f4c7c3 Mon Sep 17 00:00:00 2001 From: Oskar Schirmer Date: Wed, 4 Mar 2009 16:21:30 +0100 Subject: xtensa: enforce slab alignment to maximum register width XCHAL_DATA_WIDTH is the maximum register width, slab caches should be aligned to this. Theoretical fix as all variants have had an XCHAL_DATA_WIDTH of 4 (wordsize) for now. But the S6000 variant will raise this to 16. Signed-off-by: Oskar Schirmer Signed-off-by: Johannes Weiner Signed-off-by: Chris Zankel --- arch/xtensa/include/asm/processor.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/xtensa/include/asm/processor.h b/arch/xtensa/include/asm/processor.h index 07387d3b99f4..fba8b7e44a22 100644 --- a/arch/xtensa/include/asm/processor.h +++ b/arch/xtensa/include/asm/processor.h @@ -25,6 +25,8 @@ # error Linux requires the Xtensa Windowed Registers Option. #endif +#define ARCH_SLAB_MINALIGN XCHAL_DATA_WIDTH + /* * User space process size: 1 GB. * Windowed call ABI requires caller and callee to be located within the same -- cgit v1.2.2