From 20e652761cbf6983fd067aef2f0242c262057737 Mon Sep 17 00:00:00 2001 From: Andrew Victor Date: Wed, 5 Jul 2006 14:31:13 +0100 Subject: [ARM] 3710/1: AT91 Serial: Use GPIO API Patch from Andrew Victor The AT91RM9200 errata work-around should be using the GPIO API and not accessing the PIO registers directly. Signed-off-by: Andrew Victor Signed-off-by: Russell King --- drivers/serial/at91_serial.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/serial/at91_serial.c b/drivers/serial/at91_serial.c index a7d664383dae..54c6b2adf7b7 100644 --- a/drivers/serial/at91_serial.c +++ b/drivers/serial/at91_serial.c @@ -41,6 +41,7 @@ #include #include #include +#include #if defined(CONFIG_SERIAL_AT91_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) #define SUPPORT_SYSRQ @@ -140,9 +141,9 @@ static void at91_set_mctrl(struct uart_port *port, u_int mctrl) */ if (port->mapbase == AT91_BASE_US0) { if (mctrl & TIOCM_RTS) - at91_sys_write(AT91_PIOA + PIO_CODR, AT91_PA21_RTS0); + at91_set_gpio_value(AT91_PIN_PA21, 0); else - at91_sys_write(AT91_PIOA + PIO_SODR, AT91_PA21_RTS0); + at91_set_gpio_value(AT91_PIN_PA21, 1); } } -- cgit v1.2.2 From 5904a7f9167cdeb95569799e0be652c2ce6d3298 Mon Sep 17 00:00:00 2001 From: Vitaly Wool Date: Wed, 5 Jul 2006 14:47:20 +0100 Subject: [ARM] 3709/1: pnx4008: convert to generic irq subsystem Patch from Vitaly Wool Convert pnx4008 chip support to use generic irq subsystem Signed-off-by: Vitaly Wool Signed-off-by: Russell King --- arch/arm/mach-pnx4008/core.c | 2 -- arch/arm/mach-pnx4008/dma.c | 1 - arch/arm/mach-pnx4008/irq.c | 22 ++++++++++------------ arch/arm/mach-pnx4008/time.c | 8 +++----- 4 files changed, 13 insertions(+), 20 deletions(-) diff --git a/arch/arm/mach-pnx4008/core.c b/arch/arm/mach-pnx4008/core.c index ba91daad64fb..3d73c1e93752 100644 --- a/arch/arm/mach-pnx4008/core.c +++ b/arch/arm/mach-pnx4008/core.c @@ -27,7 +27,6 @@ #include #include -#include #include #include #include @@ -36,7 +35,6 @@ #include #include -#include #include #include diff --git a/arch/arm/mach-pnx4008/dma.c b/arch/arm/mach-pnx4008/dma.c index 981aa9dcdede..ec01574f88ac 100644 --- a/arch/arm/mach-pnx4008/dma.c +++ b/arch/arm/mach-pnx4008/dma.c @@ -23,7 +23,6 @@ #include #include -#include #include #include #include diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c index 9b0a8e084e99..3a4bcf3d91fa 100644 --- a/arch/arm/mach-pnx4008/irq.c +++ b/arch/arm/mach-pnx4008/irq.c @@ -22,8 +22,8 @@ #include #include #include +#include #include -#include #include #include #include @@ -96,26 +96,24 @@ void __init pnx4008_init_irq(void) { unsigned int i; - /* configure and enable IRQ 0,1,30,31 (cascade interrupts) mask all others */ + /* configure IRQ's */ + for (i = 0; i < NR_IRQS; i++) { + set_irq_flags(i, IRQF_VALID); + set_irq_chip(i, &pnx4008_irq_chip); + pnx4008_set_irq_type(i, pnx4008_irq_type[i]); + } + + /* configure and enable IRQ 0,1,30,31 (cascade interrupts) */ pnx4008_set_irq_type(SUB1_IRQ_N, pnx4008_irq_type[SUB1_IRQ_N]); pnx4008_set_irq_type(SUB2_IRQ_N, pnx4008_irq_type[SUB2_IRQ_N]); pnx4008_set_irq_type(SUB1_FIQ_N, pnx4008_irq_type[SUB1_FIQ_N]); pnx4008_set_irq_type(SUB2_FIQ_N, pnx4008_irq_type[SUB2_FIQ_N]); + /* mask all others */ __raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) | (1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N), INTC_ER(MAIN_BASE_INT)); __raw_writel(0, INTC_ER(SIC1_BASE_INT)); __raw_writel(0, INTC_ER(SIC2_BASE_INT)); - - /* configure all other IRQ's */ - for (i = 0; i < NR_IRQS; i++) { - if (i == SUB2_FIQ_N || i == SUB1_FIQ_N || - i == SUB2_IRQ_N || i == SUB1_IRQ_N) - continue; - set_irq_flags(i, IRQF_VALID); - set_irq_chip(i, &pnx4008_irq_chip); - pnx4008_set_irq_type(i, pnx4008_irq_type[i]); - } } diff --git a/arch/arm/mach-pnx4008/time.c b/arch/arm/mach-pnx4008/time.c index 888bf6cfba8a..756228ddd035 100644 --- a/arch/arm/mach-pnx4008/time.c +++ b/arch/arm/mach-pnx4008/time.c @@ -20,17 +20,15 @@ #include #include #include +#include +#include +#include #include #include #include #include -#include -#include #include - -#include -#include #include /*! Note: all timers are UPCOUNTING */ -- cgit v1.2.2 From ba854e18413d2d827f050984edeb8286c3335895 Mon Sep 17 00:00:00 2001 From: Andrew Victor Date: Wed, 5 Jul 2006 17:22:52 +0100 Subject: [ARM] 3711/1: AT91 timer update Patch from Andrew Victor The AIC interrupt controller is the same on the Atmel AT91RM9200, AT91SAM9261 and AT91SAM9260 processors. This patch removes any RM9200-specific naming from the IRQ driver, and moves the AT91RM9200's default IRQ priority table into at91rm9200.c. Signed-off-by: Andrew Victor Signed-off-by: Russell King --- arch/arm/mach-at91rm9200/at91rm9200.c | 45 ++++++++++++++++++++++ arch/arm/mach-at91rm9200/generic.h | 8 +++- arch/arm/mach-at91rm9200/irq.c | 70 +++++++--------------------------- include/asm-arm/arch-at91rm9200/irqs.h | 8 ---- 4 files changed, 66 insertions(+), 65 deletions(-) diff --git a/arch/arm/mach-at91rm9200/at91rm9200.c b/arch/arm/mach-at91rm9200/at91rm9200.c index 7e1d072bdd80..0985b1c42c7c 100644 --- a/arch/arm/mach-at91rm9200/at91rm9200.c +++ b/arch/arm/mach-at91rm9200/at91rm9200.c @@ -107,3 +107,48 @@ void __init at91rm9200_map_io(void) iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc)); } +/* + * The default interrupt priority levels (0 = lowest, 7 = highest). + */ +static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = { + 7, /* Advanced Interrupt Controller (FIQ) */ + 7, /* System Peripherals */ + 0, /* Parallel IO Controller A */ + 0, /* Parallel IO Controller B */ + 0, /* Parallel IO Controller C */ + 0, /* Parallel IO Controller D */ + 6, /* USART 0 */ + 6, /* USART 1 */ + 6, /* USART 2 */ + 6, /* USART 3 */ + 0, /* Multimedia Card Interface */ + 4, /* USB Device Port */ + 0, /* Two-Wire Interface */ + 6, /* Serial Peripheral Interface */ + 5, /* Serial Synchronous Controller 0 */ + 5, /* Serial Synchronous Controller 1 */ + 5, /* Serial Synchronous Controller 2 */ + 0, /* Timer Counter 0 */ + 0, /* Timer Counter 1 */ + 0, /* Timer Counter 2 */ + 0, /* Timer Counter 3 */ + 0, /* Timer Counter 4 */ + 0, /* Timer Counter 5 */ + 3, /* USB Host port */ + 3, /* Ethernet MAC */ + 0, /* Advanced Interrupt Controller (IRQ0) */ + 0, /* Advanced Interrupt Controller (IRQ1) */ + 0, /* Advanced Interrupt Controller (IRQ2) */ + 0, /* Advanced Interrupt Controller (IRQ3) */ + 0, /* Advanced Interrupt Controller (IRQ4) */ + 0, /* Advanced Interrupt Controller (IRQ5) */ + 0 /* Advanced Interrupt Controller (IRQ6) */ +}; + +void __init at91rm9200_init_irq(unsigned int priority[NR_AIC_IRQS]) +{ + if (!priority) + priority = at91rm9200_default_irq_priority; + + at91_aic_init(priority); +} diff --git a/arch/arm/mach-at91rm9200/generic.h b/arch/arm/mach-at91rm9200/generic.h index f0d969d7d874..7979d8ab7e07 100644 --- a/arch/arm/mach-at91rm9200/generic.h +++ b/arch/arm/mach-at91rm9200/generic.h @@ -8,13 +8,19 @@ * published by the Free Software Foundation. */ -void at91_gpio_irq_setup(unsigned banks); + /* Interrupts */ +extern void __init at91rm9200_init_irq(unsigned int priority[]); +extern void __init at91_aic_init(unsigned int priority[]); +extern void __init at91_gpio_irq_setup(unsigned banks); + /* Timer */ struct sys_timer; extern struct sys_timer at91rm9200_timer; + /* Memory Map */ extern void __init at91rm9200_map_io(void); + /* Clocks */ extern int __init at91_clock_init(unsigned long main_clock); struct device; extern void __init at91_clock_associate(const char *id, struct device *dev, const char *func); diff --git a/arch/arm/mach-at91rm9200/irq.c b/arch/arm/mach-at91rm9200/irq.c index dcd560dbcfb7..9b0911320417 100644 --- a/arch/arm/mach-at91rm9200/irq.c +++ b/arch/arm/mach-at91rm9200/irq.c @@ -36,58 +36,20 @@ #include "generic.h" -/* - * The default interrupt priority levels (0 = lowest, 7 = highest). - */ -static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = { - 7, /* Advanced Interrupt Controller */ - 7, /* System Peripheral */ - 0, /* Parallel IO Controller A */ - 0, /* Parallel IO Controller B */ - 0, /* Parallel IO Controller C */ - 0, /* Parallel IO Controller D */ - 6, /* USART 0 */ - 6, /* USART 1 */ - 6, /* USART 2 */ - 6, /* USART 3 */ - 0, /* Multimedia Card Interface */ - 4, /* USB Device Port */ - 0, /* Two-Wire Interface */ - 6, /* Serial Peripheral Interface */ - 5, /* Serial Synchronous Controller */ - 5, /* Serial Synchronous Controller */ - 5, /* Serial Synchronous Controller */ - 0, /* Timer Counter 0 */ - 0, /* Timer Counter 1 */ - 0, /* Timer Counter 2 */ - 0, /* Timer Counter 3 */ - 0, /* Timer Counter 4 */ - 0, /* Timer Counter 5 */ - 3, /* USB Host port */ - 3, /* Ethernet MAC */ - 0, /* Advanced Interrupt Controller */ - 0, /* Advanced Interrupt Controller */ - 0, /* Advanced Interrupt Controller */ - 0, /* Advanced Interrupt Controller */ - 0, /* Advanced Interrupt Controller */ - 0, /* Advanced Interrupt Controller */ - 0 /* Advanced Interrupt Controller */ -}; - -static void at91rm9200_mask_irq(unsigned int irq) +static void at91_aic_mask_irq(unsigned int irq) { /* Disable interrupt on AIC */ at91_sys_write(AT91_AIC_IDCR, 1 << irq); } -static void at91rm9200_unmask_irq(unsigned int irq) +static void at91_aic_unmask_irq(unsigned int irq) { /* Enable interrupt on AIC */ at91_sys_write(AT91_AIC_IECR, 1 << irq); } -static int at91rm9200_irq_type(unsigned irq, unsigned type) +static int at91_aic_set_type(unsigned irq, unsigned type) { unsigned int smr, srctype; @@ -122,7 +84,7 @@ static int at91rm9200_irq_type(unsigned irq, unsigned type) static u32 wakeups; static u32 backups; -static int at91rm9200_irq_set_wake(unsigned irq, unsigned value) +static int at91_aic_set_wake(unsigned irq, unsigned value) { if (unlikely(irq >= 32)) return -EINVAL; @@ -149,28 +111,24 @@ void at91_irq_resume(void) } #else -#define at91rm9200_irq_set_wake NULL +#define at91_aic_set_wake NULL #endif -static struct irqchip at91rm9200_irq_chip = { - .ack = at91rm9200_mask_irq, - .mask = at91rm9200_mask_irq, - .unmask = at91rm9200_unmask_irq, - .set_type = at91rm9200_irq_type, - .set_wake = at91rm9200_irq_set_wake, +static struct irqchip at91_aic_chip = { + .ack = at91_aic_mask_irq, + .mask = at91_aic_mask_irq, + .unmask = at91_aic_unmask_irq, + .set_type = at91_aic_set_type, + .set_wake = at91_aic_set_wake, }; /* * Initialize the AIC interrupt controller. */ -void __init at91rm9200_init_irq(unsigned int priority[NR_AIC_IRQS]) +void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS]) { unsigned int i; - /* No priority list specified for this board -> use defaults */ - if (priority == NULL) - priority = at91rm9200_default_irq_priority; - /* * The IVR is used by macro get_irqnr_and_base to read and verify. * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred. @@ -178,10 +136,10 @@ void __init at91rm9200_init_irq(unsigned int priority[NR_AIC_IRQS]) for (i = 0; i < NR_AIC_IRQS; i++) { /* Put irq number in Source Vector Register: */ at91_sys_write(AT91_AIC_SVR(i), i); - /* Store the Source Mode Register as defined in table above */ + /* Active Low interrupt, with the specified priority */ at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); - set_irq_chip(i, &at91rm9200_irq_chip); + set_irq_chip(i, &at91_aic_chip); set_irq_handler(i, do_level_IRQ); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); diff --git a/include/asm-arm/arch-at91rm9200/irqs.h b/include/asm-arm/arch-at91rm9200/irqs.h index 2dc93b174a8f..f63842c2c093 100644 --- a/include/asm-arm/arch-at91rm9200/irqs.h +++ b/include/asm-arm/arch-at91rm9200/irqs.h @@ -39,12 +39,4 @@ */ #define NR_IRQS (NR_AIC_IRQS + (4 * 32)) - -#ifndef __ASSEMBLY__ -/* - * Initialize the IRQ controller. - */ -extern void at91rm9200_init_irq(unsigned int priority[]); -#endif - #endif -- cgit v1.2.2