From 3c8fdae78cf5d73c6739912a1ff087c0f23b2a47 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 8 Mar 2006 17:25:33 +0000 Subject: [ARM] Fix muldi3.S When shifting the low-parts of signed numbers, a logical shift should be used to avoid sign-extending a bit which isn't a sign bit. Signed-off-by: Russell King --- arch/arm/lib/muldi3.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/lib/muldi3.S b/arch/arm/lib/muldi3.S index 72d594184b8a..d89c60615794 100644 --- a/arch/arm/lib/muldi3.S +++ b/arch/arm/lib/muldi3.S @@ -29,8 +29,8 @@ ENTRY(__aeabi_lmul) mul xh, yl, xh mla xh, xl, yh, xh - mov ip, xl, asr #16 - mov yh, yl, asr #16 + mov ip, xl, lsr #16 + mov yh, yl, lsr #16 bic xl, xl, ip, lsl #16 bic yl, yl, yh, lsl #16 mla xh, yh, ip, xh -- cgit v1.2.2 From dcc8fa50ebc251a1394a2c8561eee7d79cc5f437 Mon Sep 17 00:00:00 2001 From: Alessandro Zummo Date: Wed, 8 Mar 2006 23:45:10 +0000 Subject: [ARM] 3354/1: NAS100d: fix power led handling Patch from Alessandro Zummo Disable GPIO clocks to allow the power led to work properly. Signed-off-by: Alessandro Zummo Signed-off-by: Russell King --- arch/arm/mach-ixp4xx/nas100d-setup.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c index 856d56f3b2ae..a3b4c6ac5708 100644 --- a/arch/arm/mach-ixp4xx/nas100d-setup.c +++ b/arch/arm/mach-ixp4xx/nas100d-setup.c @@ -113,6 +113,9 @@ static void __init nas100d_init(void) { ixp4xx_sys_init(); + /* gpio 14 and 15 are _not_ clocks */ + *IXP4XX_GPIO_GPCLKR = 0; + nas100d_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); nas100d_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; -- cgit v1.2.2 From e7fcdb79ecaa01e2eba06e3fb64e10455bdb5aa7 Mon Sep 17 00:00:00 2001 From: Alessandro Zummo Date: Wed, 8 Mar 2006 23:45:12 +0000 Subject: [ARM] 3355/1: NSLU2: remove propmt depends Patch from Alessandro Zummo The patch that would have made the NSLU2 kernel non compatible with other ixp4xx machs never entered the kernel. So it is actually safe to remove the prompt dependencies. Signed-off-by: Alessandro Zummo Signed-off-by: Russell King --- arch/arm/mach-ixp4xx/Kconfig | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig index daadc78e271b..5bf50a2a737d 100644 --- a/arch/arm/mach-ixp4xx/Kconfig +++ b/arch/arm/mach-ixp4xx/Kconfig @@ -8,11 +8,9 @@ menu "Intel IXP4xx Implementation Options" comment "IXP4xx Platforms" -# This entry is placed on top because otherwise it would have -# been shown as a submenu. config MACH_NSLU2 bool - prompt "NSLU2" if !(MACH_IXDP465 || MACH_IXDPG425 || ARCH_IXDP425 || ARCH_ADI_COYOTE || ARCH_AVILA || ARCH_IXCDP1100 || ARCH_PRPMC1100 || MACH_GTWX5715) + prompt "Linksys NSLU2" help Say 'Y' here if you want your kernel to support Linksys's NSLU2 NAS device. For more information on this platform, -- cgit v1.2.2 From 141fa40cff90881ac4d81f6afa27bc283fe7acca Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Fri, 10 Mar 2006 22:26:47 +0000 Subject: [ARM] 3356/1: Workaround for the ARM1136 I-cache invalidation problem Patch from Catalin Marinas ARM1136 erratum 371025 (category 2) specifies that, under rare conditions, an invalidate I-cache by MVA (line or range) operation can fail to invalidate a cache line. The recommended workaround is to either invalidate the entire I-cache or invalidate the range by set/way rather than MVA. Note that for a 16K cache size, invalidating a 4K page by set/way is equivalent to invalidating the entire I-cache. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mm/cache-v6.S | 7 ++++--- arch/arm/mm/flush.c | 6 ++++-- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S index d921c1024ae0..2c6c2a7c05a0 100644 --- a/arch/arm/mm/cache-v6.S +++ b/arch/arm/mm/cache-v6.S @@ -96,15 +96,16 @@ ENTRY(v6_coherent_user_range) #ifdef HARVARD_CACHE bic r0, r0, #CACHE_LINE_SIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D line - mcr p15, 0, r0, c7, c5, 1 @ invalidate I line add r0, r0, #CACHE_LINE_SIZE cmp r0, r1 blo 1b #endif - mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB -#ifdef HARVARD_CACHE mov r0, #0 +#ifdef HARVARD_CACHE mcr p15, 0, r0, c7, c10, 4 @ drain write buffer + mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate +#else + mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB #endif mov pc, lr diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index 330695b6b19d..b103e56806bd 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -24,14 +24,16 @@ static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr) { unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT); + const int zero = 0; set_pte(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL)); flush_tlb_kernel_page(to); asm( "mcrr p15, 0, %1, %0, c14\n" - " mcrr p15, 0, %1, %0, c5\n" + " mcr p15, 0, %2, c7, c10, 4\n" + " mcr p15, 0, %2, c7, c5, 0\n" : - : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES) + : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero) : "cc"); } -- cgit v1.2.2 From 04916c0ef482335cb0ae575dbc5a1d97619840cd Mon Sep 17 00:00:00 2001 From: Alessandro Zummo Date: Fri, 10 Mar 2006 22:30:01 +0000 Subject: [ARM] 3350/1: Enable 1-wire on ARM Patch from Alessandro Zummo This patches add the 1-wire drivers to the ARM Kconfig. Signed-off-by: Alessandro Zummo Signed-off-by: Russell King --- arch/arm/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9f80fa502f8f..32ba00bd0a2f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -799,6 +799,8 @@ source "drivers/i2c/Kconfig" source "drivers/spi/Kconfig" +source "drivers/w1/Kconfig" + source "drivers/hwmon/Kconfig" #source "drivers/l3/Kconfig" -- cgit v1.2.2 From cdaabbd74b15296acf09215355a7f3b07b92b83e Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 12 Mar 2006 22:36:06 +0000 Subject: [ARM] iwmmxt thread state alignment This patch removes the reliance of iwmmxt on hand coded alignments. Since thread_info is always 8K aligned, specifying that fpstate is 8-byte aligned achieves the same effect without needing to resort to hand coded alignments. Signed-off-by: Russell King --- arch/arm/kernel/asm-offsets.c | 4 +++- arch/arm/kernel/ptrace.c | 14 ++++---------- include/asm-arm/fpstate.h | 4 +++- include/asm-arm/thread_info.h | 2 +- 4 files changed, 11 insertions(+), 13 deletions(-) diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c index 0abbce8c70bc..b324dcac1c56 100644 --- a/arch/arm/kernel/asm-offsets.c +++ b/arch/arm/kernel/asm-offsets.c @@ -57,7 +57,9 @@ int main(void) DEFINE(TI_TP_VALUE, offsetof(struct thread_info, tp_value)); DEFINE(TI_FPSTATE, offsetof(struct thread_info, fpstate)); DEFINE(TI_VFPSTATE, offsetof(struct thread_info, vfpstate)); - DEFINE(TI_IWMMXT_STATE, (offsetof(struct thread_info, fpstate)+4)&~7); +#ifdef CONFIG_IWMMXT + DEFINE(TI_IWMMXT_STATE, offsetof(struct thread_info, fpstate.iwmmxt)); +#endif BLANK(); DEFINE(S_R0, offsetof(struct pt_regs, ARM_r0)); DEFINE(S_R1, offsetof(struct pt_regs, ARM_r1)); diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index 7b6256bb590e..bc9e2f8ae326 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c @@ -610,15 +610,12 @@ static int ptrace_setfpregs(struct task_struct *tsk, void __user *ufp) static int ptrace_getwmmxregs(struct task_struct *tsk, void __user *ufp) { struct thread_info *thread = task_thread_info(tsk); - void *ptr = &thread->fpstate; if (!test_ti_thread_flag(thread, TIF_USING_IWMMXT)) return -ENODATA; iwmmxt_task_disable(thread); /* force it to ram */ - /* The iWMMXt state is stored doubleword-aligned. */ - if (((long) ptr) & 4) - ptr += 4; - return copy_to_user(ufp, ptr, 0x98) ? -EFAULT : 0; + return copy_to_user(ufp, &thread->fpstate.iwmmxt, IWMMXT_SIZE) + ? -EFAULT : 0; } /* @@ -627,15 +624,12 @@ static int ptrace_getwmmxregs(struct task_struct *tsk, void __user *ufp) static int ptrace_setwmmxregs(struct task_struct *tsk, void __user *ufp) { struct thread_info *thread = task_thread_info(tsk); - void *ptr = &thread->fpstate; if (!test_ti_thread_flag(thread, TIF_USING_IWMMXT)) return -EACCES; iwmmxt_task_release(thread); /* force a reload */ - /* The iWMMXt state is stored doubleword-aligned. */ - if (((long) ptr) & 4) - ptr += 4; - return copy_from_user(ptr, ufp, 0x98) ? -EFAULT : 0; + return copy_from_user(&thead->fpstate.iwmmxt, ufp, IWMMXT_SIZE) + ? -EFAULT : 0; } #endif diff --git a/include/asm-arm/fpstate.h b/include/asm-arm/fpstate.h index f7430e3aa55d..6246bf83627d 100644 --- a/include/asm-arm/fpstate.h +++ b/include/asm-arm/fpstate.h @@ -55,8 +55,10 @@ struct fp_soft_struct { unsigned int save[FP_SOFT_SIZE]; /* undefined information */ }; +#define IWMMXT_SIZE 0x98 + struct iwmmxt_struct { - unsigned int save[0x98/sizeof(int) + 1]; + unsigned int save[IWMMXT_SIZE / sizeof(unsigned int)]; }; union fp_state { diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h index 33a33cbb6329..cfbccb63c67b 100644 --- a/include/asm-arm/thread_info.h +++ b/include/asm-arm/thread_info.h @@ -59,7 +59,7 @@ struct thread_info { struct cpu_context_save cpu_context; /* cpu context */ __u8 used_cp[16]; /* thread used copro */ unsigned long tp_value; - union fp_state fpstate; + union fp_state fpstate __attribute__((aligned(8))); union vfp_state vfpstate; struct restart_block restart_block; }; -- cgit v1.2.2